754cf1192c3b28b40105a2793f4a50fec83129cc
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
103 #include "musb_core.h"
107 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
108 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110 #define MUSB_VERSION "6.0"
112 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114 #define MUSB_DRIVER_NAME "musb-hdrc"
115 const char musb_driver_name[] = MUSB_DRIVER_NAME;
117 MODULE_DESCRIPTION(DRIVER_INFO);
118 MODULE_AUTHOR(DRIVER_AUTHOR);
119 MODULE_LICENSE("GPL");
120 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122 u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
123 EXPORT_SYMBOL_GPL(musb_readb);
124 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
125 EXPORT_SYMBOL_GPL(musb_writeb);
127 /*-------------------------------------------------------------------------*/
129 static inline struct musb *dev_to_musb(struct device *dev)
130 {
131 return dev_get_drvdata(dev);
132 }
134 /*-------------------------------------------------------------------------*/
136 #ifndef CONFIG_BLACKFIN
138 /*
139 * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
140 */
141 static inline u8 __tusb_musb_readb(const void __iomem *addr, unsigned offset)
142 {
143 u16 tmp;
144 u8 val;
146 tmp = __raw_readw(addr + (offset & ~1));
147 if (offset & 1)
148 val = (tmp >> 8);
149 else
150 val = tmp & 0xff;
152 return val;
153 }
155 static inline void __tusb_musb_writeb(void __iomem *addr, unsigned offset,
156 u8 data)
157 {
158 u16 tmp;
160 tmp = __raw_readw(addr + (offset & ~1));
161 if (offset & 1)
162 tmp = (data << 8) | (tmp & 0xff);
163 else
164 tmp = (tmp & 0xff00) | data;
166 __raw_writew(tmp, addr + (offset & ~1));
167 }
169 static inline u8 __musb_readb(const void __iomem *addr, unsigned offset)
170 { return __raw_readb(addr + offset); }
172 static inline void __musb_writeb(void __iomem *addr, unsigned offset, u8 data)
173 { __raw_writeb(data, addr + offset); }
175 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
176 {
177 void __iomem *addr = otg->io_priv;
178 int i = 0;
179 u8 r;
180 u8 power;
182 /* Make sure the transceiver is not in low power mode */
183 power = musb_readb(addr, MUSB_POWER);
184 power &= ~MUSB_POWER_SUSPENDM;
185 musb_writeb(addr, MUSB_POWER, power);
187 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
188 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
189 */
191 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
192 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
193 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
195 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
196 & MUSB_ULPI_REG_CMPLT)) {
197 i++;
198 if (i == 10000)
199 return -ETIMEDOUT;
201 }
202 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
203 r &= ~MUSB_ULPI_REG_CMPLT;
204 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
206 return musb_readb(addr, MUSB_ULPI_REG_DATA);
207 }
209 static int musb_ulpi_write(struct otg_transceiver *otg,
210 u32 offset, u32 data)
211 {
212 void __iomem *addr = otg->io_priv;
213 int i = 0;
214 u8 r = 0;
215 u8 power;
217 /* Make sure the transceiver is not in low power mode */
218 power = musb_readb(addr, MUSB_POWER);
219 power &= ~MUSB_POWER_SUSPENDM;
220 musb_writeb(addr, MUSB_POWER, power);
222 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
223 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
224 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
226 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
227 & MUSB_ULPI_REG_CMPLT)) {
228 i++;
229 if (i == 10000)
230 return -ETIMEDOUT;
231 }
233 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
234 r &= ~MUSB_ULPI_REG_CMPLT;
235 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
237 return 0;
238 }
239 #else
240 static inline u8 __musb_readb(const void __iomem *addr, unsigned offset)
241 { return (u8) (bfin_read16(addr + offset)); }
243 static inline void __musb_writeb(void __iomem *addr, unsigned offset, u8 data)
244 { bfin_write16(addr + offset, (u16) data); }
246 #define musb_ulpi_read NULL
247 #define musb_ulpi_write NULL
248 #endif
250 static struct otg_io_access_ops musb_ulpi_access = {
251 .read = musb_ulpi_read,
252 .write = musb_ulpi_write,
253 };
255 /*
256 * Load an endpoint's FIFO
257 */
258 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
259 {
260 struct musb *musb = hw_ep->musb;
261 void __iomem *fifo = hw_ep->fifo;
263 prefetch((u8 *)src);
265 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
266 'T', hw_ep->epnum, fifo, len, src);
268 /* we can't assume unaligned reads work */
269 if (likely((0x01 & (unsigned long) src) == 0)) {
270 u16 index = 0;
272 /* best case is 32bit-aligned source address */
273 if ((0x02 & (unsigned long) src) == 0) {
274 if (len >= 4) {
275 writesl(fifo, src + index, len >> 2);
276 index += len & ~0x03;
277 }
278 if (len & 0x02) {
279 musb_writew(fifo, 0, *(u16 *)&src[index]);
280 index += 2;
281 }
282 } else {
283 if (len >= 2) {
284 writesw(fifo, src + index, len >> 1);
285 index += len & ~0x01;
286 }
287 }
288 if (len & 0x01)
289 musb_writeb(fifo, 0, src[index]);
290 } else {
291 /* byte aligned */
292 writesb(fifo, src, len);
293 }
294 }
295 EXPORT_SYMBOL_GPL(musb_write_fifo);
297 /*
298 * Unload an endpoint's FIFO
299 */
300 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
301 {
302 struct musb *musb = hw_ep->musb;
303 void __iomem *fifo = hw_ep->fifo;
305 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
306 'R', hw_ep->epnum, fifo, len, dst);
308 /* we can't assume unaligned writes work */
309 if (likely((0x01 & (unsigned long) dst) == 0)) {
310 u16 index = 0;
312 /* best case is 32bit-aligned destination address */
313 if ((0x02 & (unsigned long) dst) == 0) {
314 if (len >= 4) {
315 readsl(fifo, dst, len >> 2);
316 index = len & ~0x03;
317 }
318 if (len & 0x02) {
319 *(u16 *)&dst[index] = musb_readw(fifo, 0);
320 index += 2;
321 }
322 } else {
323 if (len >= 2) {
324 readsw(fifo, dst, len >> 1);
325 index = len & ~0x01;
326 }
327 }
328 if (len & 0x01)
329 dst[index] = musb_readb(fifo, 0);
330 } else {
331 /* byte aligned */
332 readsb(fifo, dst, len);
333 }
334 }
335 EXPORT_SYMBOL_GPL(musb_read_fifo);
337 /*-------------------------------------------------------------------------*/
339 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
340 static const u8 musb_test_packet[53] = {
341 /* implicit SYNC then DATA0 to start */
343 /* JKJKJKJK x9 */
344 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
345 /* JJKKJJKK x8 */
346 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
347 /* JJJJKKKK x8 */
348 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
349 /* JJJJJJJKKKKKKK x8 */
350 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
351 /* JJJJJJJK x8 */
352 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
353 /* JKKKKKKK x10, JK */
354 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
356 /* implicit CRC16 then EOP to end */
357 };
359 void musb_load_testpacket(struct musb *musb)
360 {
361 void __iomem *regs = musb->endpoints[0].regs;
363 musb_ep_select(musb, musb->mregs, 0);
364 musb->ops->write_fifo(musb->control_ep,
365 sizeof(musb_test_packet), musb_test_packet);
366 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
367 }
369 /*-------------------------------------------------------------------------*/
371 /*
372 * See also USB_OTG_1-3.pdf 6.6.5 Timers
373 * REVISIT: Are the other timers done in the hardware?
374 */
375 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
377 /*
378 * Handles OTG hnp timeouts, such as b_ase0_brst
379 */
380 void musb_otg_timer_func(unsigned long data)
381 {
382 struct musb *musb = (struct musb *)data;
383 unsigned long flags;
385 spin_lock_irqsave(&musb->lock, flags);
386 switch (musb->xceiv->state) {
387 case OTG_STATE_B_WAIT_ACON:
388 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
389 musb_g_disconnect(musb);
390 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
391 musb->is_active = 0;
392 break;
393 case OTG_STATE_A_WAIT_BCON:
394 dev_dbg(musb->controller, "HNP: a_wait_bcon timeout; back to a_host\n");
395 musb_hnp_stop(musb);
396 break;
397 default:
398 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
399 otg_state_string(musb->xceiv->state));
400 }
401 musb->ignore_disconnect = 0;
402 spin_unlock_irqrestore(&musb->lock, flags);
403 }
405 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
407 /*
408 * Stops the B-device HNP state. Caller must take care of locking.
409 */
410 void musb_hnp_stop(struct musb *musb)
411 {
412 struct usb_hcd *hcd = musb_to_hcd(musb);
413 void __iomem *mbase = musb->mregs;
414 u8 reg;
416 switch (musb->xceiv->state) {
417 case OTG_STATE_A_PERIPHERAL:
418 case OTG_STATE_A_WAIT_VFALL:
419 case OTG_STATE_A_WAIT_BCON:
420 dev_dbg(musb->controller, "HNP: Switching back to A-host\n");
421 musb_g_disconnect(musb);
422 musb->xceiv->state = OTG_STATE_A_IDLE;
423 MUSB_HST_MODE(musb);
424 musb->is_active = 0;
425 break;
426 case OTG_STATE_B_HOST:
427 dev_dbg(musb->controller, "HNP: Disabling HR\n");
428 hcd->self.is_b_host = 0;
429 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
430 MUSB_DEV_MODE(musb);
431 reg = musb_readb(mbase, MUSB_POWER);
432 reg |= MUSB_POWER_SUSPENDM;
433 musb_writeb(mbase, MUSB_POWER, reg);
434 /* REVISIT: Start SESSION_REQUEST here? */
435 break;
436 default:
437 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
438 otg_state_string(musb->xceiv->state));
439 }
441 /*
442 * When returning to A state after HNP, avoid hub_port_rebounce(),
443 * which cause occasional OPT A "Did not receive reset after connect"
444 * errors.
445 */
446 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
447 }
449 /*
450 * Interrupt Service Routine to record USB "global" interrupts.
451 * Since these do not happen often and signify things of
452 * paramount importance, it seems OK to check them individually;
453 * the order of the tests is specified in the manual
454 *
455 * @param musb instance pointer
456 * @param int_usb register contents
457 * @param devctl
458 * @param power
459 */
461 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
462 u8 devctl, u8 power)
463 {
464 irqreturn_t handled = IRQ_NONE;
466 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
467 int_usb);
469 /* in host mode, the peripheral may issue remote wakeup.
470 * in peripheral mode, the host may resume the link.
471 * spurious RESUME irqs happen too, paired with SUSPEND.
472 */
473 if (int_usb & MUSB_INTR_RESUME) {
474 handled = IRQ_HANDLED;
475 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
477 if (devctl & MUSB_DEVCTL_HM) {
478 void __iomem *mbase = musb->mregs;
480 switch (musb->xceiv->state) {
481 case OTG_STATE_A_SUSPEND:
482 /* remote wakeup? later, GetPortStatus
483 * will stop RESUME signaling
484 */
486 if (power & MUSB_POWER_SUSPENDM) {
487 /* spurious */
488 musb->int_usb &= ~MUSB_INTR_SUSPEND;
489 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
490 break;
491 }
493 power &= ~MUSB_POWER_SUSPENDM;
494 musb_writeb(mbase, MUSB_POWER,
495 power | MUSB_POWER_RESUME);
497 musb->port1_status |=
498 (USB_PORT_STAT_C_SUSPEND << 16)
499 | MUSB_PORT_STAT_RESUME;
500 musb->rh_timer = jiffies
501 + msecs_to_jiffies(20);
503 musb->xceiv->state = OTG_STATE_A_HOST;
504 musb->is_active = 1;
505 usb_hcd_resume_root_hub(musb_to_hcd(musb));
506 break;
507 case OTG_STATE_B_WAIT_ACON:
508 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
509 musb->is_active = 1;
510 MUSB_DEV_MODE(musb);
511 break;
512 default:
513 WARNING("bogus %s RESUME (%s)\n",
514 "host",
515 otg_state_string(musb->xceiv->state));
516 }
517 } else {
518 switch (musb->xceiv->state) {
519 case OTG_STATE_A_SUSPEND:
520 /* possibly DISCONNECT is upcoming */
521 musb->xceiv->state = OTG_STATE_A_HOST;
522 usb_hcd_resume_root_hub(musb_to_hcd(musb));
523 break;
524 case OTG_STATE_B_WAIT_ACON:
525 case OTG_STATE_B_PERIPHERAL:
526 /* disconnect while suspended? we may
527 * not get a disconnect irq...
528 */
529 if ((devctl & MUSB_DEVCTL_VBUS)
530 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
531 ) {
532 musb->int_usb |= MUSB_INTR_DISCONNECT;
533 musb->int_usb &= ~MUSB_INTR_SUSPEND;
534 break;
535 }
536 musb_g_resume(musb);
537 break;
538 case OTG_STATE_B_IDLE:
539 musb->int_usb &= ~MUSB_INTR_SUSPEND;
540 break;
541 default:
542 WARNING("bogus %s RESUME (%s)\n",
543 "peripheral",
544 otg_state_string(musb->xceiv->state));
545 }
546 }
547 }
549 /* see manual for the order of the tests */
550 if (int_usb & MUSB_INTR_SESSREQ) {
551 void __iomem *mbase = musb->mregs;
553 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
554 && (devctl & MUSB_DEVCTL_BDEVICE)) {
555 dev_dbg(musb->controller, "SessReq while on B state\n");
556 return IRQ_HANDLED;
557 }
559 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
560 otg_state_string(musb->xceiv->state));
562 /* IRQ arrives from ID pin sense or (later, if VBUS power
563 * is removed) SRP. responses are time critical:
564 * - turn on VBUS (with silicon-specific mechanism)
565 * - go through A_WAIT_VRISE
566 * - ... to A_WAIT_BCON.
567 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
568 */
569 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
570 musb->ep0_stage = MUSB_EP0_START;
571 musb->xceiv->state = OTG_STATE_A_IDLE;
572 MUSB_HST_MODE(musb);
573 musb_platform_set_vbus(musb, 1);
575 handled = IRQ_HANDLED;
576 }
578 if (int_usb & MUSB_INTR_VBUSERROR) {
579 int ignore = 0;
581 /* During connection as an A-Device, we may see a short
582 * current spikes causing voltage drop, because of cable
583 * and peripheral capacitance combined with vbus draw.
584 * (So: less common with truly self-powered devices, where
585 * vbus doesn't act like a power supply.)
586 *
587 * Such spikes are short; usually less than ~500 usec, max
588 * of ~2 msec. That is, they're not sustained overcurrent
589 * errors, though they're reported using VBUSERROR irqs.
590 *
591 * Workarounds: (a) hardware: use self powered devices.
592 * (b) software: ignore non-repeated VBUS errors.
593 *
594 * REVISIT: do delays from lots of DEBUG_KERNEL checks
595 * make trouble here, keeping VBUS < 4.4V ?
596 */
597 switch (musb->xceiv->state) {
598 case OTG_STATE_A_HOST:
599 /* recovery is dicey once we've gotten past the
600 * initial stages of enumeration, but if VBUS
601 * stayed ok at the other end of the link, and
602 * another reset is due (at least for high speed,
603 * to redo the chirp etc), it might work OK...
604 */
605 case OTG_STATE_A_WAIT_BCON:
606 case OTG_STATE_A_WAIT_VRISE:
607 if (musb->vbuserr_retry) {
608 void __iomem *mbase = musb->mregs;
610 musb->vbuserr_retry--;
611 ignore = 1;
612 devctl |= MUSB_DEVCTL_SESSION;
613 musb_writeb(mbase, MUSB_DEVCTL, devctl);
614 } else {
615 musb->port1_status |=
616 USB_PORT_STAT_OVERCURRENT
617 | (USB_PORT_STAT_C_OVERCURRENT << 16);
618 }
619 break;
620 default:
621 break;
622 }
624 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
625 otg_state_string(musb->xceiv->state),
626 devctl,
627 ({ char *s;
628 switch (devctl & MUSB_DEVCTL_VBUS) {
629 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
630 s = "<SessEnd"; break;
631 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
632 s = "<AValid"; break;
633 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
634 s = "<VBusValid"; break;
635 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
636 default:
637 s = "VALID"; break;
638 }; s; }),
639 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
640 musb->port1_status);
642 /* go through A_WAIT_VFALL then start a new session */
643 if (!ignore)
644 musb_platform_set_vbus(musb, 0);
645 handled = IRQ_HANDLED;
646 }
648 if (int_usb & MUSB_INTR_SUSPEND) {
649 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
650 otg_state_string(musb->xceiv->state), devctl, power);
651 handled = IRQ_HANDLED;
653 switch (musb->xceiv->state) {
654 case OTG_STATE_A_PERIPHERAL:
655 /*
656 * We cannot stop HNP here, devctl BDEVICE might be
657 * still set.
658 */
659 break;
660 case OTG_STATE_B_IDLE:
661 if (!musb->is_active)
662 break;
663 case OTG_STATE_B_PERIPHERAL:
664 musb_g_suspend(musb);
665 musb->is_active = is_otg_enabled(musb)
666 && musb->xceiv->gadget->b_hnp_enable;
667 if (musb->is_active) {
668 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
669 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
670 musb_otg_timer.data = (unsigned long)musb;
671 mod_timer(&musb_otg_timer, jiffies
672 + msecs_to_jiffies(TB_ASE0_BRST));
673 }
674 break;
675 case OTG_STATE_A_WAIT_BCON:
676 if (musb->a_wait_bcon != 0)
677 musb_platform_try_idle(musb, jiffies
678 + msecs_to_jiffies(musb->a_wait_bcon));
679 break;
680 case OTG_STATE_A_HOST:
681 musb->xceiv->state = OTG_STATE_A_SUSPEND;
682 musb->is_active = is_otg_enabled(musb)
683 && musb->xceiv->host->b_hnp_enable;
684 break;
685 case OTG_STATE_B_HOST:
686 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
687 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
688 break;
689 default:
690 /* "should not happen" */
691 musb->is_active = 0;
692 break;
693 }
694 }
696 if (int_usb & MUSB_INTR_CONNECT) {
697 struct usb_hcd *hcd = musb_to_hcd(musb);
699 handled = IRQ_HANDLED;
700 musb->is_active = 1;
701 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
703 musb->ep0_stage = MUSB_EP0_START;
705 /* flush endpoints when transitioning from Device Mode */
706 if (is_peripheral_active(musb)) {
707 /* REVISIT HNP; just force disconnect */
708 }
709 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
710 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
711 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
712 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
713 |USB_PORT_STAT_HIGH_SPEED
714 |USB_PORT_STAT_ENABLE
715 );
716 musb->port1_status |= USB_PORT_STAT_CONNECTION
717 |(USB_PORT_STAT_C_CONNECTION << 16);
719 /* high vs full speed is just a guess until after reset */
720 if (devctl & MUSB_DEVCTL_LSDEV)
721 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
723 if (hcd->status_urb)
724 usb_hcd_poll_rh_status(hcd);
725 else
726 usb_hcd_resume_root_hub(hcd);
728 MUSB_HST_MODE(musb);
730 /* indicate new connection to OTG machine */
731 switch (musb->xceiv->state) {
732 case OTG_STATE_B_PERIPHERAL:
733 if (int_usb & MUSB_INTR_SUSPEND) {
734 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
735 musb->xceiv->state = OTG_STATE_B_HOST;
736 hcd->self.is_b_host = 1;
737 int_usb &= ~MUSB_INTR_SUSPEND;
738 } else
739 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
740 break;
741 case OTG_STATE_B_WAIT_ACON:
742 dev_dbg(musb->controller, "HNP: Waiting to switch to b_host state\n");
743 musb->xceiv->state = OTG_STATE_B_HOST;
744 hcd->self.is_b_host = 1;
745 break;
746 default:
747 if ((devctl & MUSB_DEVCTL_VBUS)
748 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
749 musb->xceiv->state = OTG_STATE_A_HOST;
750 hcd->self.is_b_host = 0;
751 }
752 break;
753 }
755 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
756 otg_state_string(musb->xceiv->state), devctl);
757 }
759 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
760 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
761 otg_state_string(musb->xceiv->state),
762 MUSB_MODE(musb), devctl);
763 handled = IRQ_HANDLED;
765 switch (musb->xceiv->state) {
766 case OTG_STATE_A_HOST:
767 case OTG_STATE_A_SUSPEND:
768 usb_hcd_resume_root_hub(musb_to_hcd(musb));
769 musb_root_disconnect(musb);
770 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
771 musb_platform_try_idle(musb, jiffies
772 + msecs_to_jiffies(musb->a_wait_bcon));
773 break;
774 case OTG_STATE_B_HOST:
775 musb_hnp_stop(musb);
776 break;
777 case OTG_STATE_A_PERIPHERAL:
778 musb_hnp_stop(musb);
779 musb_root_disconnect(musb);
780 /* FALLTHROUGH */
781 case OTG_STATE_B_WAIT_ACON:
782 /* FALLTHROUGH */
783 case OTG_STATE_B_PERIPHERAL:
784 case OTG_STATE_B_IDLE:
785 printk(KERN_INFO "musb %s gadget disconnected.\n",
786 musb->gadget_driver
787 ? musb->gadget_driver->driver.name
788 : "");
789 musb_g_disconnect(musb);
790 break;
791 default:
792 WARNING("unhandled DISCONNECT transition (%s)\n",
793 otg_state_string(musb->xceiv->state));
794 break;
795 }
796 }
798 /* mentor saves a bit: bus reset and babble share the same irq.
799 * only host sees babble; only peripheral sees bus reset.
800 */
801 if (int_usb & MUSB_INTR_RESET) {
802 handled = IRQ_HANDLED;
803 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
804 /*
805 * Looks like non-HS BABBLE can be ignored, but
806 * HS BABBLE is an error condition. For HS the solution
807 * is to avoid babble in the first place and fix what
808 * caused BABBLE. When HS BABBLE happens we can only
809 * stop the session.
810 */
811 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
812 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
813 else {
814 ERR("Stopping host session -- babble\n");
815 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
816 }
817 } else if (is_peripheral_capable()) {
818 dev_dbg(musb->controller, "BUS RESET as %s\n",
819 otg_state_string(musb->xceiv->state));
820 switch (musb->xceiv->state) {
821 case OTG_STATE_A_SUSPEND:
822 /* We need to ignore disconnect on suspend
823 * otherwise tusb 2.0 won't reconnect after a
824 * power cycle, which breaks otg compliance.
825 */
826 musb->ignore_disconnect = 1;
827 musb_g_reset(musb);
828 /* FALLTHROUGH */
829 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
830 dev_dbg(musb->controller, "HNP: Setting timer as %s\n",
831 otg_state_string(musb->xceiv->state));
832 musb_otg_timer.data = (unsigned long)musb;
833 mod_timer(&musb_otg_timer, jiffies
834 + msecs_to_jiffies(100));
835 break;
836 case OTG_STATE_A_PERIPHERAL:
837 musb_hnp_stop(musb);
838 break;
839 case OTG_STATE_B_WAIT_ACON:
840 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
841 otg_state_string(musb->xceiv->state));
842 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
843 musb_g_reset(musb);
844 break;
845 case OTG_STATE_B_IDLE:
846 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
847 /* FALLTHROUGH */
848 case OTG_STATE_B_PERIPHERAL:
849 musb_g_reset(musb);
850 break;
851 default:
852 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
853 otg_state_string(musb->xceiv->state));
854 }
855 }
856 }
858 #if 0
859 /* REVISIT ... this would be for multiplexing periodic endpoints, or
860 * supporting transfer phasing to prevent exceeding ISO bandwidth
861 * limits of a given frame or microframe.
862 *
863 * It's not needed for peripheral side, which dedicates endpoints;
864 * though it _might_ use SOF irqs for other purposes.
865 *
866 * And it's not currently needed for host side, which also dedicates
867 * endpoints, relies on TX/RX interval registers, and isn't claimed
868 * to support ISO transfers yet.
869 */
870 if (int_usb & MUSB_INTR_SOF) {
871 void __iomem *mbase = musb->mregs;
872 struct musb_hw_ep *ep;
873 u8 epnum;
874 u16 frame;
876 dev_dbg(musb->controller, "START_OF_FRAME\n");
877 handled = IRQ_HANDLED;
879 /* start any periodic Tx transfers waiting for current frame */
880 frame = musb_readw(mbase, MUSB_FRAME);
881 ep = musb->endpoints;
882 for (epnum = 1; (epnum < musb->nr_endpoints)
883 && (musb->epmask >= (1 << epnum));
884 epnum++, ep++) {
885 /*
886 * FIXME handle framecounter wraps (12 bits)
887 * eliminate duplicated StartUrb logic
888 */
889 if (ep->dwWaitFrame >= frame) {
890 ep->dwWaitFrame = 0;
891 pr_debug("SOF --> periodic TX%s on %d\n",
892 ep->tx_channel ? " DMA" : "",
893 epnum);
894 if (!ep->tx_channel)
895 musb_h_tx_start(musb, epnum);
896 else
897 cppi_hostdma_start(musb, epnum);
898 }
899 } /* end of for loop */
900 }
901 #endif
903 schedule_work(&musb->irq_work);
905 return handled;
906 }
908 /*-------------------------------------------------------------------------*/
910 /*
911 * Program the HDRC to start (enable interrupts, dma, etc.).
912 */
913 void musb_start(struct musb *musb)
914 {
915 void __iomem *regs = musb->mregs;
916 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
918 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
920 /* Set INT enable registers, enable interrupts */
921 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
922 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
923 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
925 musb_writeb(regs, MUSB_TESTMODE, 0);
927 /* put into basic highspeed mode and start session */
928 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
929 | MUSB_POWER_HSENAB
930 /* ENSUSPEND wedges tusb */
931 /* | MUSB_POWER_ENSUSPEND */
932 );
934 musb->is_active = 0;
935 devctl = musb_readb(regs, MUSB_DEVCTL);
936 devctl &= ~MUSB_DEVCTL_SESSION;
938 if (is_otg_enabled(musb)) {
939 /* session started after:
940 * (a) ID-grounded irq, host mode;
941 * (b) vbus present/connect IRQ, peripheral mode;
942 * (c) peripheral initiates, using SRP
943 */
944 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
945 musb->is_active = 1;
946 else
947 devctl |= MUSB_DEVCTL_SESSION;
949 } else if (is_host_enabled(musb)) {
950 /* assume ID pin is hard-wired to ground */
951 devctl |= MUSB_DEVCTL_SESSION;
953 } else /* peripheral is enabled */ {
954 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
955 musb->is_active = 1;
956 }
957 musb_platform_enable(musb);
958 musb_writeb(regs, MUSB_DEVCTL, devctl);
959 }
962 static void musb_generic_disable(struct musb *musb)
963 {
964 void __iomem *mbase = musb->mregs;
965 u16 temp;
967 /* disable interrupts */
968 musb_writeb(mbase, MUSB_INTRUSBE, 0);
969 musb_writew(mbase, MUSB_INTRTXE, 0);
970 musb_writew(mbase, MUSB_INTRRXE, 0);
972 /* off */
973 musb_writeb(mbase, MUSB_DEVCTL, 0);
975 /* flush pending interrupts */
976 temp = musb_readb(mbase, MUSB_INTRUSB);
977 temp = musb_readw(mbase, MUSB_INTRTX);
978 temp = musb_readw(mbase, MUSB_INTRRX);
980 }
982 /*
983 * Make the HDRC stop (disable interrupts, etc.);
984 * reversible by musb_start
985 * called on gadget driver unregister
986 * with controller locked, irqs blocked
987 * acts as a NOP unless some role activated the hardware
988 */
989 void musb_stop(struct musb *musb)
990 {
991 /* stop IRQs, timers, ... */
992 musb_platform_disable(musb);
993 musb_generic_disable(musb);
994 dev_dbg(musb->controller, "HDRC disabled\n");
996 /* FIXME
997 * - mark host and/or peripheral drivers unusable/inactive
998 * - disable DMA (and enable it in HdrcStart)
999 * - make sure we can musb_start() after musb_stop(); with
1000 * OTG mode, gadget driver module rmmod/modprobe cycles that
1001 * - ...
1002 */
1003 musb_platform_try_idle(musb, 0);
1004 }
1006 static void musb_shutdown(struct platform_device *pdev)
1007 {
1008 struct musb *musb = dev_to_musb(&pdev->dev);
1009 unsigned long flags;
1011 pm_runtime_get_sync(musb->controller);
1012 spin_lock_irqsave(&musb->lock, flags);
1013 musb_platform_disable(musb);
1014 musb_generic_disable(musb);
1015 spin_unlock_irqrestore(&musb->lock, flags);
1017 if (!is_otg_enabled(musb) && is_host_enabled(musb))
1018 usb_remove_hcd(musb_to_hcd(musb));
1019 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1020 musb_platform_exit(musb);
1022 pm_runtime_put(musb->controller);
1023 /* FIXME power down */
1024 }
1027 /*-------------------------------------------------------------------------*/
1029 /*
1030 * The silicon either has hard-wired endpoint configurations, or else
1031 * "dynamic fifo" sizing. The driver has support for both, though at this
1032 * writing only the dynamic sizing is very well tested. Since we switched
1033 * away from compile-time hardware parameters, we can no longer rely on
1034 * dead code elimination to leave only the relevant one in the object file.
1035 *
1036 * We don't currently use dynamic fifo setup capability to do anything
1037 * more than selecting one of a bunch of predefined configurations.
1038 */
1039 static short __devinitdata fifo_mode = -1;
1041 /* "modprobe ... fifo_mode=1" etc */
1042 module_param(fifo_mode, short, 0);
1043 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1045 /*
1046 * tables defining fifo_mode values. define more if you like.
1047 * for host side, make sure both halves of ep1 are set up.
1048 */
1050 /* mode 0 - fits in 2KB */
1051 static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = {
1052 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1053 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1054 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1055 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1056 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1057 };
1059 /* mode 1 - fits in 4KB */
1060 static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = {
1061 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1062 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1063 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1064 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1065 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1066 };
1068 /* mode 2 - fits in 4KB */
1069 static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = {
1070 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1071 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1072 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1073 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1074 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1075 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1076 };
1078 /* mode 3 - fits in 4KB */
1079 static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = {
1080 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1081 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1082 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1083 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1084 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1085 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1086 };
1088 /* mode 4 - fits in 16KB */
1089 static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = {
1090 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1091 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1092 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1093 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1094 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1095 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1096 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1097 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1098 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1099 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1100 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1101 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1102 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1103 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1104 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1105 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1106 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1107 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1108 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1109 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1110 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1111 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1112 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1113 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1114 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1115 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1116 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1117 };
1119 /* mode 5 - fits in 8KB */
1120 static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = {
1121 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1122 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1123 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1124 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1125 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1126 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1127 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1128 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1129 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1130 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1131 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1132 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1133 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1134 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1135 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1136 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1137 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1138 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1139 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1140 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1141 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1142 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1143 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1144 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1145 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1146 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1147 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1148 };
1150 /*
1151 * configure a fifo; for non-shared endpoints, this may be called
1152 * once for a tx fifo and once for an rx fifo.
1153 *
1154 * returns negative errno or offset for next fifo.
1155 */
1156 static int __devinit
1157 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1158 const struct musb_fifo_cfg *cfg, u16 offset)
1159 {
1160 void __iomem *mbase = musb->mregs;
1161 int size = 0;
1162 u16 maxpacket = cfg->maxpacket;
1163 u16 c_off = offset >> 3;
1164 u8 c_size;
1166 /* expect hw_ep has already been zero-initialized */
1168 size = ffs(max(maxpacket, (u16) 8)) - 1;
1169 maxpacket = 1 << size;
1171 c_size = size - 3;
1172 if (cfg->mode == BUF_DOUBLE) {
1173 if ((offset + (maxpacket << 1)) >
1174 (1 << (musb->config->ram_bits + 2)))
1175 return -EMSGSIZE;
1176 c_size |= MUSB_FIFOSZ_DPB;
1177 } else {
1178 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1179 return -EMSGSIZE;
1180 }
1182 /* configure the FIFO */
1183 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1185 /* EP0 reserved endpoint for control, bidirectional;
1186 * EP1 reserved for bulk, two unidirection halves.
1187 */
1188 if (hw_ep->epnum == 1)
1189 musb->bulk_ep = hw_ep;
1190 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1191 switch (cfg->style) {
1192 case FIFO_TX:
1193 musb_write_txfifosz(mbase, c_size);
1194 musb_write_txfifoadd(mbase, c_off);
1195 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1196 hw_ep->max_packet_sz_tx = maxpacket;
1197 break;
1198 case FIFO_RX:
1199 musb_write_rxfifosz(mbase, c_size);
1200 musb_write_rxfifoadd(mbase, c_off);
1201 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1202 hw_ep->max_packet_sz_rx = maxpacket;
1203 break;
1204 case FIFO_RXTX:
1205 musb_write_txfifosz(mbase, c_size);
1206 musb_write_txfifoadd(mbase, c_off);
1207 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1208 hw_ep->max_packet_sz_rx = maxpacket;
1210 musb_write_rxfifosz(mbase, c_size);
1211 musb_write_rxfifoadd(mbase, c_off);
1212 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1213 hw_ep->max_packet_sz_tx = maxpacket;
1215 hw_ep->is_shared_fifo = true;
1216 break;
1217 }
1219 /* NOTE rx and tx endpoint irqs aren't managed separately,
1220 * which happens to be ok
1221 */
1222 musb->epmask |= (1 << hw_ep->epnum);
1224 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1225 }
1227 static struct musb_fifo_cfg __devinitdata ep0_cfg = {
1228 .style = FIFO_RXTX, .maxpacket = 64,
1229 };
1231 static int __devinit ep_config_from_table(struct musb *musb)
1232 {
1233 const struct musb_fifo_cfg *cfg;
1234 unsigned i, n;
1235 int offset;
1236 struct musb_hw_ep *hw_ep = musb->endpoints;
1238 if (musb->config->fifo_cfg) {
1239 cfg = musb->config->fifo_cfg;
1240 n = musb->config->fifo_cfg_size;
1241 goto done;
1242 }
1244 switch (fifo_mode) {
1245 default:
1246 fifo_mode = 0;
1247 /* FALLTHROUGH */
1248 case 0:
1249 cfg = mode_0_cfg;
1250 n = ARRAY_SIZE(mode_0_cfg);
1251 break;
1252 case 1:
1253 cfg = mode_1_cfg;
1254 n = ARRAY_SIZE(mode_1_cfg);
1255 break;
1256 case 2:
1257 cfg = mode_2_cfg;
1258 n = ARRAY_SIZE(mode_2_cfg);
1259 break;
1260 case 3:
1261 cfg = mode_3_cfg;
1262 n = ARRAY_SIZE(mode_3_cfg);
1263 break;
1264 case 4:
1265 cfg = mode_4_cfg;
1266 n = ARRAY_SIZE(mode_4_cfg);
1267 break;
1268 case 5:
1269 cfg = mode_5_cfg;
1270 n = ARRAY_SIZE(mode_5_cfg);
1271 break;
1272 }
1274 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1275 musb_driver_name, fifo_mode);
1278 done:
1279 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1280 /* assert(offset > 0) */
1282 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1283 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1284 */
1286 for (i = 0; i < n; i++) {
1287 u8 epn = cfg->hw_ep_num;
1289 if (epn >= musb->config->num_eps) {
1290 pr_debug("%s: invalid ep %d\n",
1291 musb_driver_name, epn);
1292 return -EINVAL;
1293 }
1294 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1295 if (offset < 0) {
1296 pr_debug("%s: mem overrun, ep %d\n",
1297 musb_driver_name, epn);
1298 return -EINVAL;
1299 }
1300 epn++;
1301 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1302 }
1304 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1305 musb_driver_name,
1306 n + 1, musb->config->num_eps * 2 - 1,
1307 offset, (1 << (musb->config->ram_bits + 2)));
1309 if (!musb->bulk_ep) {
1310 pr_debug("%s: missing bulk\n", musb_driver_name);
1311 return -EINVAL;
1312 }
1314 return 0;
1315 }
1317 /*
1318 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1319 * @param musb the controller
1320 */
1321 static int __devinit ep_config_from_hw(struct musb *musb)
1322 {
1323 u8 epnum = 0;
1324 struct musb_hw_ep *hw_ep;
1325 void *mbase = musb->mregs;
1326 int ret = 0;
1328 dev_dbg(musb->controller, "<== static silicon ep config\n");
1330 /* FIXME pick up ep0 maxpacket size */
1332 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1333 musb_ep_select(musb, mbase, epnum);
1334 hw_ep = musb->endpoints + epnum;
1336 ret = musb_read_fifosize(musb, hw_ep, epnum);
1337 if (ret < 0)
1338 break;
1340 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1342 /* pick an RX/TX endpoint for bulk */
1343 if (hw_ep->max_packet_sz_tx < 512
1344 || hw_ep->max_packet_sz_rx < 512)
1345 continue;
1347 /* REVISIT: this algorithm is lazy, we should at least
1348 * try to pick a double buffered endpoint.
1349 */
1350 if (musb->bulk_ep)
1351 continue;
1352 musb->bulk_ep = hw_ep;
1353 }
1355 if (!musb->bulk_ep) {
1356 pr_debug("%s: missing bulk\n", musb_driver_name);
1357 return -EINVAL;
1358 }
1360 return 0;
1361 }
1363 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1365 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1366 * configure endpoints, or take their config from silicon
1367 */
1368 static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
1369 {
1370 u8 reg;
1371 char *type;
1372 char aInfo[90], aRevision[32], aDate[12];
1373 void __iomem *mbase = musb->mregs;
1374 int status = 0;
1375 int i;
1377 /* log core options (read using indexed model) */
1378 reg = musb_read_configdata(mbase);
1380 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1381 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1382 strcat(aInfo, ", dyn FIFOs");
1383 musb->dyn_fifo = true;
1384 }
1385 if (reg & MUSB_CONFIGDATA_MPRXE) {
1386 strcat(aInfo, ", bulk combine");
1387 musb->bulk_combine = true;
1388 }
1389 if (reg & MUSB_CONFIGDATA_MPTXE) {
1390 strcat(aInfo, ", bulk split");
1391 musb->bulk_split = true;
1392 }
1393 if (reg & MUSB_CONFIGDATA_HBRXE) {
1394 strcat(aInfo, ", HB-ISO Rx");
1395 musb->hb_iso_rx = true;
1396 }
1397 if (reg & MUSB_CONFIGDATA_HBTXE) {
1398 strcat(aInfo, ", HB-ISO Tx");
1399 musb->hb_iso_tx = true;
1400 }
1401 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1402 strcat(aInfo, ", SoftConn");
1404 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1405 musb_driver_name, reg, aInfo);
1407 aDate[0] = 0;
1408 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1409 musb->is_multipoint = 1;
1410 type = "M";
1411 } else {
1412 musb->is_multipoint = 0;
1413 type = "";
1414 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1415 printk(KERN_ERR
1416 "%s: kernel must blacklist external hubs\n",
1417 musb_driver_name);
1418 #endif
1419 }
1421 /* log release info */
1422 musb->hwvers = musb_read_hwvers(mbase);
1423 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1424 MUSB_HWVERS_MINOR(musb->hwvers),
1425 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1426 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1427 musb_driver_name, type, aRevision, aDate);
1429 /* configure ep0 */
1430 musb_configure_ep0(musb);
1432 /* discover endpoint configuration */
1433 musb->nr_endpoints = 1;
1434 musb->epmask = 1;
1436 if (musb->dyn_fifo)
1437 status = ep_config_from_table(musb);
1438 else
1439 status = ep_config_from_hw(musb);
1441 if (status < 0)
1442 return status;
1444 /* finish init, and print endpoint config */
1445 for (i = 0; i < musb->nr_endpoints; i++) {
1446 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1448 if (musb->ops->flags & MUSB_GLUE_TUSB_STYLE) {
1449 hw_ep->fifo = MUSB_TUSB_FIFO_OFFSET(i) + mbase;
1450 hw_ep->fifo_async = musb->async +
1451 0x400 + MUSB_TUSB_FIFO_OFFSET(i);
1452 hw_ep->fifo_sync = musb->sync +
1453 0x400 + MUSB_TUSB_FIFO_OFFSET(i);
1454 hw_ep->fifo_sync_va = musb->sync_va + 0x400 +
1455 MUSB_TUSB_FIFO_OFFSET(i);
1457 if (i == 0)
1458 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1459 else
1460 hw_ep->conf = mbase + 0x400 +
1461 (((i - 1) & 0xf) << 2);
1462 } else {
1463 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1464 }
1466 hw_ep->regs = MUSB_EP_OFFSET(musb, i, 0) + mbase;
1467 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1468 hw_ep->rx_reinit = 1;
1469 hw_ep->tx_reinit = 1;
1471 if (hw_ep->max_packet_sz_tx) {
1472 dev_dbg(musb->controller,
1473 "%s: hw_ep %d%s, %smax %d\n",
1474 musb_driver_name, i,
1475 hw_ep->is_shared_fifo ? "shared" : "tx",
1476 hw_ep->tx_double_buffered
1477 ? "doublebuffer, " : "",
1478 hw_ep->max_packet_sz_tx);
1479 }
1480 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1481 dev_dbg(musb->controller,
1482 "%s: hw_ep %d%s, %smax %d\n",
1483 musb_driver_name, i,
1484 "rx",
1485 hw_ep->rx_double_buffered
1486 ? "doublebuffer, " : "",
1487 hw_ep->max_packet_sz_rx);
1488 }
1489 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1490 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1491 }
1493 return 0;
1494 }
1496 /*-------------------------------------------------------------------------*/
1498 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1499 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
1501 static irqreturn_t generic_interrupt(int irq, void *__hci)
1502 {
1503 unsigned long flags;
1504 irqreturn_t retval = IRQ_NONE;
1505 struct musb *musb = __hci;
1507 spin_lock_irqsave(&musb->lock, flags);
1509 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1510 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1511 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1513 if (musb->int_usb || musb->int_tx || musb->int_rx)
1514 retval = musb_interrupt(musb);
1516 spin_unlock_irqrestore(&musb->lock, flags);
1518 return retval;
1519 }
1521 #else
1522 #define generic_interrupt NULL
1523 #endif
1525 /*
1526 * handle all the irqs defined by the HDRC core. for now we expect: other
1527 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1528 * will be assigned, and the irq will already have been acked.
1529 *
1530 * called in irq context with spinlock held, irqs blocked
1531 */
1532 irqreturn_t musb_interrupt(struct musb *musb)
1533 {
1534 irqreturn_t retval = IRQ_NONE;
1535 u8 devctl, power;
1536 int ep_num;
1537 u32 reg;
1539 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1540 power = musb_readb(musb->mregs, MUSB_POWER);
1542 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1543 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1544 musb->int_usb, musb->int_tx, musb->int_rx);
1546 /* the core can interrupt us for multiple reasons; docs have
1547 * a generic interrupt flowchart to follow
1548 */
1549 if (musb->int_usb)
1550 retval |= musb_stage0_irq(musb, musb->int_usb,
1551 devctl, power);
1553 /* "stage 1" is handling endpoint irqs */
1555 /* handle endpoint 0 first */
1556 if (musb->int_tx & 1) {
1557 if (devctl & MUSB_DEVCTL_HM)
1558 retval |= musb_h_ep0_irq(musb);
1559 else
1560 retval |= musb_g_ep0_irq(musb);
1561 }
1563 /* RX on endpoints 1-15 */
1564 reg = musb->int_rx >> 1;
1565 ep_num = 1;
1566 while (reg) {
1567 if (reg & 1) {
1568 /* musb_ep_select(musb, musb->mregs, ep_num); */
1569 /* REVISIT just retval = ep->rx_irq(...) */
1570 retval = IRQ_HANDLED;
1571 if (devctl & MUSB_DEVCTL_HM) {
1572 if (is_host_capable())
1573 musb_host_rx(musb, ep_num);
1574 } else {
1575 if (is_peripheral_capable())
1576 musb_g_rx(musb, ep_num);
1577 }
1578 }
1580 reg >>= 1;
1581 ep_num++;
1582 }
1584 /* TX on endpoints 1-15 */
1585 reg = musb->int_tx >> 1;
1586 ep_num = 1;
1587 while (reg) {
1588 if (reg & 1) {
1589 /* musb_ep_select(musb, musb->mregs, ep_num); */
1590 /* REVISIT just retval |= ep->tx_irq(...) */
1591 retval = IRQ_HANDLED;
1592 if (devctl & MUSB_DEVCTL_HM) {
1593 if (is_host_capable())
1594 musb_host_tx(musb, ep_num);
1595 } else {
1596 if (is_peripheral_capable())
1597 musb_g_tx(musb, ep_num);
1598 }
1599 }
1600 reg >>= 1;
1601 ep_num++;
1602 }
1604 return retval;
1605 }
1606 EXPORT_SYMBOL_GPL(musb_interrupt);
1608 #ifndef CONFIG_MUSB_PIO_ONLY
1609 static int __devinitdata use_dma = 1;
1611 /* "modprobe ... use_dma=0" etc */
1612 module_param(use_dma, bool, 0);
1613 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1615 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1616 {
1617 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1619 /* called with controller lock already held */
1621 if (!epnum) {
1622 if (!tusb_dma_omap(musb) && !is_cppi_enabled(musb)) {
1623 /* endpoint 0 */
1624 if (devctl & MUSB_DEVCTL_HM)
1625 musb_h_ep0_irq(musb);
1626 else
1627 musb_g_ep0_irq(musb);
1628 }
1629 } else {
1630 /* endpoints 1..15 */
1631 if (transmit) {
1632 if (devctl & MUSB_DEVCTL_HM) {
1633 if (is_host_capable())
1634 musb_host_tx(musb, epnum);
1635 } else {
1636 if (is_peripheral_capable())
1637 musb_g_tx(musb, epnum);
1638 }
1639 } else {
1640 /* receive */
1641 if (devctl & MUSB_DEVCTL_HM) {
1642 if (is_host_capable())
1643 musb_host_rx(musb, epnum);
1644 } else {
1645 if (is_peripheral_capable())
1646 musb_g_rx(musb, epnum);
1647 }
1648 }
1649 }
1650 }
1651 EXPORT_SYMBOL_GPL(musb_dma_completion);
1653 #else
1654 #define use_dma 0
1655 #endif
1657 /*-------------------------------------------------------------------------*/
1659 #ifdef CONFIG_SYSFS
1661 static ssize_t
1662 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1663 {
1664 struct musb *musb = dev_to_musb(dev);
1665 unsigned long flags;
1666 int ret = -EINVAL;
1668 spin_lock_irqsave(&musb->lock, flags);
1669 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1670 spin_unlock_irqrestore(&musb->lock, flags);
1672 return ret;
1673 }
1675 static ssize_t
1676 musb_mode_store(struct device *dev, struct device_attribute *attr,
1677 const char *buf, size_t n)
1678 {
1679 struct musb *musb = dev_to_musb(dev);
1680 unsigned long flags;
1681 int status;
1683 spin_lock_irqsave(&musb->lock, flags);
1684 if (sysfs_streq(buf, "host"))
1685 status = musb_platform_set_mode(musb, MUSB_HOST);
1686 else if (sysfs_streq(buf, "peripheral"))
1687 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1688 else if (sysfs_streq(buf, "otg"))
1689 status = musb_platform_set_mode(musb, MUSB_OTG);
1690 else
1691 status = -EINVAL;
1692 spin_unlock_irqrestore(&musb->lock, flags);
1694 return (status == 0) ? n : status;
1695 }
1696 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1698 static ssize_t
1699 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1700 const char *buf, size_t n)
1701 {
1702 struct musb *musb = dev_to_musb(dev);
1703 unsigned long flags;
1704 unsigned long val;
1706 if (sscanf(buf, "%lu", &val) < 1) {
1707 dev_err(dev, "Invalid VBUS timeout ms value\n");
1708 return -EINVAL;
1709 }
1711 spin_lock_irqsave(&musb->lock, flags);
1712 musb->a_wait_bcon = val;
1713 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1714 musb->is_active = 0;
1715 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1716 spin_unlock_irqrestore(&musb->lock, flags);
1718 return n;
1719 }
1721 static ssize_t
1722 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1723 {
1724 struct musb *musb = dev_to_musb(dev);
1725 unsigned long flags;
1726 unsigned long val;
1727 int vbus;
1729 spin_lock_irqsave(&musb->lock, flags);
1730 val = musb->a_wait_bcon;
1731 vbus = musb_platform_get_vbus_status(musb);
1732 spin_unlock_irqrestore(&musb->lock, flags);
1734 return sprintf(buf, "Vbus %s, timeout %lu\n",
1735 vbus ? "on" : "off", val);
1736 }
1737 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1739 /* Gadget drivers can't know that a host is connected so they might want
1740 * to start SRP, but users can. This allows userspace to trigger SRP.
1741 */
1742 static ssize_t
1743 musb_srp_store(struct device *dev, struct device_attribute *attr,
1744 const char *buf, size_t n)
1745 {
1746 struct musb *musb = dev_to_musb(dev);
1747 unsigned short srp;
1749 if (sscanf(buf, "%hu", &srp) != 1
1750 || (srp != 1)) {
1751 dev_err(dev, "SRP: Value must be 1\n");
1752 return -EINVAL;
1753 }
1755 if (srp == 1)
1756 musb_g_wakeup(musb);
1758 return n;
1759 }
1760 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1762 static struct attribute *musb_attributes[] = {
1763 &dev_attr_mode.attr,
1764 &dev_attr_vbus.attr,
1765 &dev_attr_srp.attr,
1766 NULL
1767 };
1769 static const struct attribute_group musb_attr_group = {
1770 .attrs = musb_attributes,
1771 };
1773 #endif /* sysfs */
1775 /* Only used to provide driver mode change events */
1776 static void musb_irq_work(struct work_struct *data)
1777 {
1778 struct musb *musb = container_of(data, struct musb, irq_work);
1779 static int old_state;
1781 if (musb->xceiv->state != old_state) {
1782 old_state = musb->xceiv->state;
1783 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1784 }
1785 }
1787 /* --------------------------------------------------------------------------
1788 * Init support
1789 */
1791 static struct musb *__devinit
1792 allocate_instance(struct device *dev,
1793 struct musb_hdrc_config *config, void __iomem *mbase)
1794 {
1795 struct musb *musb;
1796 struct musb_hw_ep *ep;
1797 int epnum;
1798 struct usb_hcd *hcd;
1800 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1801 if (!hcd)
1802 return NULL;
1803 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1805 musb = hcd_to_musb(hcd);
1806 INIT_LIST_HEAD(&musb->control);
1807 INIT_LIST_HEAD(&musb->in_bulk);
1808 INIT_LIST_HEAD(&musb->out_bulk);
1810 hcd->uses_new_polling = 1;
1811 hcd->has_tt = 1;
1813 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1814 dev_set_drvdata(dev, musb);
1815 musb->mregs = mbase;
1816 musb->ctrl_base = mbase;
1817 musb->nIrq = -ENODEV;
1818 musb->config = config;
1819 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1820 for (epnum = 0, ep = musb->endpoints;
1821 epnum < musb->config->num_eps;
1822 epnum++, ep++) {
1823 ep->musb = musb;
1824 ep->epnum = epnum;
1825 }
1827 musb->controller = dev;
1829 return musb;
1830 }
1832 static void musb_free(struct musb *musb)
1833 {
1834 /* this has multiple entry modes. it handles fault cleanup after
1835 * probe(), where things may be partially set up, as well as rmmod
1836 * cleanup after everything's been de-activated.
1837 */
1839 #ifdef CONFIG_SYSFS
1840 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1841 #endif
1843 musb_gadget_cleanup(musb);
1845 if (musb->nIrq >= 0) {
1846 if (musb->irq_wake)
1847 disable_irq_wake(musb->nIrq);
1848 free_irq(musb->nIrq, musb);
1849 }
1850 if (is_dma_capable() && musb->dma_controller) {
1851 struct dma_controller *c = musb->dma_controller;
1853 (void) c->stop(c);
1854 musb->ops->dma_controller_destroy(c);
1855 }
1857 kfree(musb);
1858 }
1860 /*
1861 * Perform generic per-controller initialization.
1862 *
1863 * @pDevice: the controller (already clocked, etc)
1864 * @nIrq: irq
1865 * @mregs: virtual address of controller registers,
1866 * not yet corrected for platform-specific offsets
1867 */
1868 static int __devinit
1869 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1870 {
1871 int status;
1872 struct musb *musb;
1873 struct musb_hdrc_platform_data *plat = dev->platform_data;
1875 /* The driver might handle more features than the board; OK.
1876 * Fail when the board needs a feature that's not enabled.
1877 */
1878 if (!plat) {
1879 dev_dbg(dev, "no platform_data?\n");
1880 status = -ENODEV;
1881 goto fail0;
1882 }
1884 /* allocate */
1885 musb = allocate_instance(dev, plat->config, ctrl);
1886 if (!musb) {
1887 status = -ENOMEM;
1888 goto fail0;
1889 }
1891 pm_runtime_use_autosuspend(musb->controller);
1892 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1893 pm_runtime_enable(musb->controller);
1895 spin_lock_init(&musb->lock);
1896 musb->board_mode = plat->mode;
1897 musb->board_set_power = plat->set_power;
1898 musb->min_power = plat->min_power;
1899 musb->ops = plat->platform_ops;
1900 if (fifo_mode == -1)
1901 fifo_mode = musb->ops->fifo_mode;
1903 if (musb->ops->flags & MUSB_GLUE_TUSB_STYLE) {
1904 musb_readb = __tusb_musb_readb;
1905 musb_writeb = __tusb_musb_writeb;
1906 } else {
1907 musb_readb = __musb_readb;
1908 musb_writeb = __musb_writeb;
1909 }
1911 dev_info(dev, "dma type: %s\n", get_dma_name(musb));
1913 /* The musb_platform_init() call:
1914 * - adjusts musb->mregs and musb->isr if needed,
1915 * - may initialize an integrated tranceiver
1916 * - initializes musb->xceiv, usually by otg_get_transceiver()
1917 * - stops powering VBUS
1918 *
1919 * There are various transceiver configurations. Blackfin,
1920 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1921 * external/discrete ones in various flavors (twl4030 family,
1922 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1923 */
1924 musb->isr = generic_interrupt;
1925 status = musb_platform_init(musb);
1926 if (status < 0)
1927 goto fail1;
1929 if (!musb->isr) {
1930 status = -ENODEV;
1931 goto fail3;
1932 }
1934 if (!musb->xceiv->io_ops) {
1935 musb->xceiv->io_priv = musb->mregs;
1936 musb->xceiv->io_ops = &musb_ulpi_access;
1937 }
1939 #ifndef CONFIG_MUSB_PIO_ONLY
1940 if (use_dma && dev->dma_mask) {
1941 struct dma_controller *c;
1943 if (!musb->ops->dma_controller_create) {
1944 dev_err(dev, "no dma_controller_create for non-PIO mode!\n");
1945 status = -ENODEV;
1946 goto fail3;
1947 }
1948 c = musb->ops->dma_controller_create(musb, musb->mregs);
1949 musb->dma_controller = c;
1950 if (c)
1951 (void) c->start(c);
1952 }
1953 #endif
1954 /* ideally this would be abstracted in platform setup */
1955 if (!is_dma_capable() || !musb->dma_controller)
1956 dev->dma_mask = NULL;
1958 /* be sure interrupts are disabled before connecting ISR */
1959 musb_platform_disable(musb);
1960 musb_generic_disable(musb);
1962 /* setup musb parts of the core (especially endpoints) */
1963 status = musb_core_init(plat->config->multipoint
1964 ? MUSB_CONTROLLER_MHDRC
1965 : MUSB_CONTROLLER_HDRC, musb);
1966 if (status < 0)
1967 goto fail3;
1969 /* Init IRQ workqueue before request_irq */
1970 INIT_WORK(&musb->irq_work, musb_irq_work);
1972 /* attach to the IRQ */
1973 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1974 dev_err(dev, "request_irq %d failed!\n", nIrq);
1975 status = -ENODEV;
1976 goto fail3;
1977 }
1978 musb->nIrq = nIrq;
1979 /* FIXME this handles wakeup irqs wrong */
1980 if (enable_irq_wake(nIrq) == 0) {
1981 musb->irq_wake = 1;
1982 device_init_wakeup(dev, 1);
1983 } else {
1984 musb->irq_wake = 0;
1985 }
1987 /* host side needs more setup */
1988 if (is_host_enabled(musb)) {
1989 struct usb_hcd *hcd = musb_to_hcd(musb);
1991 otg_set_host(musb->xceiv, &hcd->self);
1993 if (is_otg_enabled(musb))
1994 hcd->self.otg_port = 1;
1995 musb->xceiv->host = &hcd->self;
1996 hcd->power_budget = 2 * (plat->power ? : 250);
1998 /* program PHY to use external vBus if required */
1999 if (plat->extvbus) {
2000 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2001 busctl |= MUSB_ULPI_USE_EXTVBUS;
2002 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2003 }
2004 }
2006 /* For the host-only role, we can activate right away.
2007 * (We expect the ID pin to be forcibly grounded!!)
2008 * Otherwise, wait till the gadget driver hooks up.
2009 */
2010 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2011 struct usb_hcd *hcd = musb_to_hcd(musb);
2013 MUSB_HST_MODE(musb);
2014 musb->xceiv->default_a = 1;
2015 musb->xceiv->state = OTG_STATE_A_IDLE;
2017 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2019 hcd->self.uses_pio_for_control = 1;
2020 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2021 "HOST", status,
2022 musb_readb(musb->mregs, MUSB_DEVCTL),
2023 (musb_readb(musb->mregs, MUSB_DEVCTL)
2024 & MUSB_DEVCTL_BDEVICE
2025 ? 'B' : 'A'));
2027 } else /* peripheral is enabled */ {
2028 MUSB_DEV_MODE(musb);
2029 musb->xceiv->default_a = 0;
2030 musb->xceiv->state = OTG_STATE_B_IDLE;
2032 status = musb_gadget_setup(musb);
2034 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2035 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2036 status,
2037 musb_readb(musb->mregs, MUSB_DEVCTL));
2039 }
2040 if (status < 0)
2041 goto fail3;
2043 status = musb_init_debugfs(musb);
2044 if (status < 0)
2045 goto fail4;
2047 #ifdef CONFIG_SYSFS
2048 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2049 if (status)
2050 goto fail5;
2051 #endif
2053 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2054 ({char *s;
2055 switch (musb->board_mode) {
2056 case MUSB_HOST: s = "Host"; break;
2057 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2058 default: s = "OTG"; break;
2059 }; s; }),
2060 ctrl,
2061 (is_dma_capable() && musb->dma_controller)
2062 ? "DMA" : "PIO",
2063 musb->nIrq);
2065 if (status == 0)
2066 musb_debug_create("driver/musb_hdrc", musb);
2068 return 0;
2070 fail5:
2071 musb_exit_debugfs(musb);
2073 fail4:
2074 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2075 usb_remove_hcd(musb_to_hcd(musb));
2076 else
2077 musb_gadget_cleanup(musb);
2079 fail3:
2080 if (musb->irq_wake)
2081 device_init_wakeup(dev, 0);
2082 musb_platform_exit(musb);
2084 fail1:
2085 dev_err(musb->controller,
2086 "musb_init_controller failed with status %d\n", status);
2088 musb_free(musb);
2090 fail0:
2092 return status;
2094 }
2096 /*-------------------------------------------------------------------------*/
2098 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2099 * bridge to a platform device; this driver then suffices.
2100 */
2102 #ifndef CONFIG_MUSB_PIO_ONLY
2103 static u64 *orig_dma_mask;
2104 #endif
2106 static int __devinit musb_probe(struct platform_device *pdev)
2107 {
2108 struct device *dev = &pdev->dev;
2109 int irq = platform_get_irq_byname(pdev, "mc");
2110 int status;
2111 struct resource *iomem;
2112 void __iomem *base;
2114 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2115 if (!iomem || irq <= 0)
2116 return -ENODEV;
2118 base = ioremap(iomem->start, resource_size(iomem));
2119 if (!base) {
2120 dev_err(dev, "ioremap failed\n");
2121 return -ENOMEM;
2122 }
2124 #ifndef CONFIG_MUSB_PIO_ONLY
2125 /* clobbered by use_dma=n */
2126 orig_dma_mask = dev->dma_mask;
2127 #endif
2128 status = musb_init_controller(dev, irq, base);
2129 if (status < 0)
2130 iounmap(base);
2132 return status;
2133 }
2135 static int __exit musb_remove(struct platform_device *pdev)
2136 {
2137 struct musb *musb = dev_to_musb(&pdev->dev);
2138 void __iomem *ctrl_base = musb->ctrl_base;
2140 /* this gets called on rmmod.
2141 * - Host mode: host may still be active
2142 * - Peripheral mode: peripheral is deactivated (or never-activated)
2143 * - OTG mode: both roles are deactivated (or never-activated)
2144 */
2145 pm_runtime_get_sync(musb->controller);
2146 musb_exit_debugfs(musb);
2147 musb_shutdown(pdev);
2148 musb_debug_delete("driver/musb_hdrc", musb);
2150 pm_runtime_put(musb->controller);
2151 musb_free(musb);
2152 iounmap(ctrl_base);
2153 device_init_wakeup(&pdev->dev, 0);
2154 #ifndef CONFIG_MUSB_PIO_ONLY
2155 pdev->dev.dma_mask = orig_dma_mask;
2156 #endif
2157 return 0;
2158 }
2160 #ifdef CONFIG_PM
2162 static void musb_save_context(struct musb *musb)
2163 {
2164 int i;
2165 void __iomem *musb_base = musb->mregs;
2166 void __iomem *epio;
2168 if (is_host_enabled(musb)) {
2169 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2170 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2171 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2172 }
2173 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2174 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2175 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2176 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2177 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2178 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2180 for (i = 0; i < musb->config->num_eps; ++i) {
2181 struct musb_hw_ep *hw_ep;
2183 hw_ep = &musb->endpoints[i];
2184 if (!hw_ep)
2185 continue;
2187 epio = hw_ep->regs;
2188 if (!epio)
2189 continue;
2191 musb_writeb(musb_base, MUSB_INDEX, i);
2192 musb->context.index_regs[i].txmaxp =
2193 musb_readw(epio, MUSB_TXMAXP);
2194 musb->context.index_regs[i].txcsr =
2195 musb_readw(epio, MUSB_TXCSR);
2196 musb->context.index_regs[i].rxmaxp =
2197 musb_readw(epio, MUSB_RXMAXP);
2198 musb->context.index_regs[i].rxcsr =
2199 musb_readw(epio, MUSB_RXCSR);
2201 if (musb->dyn_fifo) {
2202 musb->context.index_regs[i].txfifoadd =
2203 musb_read_txfifoadd(musb_base);
2204 musb->context.index_regs[i].rxfifoadd =
2205 musb_read_rxfifoadd(musb_base);
2206 musb->context.index_regs[i].txfifosz =
2207 musb_read_txfifosz(musb_base);
2208 musb->context.index_regs[i].rxfifosz =
2209 musb_read_rxfifosz(musb_base);
2210 }
2211 if (is_host_enabled(musb)) {
2212 musb->context.index_regs[i].txtype =
2213 musb_readb(epio, MUSB_TXTYPE);
2214 musb->context.index_regs[i].txinterval =
2215 musb_readb(epio, MUSB_TXINTERVAL);
2216 musb->context.index_regs[i].rxtype =
2217 musb_readb(epio, MUSB_RXTYPE);
2218 musb->context.index_regs[i].rxinterval =
2219 musb_readb(epio, MUSB_RXINTERVAL);
2221 musb->context.index_regs[i].txfunaddr =
2222 musb_read_txfunaddr(musb_base, i);
2223 musb->context.index_regs[i].txhubaddr =
2224 musb_read_txhubaddr(musb_base, i);
2225 musb->context.index_regs[i].txhubport =
2226 musb_read_txhubport(musb_base, i);
2228 musb->context.index_regs[i].rxfunaddr =
2229 musb_read_rxfunaddr(musb_base, i);
2230 musb->context.index_regs[i].rxhubaddr =
2231 musb_read_rxhubaddr(musb_base, i);
2232 musb->context.index_regs[i].rxhubport =
2233 musb_read_rxhubport(musb_base, i);
2234 }
2235 }
2236 }
2238 static void musb_restore_context(struct musb *musb)
2239 {
2240 int i;
2241 void __iomem *musb_base = musb->mregs;
2242 void __iomem *ep_target_regs;
2243 void __iomem *epio;
2245 if (is_host_enabled(musb)) {
2246 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2247 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2248 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2249 }
2250 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2251 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2252 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2253 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2254 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2256 for (i = 0; i < musb->config->num_eps; ++i) {
2257 struct musb_hw_ep *hw_ep;
2259 hw_ep = &musb->endpoints[i];
2260 if (!hw_ep)
2261 continue;
2263 epio = hw_ep->regs;
2264 if (!epio)
2265 continue;
2267 musb_writeb(musb_base, MUSB_INDEX, i);
2268 musb_writew(epio, MUSB_TXMAXP,
2269 musb->context.index_regs[i].txmaxp);
2270 musb_writew(epio, MUSB_TXCSR,
2271 musb->context.index_regs[i].txcsr);
2272 musb_writew(epio, MUSB_RXMAXP,
2273 musb->context.index_regs[i].rxmaxp);
2274 musb_writew(epio, MUSB_RXCSR,
2275 musb->context.index_regs[i].rxcsr);
2277 if (musb->dyn_fifo) {
2278 musb_write_txfifosz(musb_base,
2279 musb->context.index_regs[i].txfifosz);
2280 musb_write_rxfifosz(musb_base,
2281 musb->context.index_regs[i].rxfifosz);
2282 musb_write_txfifoadd(musb_base,
2283 musb->context.index_regs[i].txfifoadd);
2284 musb_write_rxfifoadd(musb_base,
2285 musb->context.index_regs[i].rxfifoadd);
2286 }
2288 if (is_host_enabled(musb)) {
2289 musb_writeb(epio, MUSB_TXTYPE,
2290 musb->context.index_regs[i].txtype);
2291 musb_writeb(epio, MUSB_TXINTERVAL,
2292 musb->context.index_regs[i].txinterval);
2293 musb_writeb(epio, MUSB_RXTYPE,
2294 musb->context.index_regs[i].rxtype);
2295 musb_writeb(epio, MUSB_RXINTERVAL,
2297 musb->context.index_regs[i].rxinterval);
2298 musb_write_txfunaddr(musb_base, i,
2299 musb->context.index_regs[i].txfunaddr);
2300 musb_write_txhubaddr(musb_base, i,
2301 musb->context.index_regs[i].txhubaddr);
2302 musb_write_txhubport(musb_base, i,
2303 musb->context.index_regs[i].txhubport);
2305 ep_target_regs =
2306 musb_read_target_reg_base(i, musb_base);
2308 musb_write_rxfunaddr(ep_target_regs,
2309 musb->context.index_regs[i].rxfunaddr);
2310 musb_write_rxhubaddr(ep_target_regs,
2311 musb->context.index_regs[i].rxhubaddr);
2312 musb_write_rxhubport(ep_target_regs,
2313 musb->context.index_regs[i].rxhubport);
2314 }
2315 }
2316 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2317 }
2319 static int musb_suspend(struct device *dev)
2320 {
2321 struct musb *musb = dev_to_musb(dev);
2322 unsigned long flags;
2324 spin_lock_irqsave(&musb->lock, flags);
2326 if (is_peripheral_active(musb)) {
2327 /* FIXME force disconnect unless we know USB will wake
2328 * the system up quickly enough to respond ...
2329 */
2330 } else if (is_host_active(musb)) {
2331 /* we know all the children are suspended; sometimes
2332 * they will even be wakeup-enabled.
2333 */
2334 }
2336 spin_unlock_irqrestore(&musb->lock, flags);
2337 return 0;
2338 }
2340 static int musb_resume_noirq(struct device *dev)
2341 {
2342 /* for static cmos like DaVinci, register values were preserved
2343 * unless for some reason the whole soc powered down or the USB
2344 * module got reset through the PSC (vs just being disabled).
2345 */
2346 return 0;
2347 }
2349 static int musb_runtime_suspend(struct device *dev)
2350 {
2351 struct musb *musb = dev_to_musb(dev);
2353 musb_save_context(musb);
2355 return 0;
2356 }
2358 static int musb_runtime_resume(struct device *dev)
2359 {
2360 struct musb *musb = dev_to_musb(dev);
2361 static int first = 1;
2363 /*
2364 * When pm_runtime_get_sync called for the first time in driver
2365 * init, some of the structure is still not initialized which is
2366 * used in restore function. But clock needs to be
2367 * enabled before any register access, so
2368 * pm_runtime_get_sync has to be called.
2369 * Also context restore without save does not make
2370 * any sense
2371 */
2372 if (!first)
2373 musb_restore_context(musb);
2374 first = 0;
2376 return 0;
2377 }
2379 static const struct dev_pm_ops musb_dev_pm_ops = {
2380 .suspend = musb_suspend,
2381 .resume_noirq = musb_resume_noirq,
2382 .runtime_suspend = musb_runtime_suspend,
2383 .runtime_resume = musb_runtime_resume,
2384 };
2386 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2387 #else
2388 #define MUSB_DEV_PM_OPS NULL
2389 #endif
2391 static struct platform_driver musb_driver = {
2392 .driver = {
2393 .name = (char *)musb_driver_name,
2394 .bus = &platform_bus_type,
2395 .owner = THIS_MODULE,
2396 .pm = MUSB_DEV_PM_OPS,
2397 },
2398 .probe = musb_probe,
2399 .remove = __exit_p(musb_remove),
2400 .shutdown = musb_shutdown,
2401 };
2403 /*-------------------------------------------------------------------------*/
2405 static int __init musb_init(void)
2406 {
2407 if (usb_disabled())
2408 return 0;
2410 pr_info("%s: version " MUSB_VERSION ", "
2411 "?dma?"
2412 ", "
2413 "otg (peripheral+host)",
2414 musb_driver_name);
2415 return platform_driver_register(&musb_driver);
2416 }
2418 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2419 * and before usb gadget and host-side drivers start to register
2420 */
2421 fs_initcall(musb_init);
2423 static void __exit musb_cleanup(void)
2424 {
2425 platform_driver_unregister(&musb_driver);
2426 }
2427 module_exit(musb_cleanup);