1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
103 #include "musb_core.h"
107 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
108 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110 #define MUSB_VERSION "6.0"
112 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114 #define MUSB_DRIVER_NAME "musb-hdrc"
115 const char musb_driver_name[] = MUSB_DRIVER_NAME;
117 MODULE_DESCRIPTION(DRIVER_INFO);
118 MODULE_AUTHOR(DRIVER_AUTHOR);
119 MODULE_LICENSE("GPL");
120 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122 u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
123 EXPORT_SYMBOL_GPL(musb_readb);
124 void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
125 EXPORT_SYMBOL_GPL(musb_writeb);
127 /*-------------------------------------------------------------------------*/
129 static inline struct musb *dev_to_musb(struct device *dev)
130 {
131 return dev_get_drvdata(dev);
132 }
134 /*-------------------------------------------------------------------------*/
136 #ifndef CONFIG_BLACKFIN
138 /*
139 * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
140 */
141 static inline u8 __tusb_musb_readb(const void __iomem *addr, unsigned offset)
142 {
143 u16 tmp;
144 u8 val;
146 tmp = __raw_readw(addr + (offset & ~1));
147 if (offset & 1)
148 val = (tmp >> 8);
149 else
150 val = tmp & 0xff;
152 return val;
153 }
155 static inline void __tusb_musb_writeb(void __iomem *addr, unsigned offset,
156 u8 data)
157 {
158 u16 tmp;
160 tmp = __raw_readw(addr + (offset & ~1));
161 if (offset & 1)
162 tmp = (data << 8) | (tmp & 0xff);
163 else
164 tmp = (tmp & 0xff00) | data;
166 __raw_writew(tmp, addr + (offset & ~1));
167 }
169 static inline u8 __musb_readb(const void __iomem *addr, unsigned offset)
170 { return __raw_readb(addr + offset); }
172 static inline void __musb_writeb(void __iomem *addr, unsigned offset, u8 data)
173 { __raw_writeb(data, addr + offset); }
175 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
176 {
177 void __iomem *addr = otg->io_priv;
178 int i = 0;
179 u8 r;
180 u8 power;
182 /* Make sure the transceiver is not in low power mode */
183 power = musb_readb(addr, MUSB_POWER);
184 power &= ~MUSB_POWER_SUSPENDM;
185 musb_writeb(addr, MUSB_POWER, power);
187 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
188 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
189 */
191 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
192 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
193 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
195 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
196 & MUSB_ULPI_REG_CMPLT)) {
197 i++;
198 if (i == 10000)
199 return -ETIMEDOUT;
201 }
202 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
203 r &= ~MUSB_ULPI_REG_CMPLT;
204 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
206 return musb_readb(addr, MUSB_ULPI_REG_DATA);
207 }
209 static int musb_ulpi_write(struct otg_transceiver *otg,
210 u32 offset, u32 data)
211 {
212 void __iomem *addr = otg->io_priv;
213 int i = 0;
214 u8 r = 0;
215 u8 power;
217 /* Make sure the transceiver is not in low power mode */
218 power = musb_readb(addr, MUSB_POWER);
219 power &= ~MUSB_POWER_SUSPENDM;
220 musb_writeb(addr, MUSB_POWER, power);
222 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
223 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
224 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
226 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
227 & MUSB_ULPI_REG_CMPLT)) {
228 i++;
229 if (i == 10000)
230 return -ETIMEDOUT;
231 }
233 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
234 r &= ~MUSB_ULPI_REG_CMPLT;
235 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
237 return 0;
238 }
239 #else
240 static inline u8 __musb_readb(const void __iomem *addr, unsigned offset)
241 { return (u8) (bfin_read16(addr + offset)); }
243 static inline void __musb_writeb(void __iomem *addr, unsigned offset, u8 data)
244 { bfin_write16(addr + offset, (u16) data); }
246 #define musb_ulpi_read NULL
247 #define musb_ulpi_write NULL
248 #endif
250 static struct otg_io_access_ops musb_ulpi_access = {
251 .read = musb_ulpi_read,
252 .write = musb_ulpi_write,
253 };
255 /*
256 * Load an endpoint's FIFO
257 */
258 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
259 {
260 struct musb *musb = hw_ep->musb;
261 void __iomem *fifo = hw_ep->fifo;
263 prefetch((u8 *)src);
265 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
266 'T', hw_ep->epnum, fifo, len, src);
268 /* we can't assume unaligned reads work */
269 if (likely((0x01 & (unsigned long) src) == 0)) {
270 u16 index = 0;
272 /* best case is 32bit-aligned source address */
273 if ((0x02 & (unsigned long) src) == 0) {
274 if (len >= 4) {
275 writesl(fifo, src + index, len >> 2);
276 index += len & ~0x03;
277 }
278 if (len & 0x02) {
279 musb_writew(fifo, 0, *(u16 *)&src[index]);
280 index += 2;
281 }
282 } else {
283 if (len >= 2) {
284 writesw(fifo, src + index, len >> 1);
285 index += len & ~0x01;
286 }
287 }
288 if (len & 0x01)
289 musb_writeb(fifo, 0, src[index]);
290 } else {
291 /* byte aligned */
292 writesb(fifo, src, len);
293 }
294 }
295 EXPORT_SYMBOL_GPL(musb_write_fifo);
297 /*
298 * Unload an endpoint's FIFO
299 */
300 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
301 {
302 struct musb *musb = hw_ep->musb;
303 void __iomem *fifo = hw_ep->fifo;
305 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
306 'R', hw_ep->epnum, fifo, len, dst);
308 /* we can't assume unaligned writes work */
309 if (likely((0x01 & (unsigned long) dst) == 0)) {
310 u16 index = 0;
312 /* best case is 32bit-aligned destination address */
313 if ((0x02 & (unsigned long) dst) == 0) {
314 if (len >= 4) {
315 readsl(fifo, dst, len >> 2);
316 index = len & ~0x03;
317 }
318 if (len & 0x02) {
319 *(u16 *)&dst[index] = musb_readw(fifo, 0);
320 index += 2;
321 }
322 } else {
323 if (len >= 2) {
324 readsw(fifo, dst, len >> 1);
325 index = len & ~0x01;
326 }
327 }
328 if (len & 0x01)
329 dst[index] = musb_readb(fifo, 0);
330 } else {
331 /* byte aligned */
332 readsb(fifo, dst, len);
333 }
334 }
335 EXPORT_SYMBOL_GPL(musb_read_fifo);
337 /*-------------------------------------------------------------------------*/
339 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
340 static const u8 musb_test_packet[53] = {
341 /* implicit SYNC then DATA0 to start */
343 /* JKJKJKJK x9 */
344 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
345 /* JJKKJJKK x8 */
346 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
347 /* JJJJKKKK x8 */
348 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
349 /* JJJJJJJKKKKKKK x8 */
350 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
351 /* JJJJJJJK x8 */
352 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
353 /* JKKKKKKK x10, JK */
354 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
356 /* implicit CRC16 then EOP to end */
357 };
359 void musb_load_testpacket(struct musb *musb)
360 {
361 musb_ep_select(musb, musb->mregs, 0);
362 musb->ops->write_fifo(musb->control_ep,
363 sizeof(musb_test_packet), musb_test_packet);
364 }
366 /*-------------------------------------------------------------------------*/
368 /*
369 * See also USB_OTG_1-3.pdf 6.6.5 Timers
370 * REVISIT: Are the other timers done in the hardware?
371 */
372 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
374 /*
375 * Handles OTG hnp timeouts, such as b_ase0_brst
376 */
377 void musb_otg_timer_func(unsigned long data)
378 {
379 struct musb *musb = (struct musb *)data;
380 unsigned long flags;
382 spin_lock_irqsave(&musb->lock, flags);
383 switch (musb->xceiv->state) {
384 case OTG_STATE_B_WAIT_ACON:
385 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
386 musb_g_disconnect(musb);
387 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
388 musb->is_active = 0;
389 break;
390 case OTG_STATE_A_WAIT_BCON:
391 dev_dbg(musb->controller, "HNP: a_wait_bcon timeout; back to a_host\n");
392 musb_hnp_stop(musb);
393 break;
394 default:
395 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
396 otg_state_string(musb->xceiv->state));
397 }
398 musb->ignore_disconnect = 0;
399 spin_unlock_irqrestore(&musb->lock, flags);
400 }
402 /*
403 * Stops the B-device HNP state. Caller must take care of locking.
404 */
405 void musb_hnp_stop(struct musb *musb)
406 {
407 struct usb_hcd *hcd = musb_to_hcd(musb);
408 void __iomem *mbase = musb->mregs;
409 u8 reg;
411 switch (musb->xceiv->state) {
412 case OTG_STATE_A_PERIPHERAL:
413 case OTG_STATE_A_WAIT_VFALL:
414 case OTG_STATE_A_WAIT_BCON:
415 dev_dbg(musb->controller, "HNP: Switching back to A-host\n");
416 musb_g_disconnect(musb);
417 musb->xceiv->state = OTG_STATE_A_IDLE;
418 MUSB_HST_MODE(musb);
419 musb->is_active = 0;
420 break;
421 case OTG_STATE_B_HOST:
422 dev_dbg(musb->controller, "HNP: Disabling HR\n");
423 hcd->self.is_b_host = 0;
424 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
425 MUSB_DEV_MODE(musb);
426 reg = musb_readb(mbase, MUSB_POWER);
427 reg |= MUSB_POWER_SUSPENDM;
428 musb_writeb(mbase, MUSB_POWER, reg);
429 /* REVISIT: Start SESSION_REQUEST here? */
430 break;
431 default:
432 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
433 otg_state_string(musb->xceiv->state));
434 }
436 /*
437 * When returning to A state after HNP, avoid hub_port_rebounce(),
438 * which cause occasional OPT A "Did not receive reset after connect"
439 * errors.
440 */
441 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
442 }
444 /*
445 * Interrupt Service Routine to record USB "global" interrupts.
446 * Since these do not happen often and signify things of
447 * paramount importance, it seems OK to check them individually;
448 * the order of the tests is specified in the manual
449 *
450 * @param musb instance pointer
451 * @param int_usb register contents
452 * @param devctl
453 * @param power
454 */
456 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
457 u8 devctl, u8 power)
458 {
459 irqreturn_t handled = IRQ_NONE;
461 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
462 int_usb);
464 /* in host mode, the peripheral may issue remote wakeup.
465 * in peripheral mode, the host may resume the link.
466 * spurious RESUME irqs happen too, paired with SUSPEND.
467 */
468 if (int_usb & MUSB_INTR_RESUME) {
469 handled = IRQ_HANDLED;
470 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
472 if (devctl & MUSB_DEVCTL_HM) {
473 void __iomem *mbase = musb->mregs;
475 switch (musb->xceiv->state) {
476 case OTG_STATE_A_SUSPEND:
477 /* remote wakeup? later, GetPortStatus
478 * will stop RESUME signaling
479 */
481 if (power & MUSB_POWER_SUSPENDM) {
482 /* spurious */
483 musb->int_usb &= ~MUSB_INTR_SUSPEND;
484 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
485 break;
486 }
488 power &= ~MUSB_POWER_SUSPENDM;
489 musb_writeb(mbase, MUSB_POWER,
490 power | MUSB_POWER_RESUME);
492 musb->port1_status |=
493 (USB_PORT_STAT_C_SUSPEND << 16)
494 | MUSB_PORT_STAT_RESUME;
495 musb->rh_timer = jiffies
496 + msecs_to_jiffies(20);
498 musb->xceiv->state = OTG_STATE_A_HOST;
499 musb->is_active = 1;
500 usb_hcd_resume_root_hub(musb_to_hcd(musb));
501 break;
502 case OTG_STATE_B_WAIT_ACON:
503 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
504 musb->is_active = 1;
505 MUSB_DEV_MODE(musb);
506 break;
507 default:
508 WARNING("bogus %s RESUME (%s)\n",
509 "host",
510 otg_state_string(musb->xceiv->state));
511 }
512 } else {
513 switch (musb->xceiv->state) {
514 case OTG_STATE_A_SUSPEND:
515 /* possibly DISCONNECT is upcoming */
516 musb->xceiv->state = OTG_STATE_A_HOST;
517 usb_hcd_resume_root_hub(musb_to_hcd(musb));
518 break;
519 case OTG_STATE_B_WAIT_ACON:
520 case OTG_STATE_B_PERIPHERAL:
521 /* disconnect while suspended? we may
522 * not get a disconnect irq...
523 */
524 if ((devctl & MUSB_DEVCTL_VBUS)
525 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
526 ) {
527 musb->int_usb |= MUSB_INTR_DISCONNECT;
528 musb->int_usb &= ~MUSB_INTR_SUSPEND;
529 break;
530 }
531 musb_g_resume(musb);
532 break;
533 case OTG_STATE_B_IDLE:
534 musb->int_usb &= ~MUSB_INTR_SUSPEND;
535 break;
536 default:
537 WARNING("bogus %s RESUME (%s)\n",
538 "peripheral",
539 otg_state_string(musb->xceiv->state));
540 }
541 }
542 }
544 /* see manual for the order of the tests */
545 if (int_usb & MUSB_INTR_SESSREQ) {
546 void __iomem *mbase = musb->mregs;
548 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
549 && (devctl & MUSB_DEVCTL_BDEVICE)) {
550 dev_dbg(musb->controller, "SessReq while on B state\n");
551 return IRQ_HANDLED;
552 }
554 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
555 otg_state_string(musb->xceiv->state));
557 /* IRQ arrives from ID pin sense or (later, if VBUS power
558 * is removed) SRP. responses are time critical:
559 * - turn on VBUS (with silicon-specific mechanism)
560 * - go through A_WAIT_VRISE
561 * - ... to A_WAIT_BCON.
562 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
563 */
564 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
565 musb->ep0_stage = MUSB_EP0_START;
566 musb->xceiv->state = OTG_STATE_A_IDLE;
567 MUSB_HST_MODE(musb);
568 musb_platform_set_vbus(musb, 1);
570 handled = IRQ_HANDLED;
571 }
573 if (int_usb & MUSB_INTR_VBUSERROR) {
574 int ignore = 0;
576 /* During connection as an A-Device, we may see a short
577 * current spikes causing voltage drop, because of cable
578 * and peripheral capacitance combined with vbus draw.
579 * (So: less common with truly self-powered devices, where
580 * vbus doesn't act like a power supply.)
581 *
582 * Such spikes are short; usually less than ~500 usec, max
583 * of ~2 msec. That is, they're not sustained overcurrent
584 * errors, though they're reported using VBUSERROR irqs.
585 *
586 * Workarounds: (a) hardware: use self powered devices.
587 * (b) software: ignore non-repeated VBUS errors.
588 *
589 * REVISIT: do delays from lots of DEBUG_KERNEL checks
590 * make trouble here, keeping VBUS < 4.4V ?
591 */
592 switch (musb->xceiv->state) {
593 case OTG_STATE_A_HOST:
594 /* recovery is dicey once we've gotten past the
595 * initial stages of enumeration, but if VBUS
596 * stayed ok at the other end of the link, and
597 * another reset is due (at least for high speed,
598 * to redo the chirp etc), it might work OK...
599 */
600 case OTG_STATE_A_WAIT_BCON:
601 case OTG_STATE_A_WAIT_VRISE:
602 if (musb->vbuserr_retry) {
603 void __iomem *mbase = musb->mregs;
605 musb->vbuserr_retry--;
606 ignore = 1;
607 devctl |= MUSB_DEVCTL_SESSION;
608 musb_writeb(mbase, MUSB_DEVCTL, devctl);
609 } else {
610 musb->port1_status |=
611 USB_PORT_STAT_OVERCURRENT
612 | (USB_PORT_STAT_C_OVERCURRENT << 16);
613 }
614 break;
615 default:
616 break;
617 }
619 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
620 otg_state_string(musb->xceiv->state),
621 devctl,
622 ({ char *s;
623 switch (devctl & MUSB_DEVCTL_VBUS) {
624 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
625 s = "<SessEnd"; break;
626 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
627 s = "<AValid"; break;
628 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
629 s = "<VBusValid"; break;
630 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
631 default:
632 s = "VALID"; break;
633 }; s; }),
634 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
635 musb->port1_status);
637 /* go through A_WAIT_VFALL then start a new session */
638 if (!ignore)
639 musb_platform_set_vbus(musb, 0);
640 handled = IRQ_HANDLED;
641 }
643 if (int_usb & MUSB_INTR_SUSPEND) {
644 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
645 otg_state_string(musb->xceiv->state), devctl, power);
646 handled = IRQ_HANDLED;
648 switch (musb->xceiv->state) {
649 case OTG_STATE_A_PERIPHERAL:
650 /*
651 * We cannot stop HNP here, devctl BDEVICE might be
652 * still set.
653 */
654 break;
655 case OTG_STATE_B_IDLE:
656 if (!musb->is_active)
657 break;
658 case OTG_STATE_B_PERIPHERAL:
659 musb_g_suspend(musb);
660 musb->is_active = is_otg_enabled(musb)
661 && musb->xceiv->gadget->b_hnp_enable;
662 if (musb->is_active) {
663 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
664 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
665 mod_timer(&musb->otg_timer, jiffies
666 + msecs_to_jiffies(TB_ASE0_BRST));
667 }
668 break;
669 case OTG_STATE_A_WAIT_BCON:
670 if (musb->a_wait_bcon != 0)
671 musb_platform_try_idle(musb, jiffies
672 + msecs_to_jiffies(musb->a_wait_bcon));
673 break;
674 case OTG_STATE_A_HOST:
675 musb->xceiv->state = OTG_STATE_A_SUSPEND;
676 musb->is_active = is_otg_enabled(musb)
677 && musb->xceiv->host->b_hnp_enable;
678 break;
679 case OTG_STATE_B_HOST:
680 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
681 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
682 break;
683 default:
684 /* "should not happen" */
685 musb->is_active = 0;
686 break;
687 }
688 }
690 if (int_usb & MUSB_INTR_CONNECT) {
691 struct usb_hcd *hcd = musb_to_hcd(musb);
693 handled = IRQ_HANDLED;
694 musb->is_active = 1;
695 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
697 musb->ep0_stage = MUSB_EP0_START;
699 /* flush endpoints when transitioning from Device Mode */
700 if (is_peripheral_active(musb)) {
701 /* REVISIT HNP; just force disconnect */
702 }
703 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
704 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
705 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
706 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
707 |USB_PORT_STAT_HIGH_SPEED
708 |USB_PORT_STAT_ENABLE
709 );
710 musb->port1_status |= USB_PORT_STAT_CONNECTION
711 |(USB_PORT_STAT_C_CONNECTION << 16);
713 /* high vs full speed is just a guess until after reset */
714 if (devctl & MUSB_DEVCTL_LSDEV)
715 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
717 if (hcd->status_urb)
718 usb_hcd_poll_rh_status(hcd);
719 else
720 usb_hcd_resume_root_hub(hcd);
722 MUSB_HST_MODE(musb);
724 /* indicate new connection to OTG machine */
725 switch (musb->xceiv->state) {
726 case OTG_STATE_B_PERIPHERAL:
727 if (int_usb & MUSB_INTR_SUSPEND) {
728 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
729 musb->xceiv->state = OTG_STATE_B_HOST;
730 hcd->self.is_b_host = 1;
731 int_usb &= ~MUSB_INTR_SUSPEND;
732 } else
733 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
734 break;
735 case OTG_STATE_B_WAIT_ACON:
736 dev_dbg(musb->controller, "HNP: Waiting to switch to b_host state\n");
737 musb->xceiv->state = OTG_STATE_B_HOST;
738 hcd->self.is_b_host = 1;
739 break;
740 default:
741 if ((devctl & MUSB_DEVCTL_VBUS)
742 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
743 musb->xceiv->state = OTG_STATE_A_HOST;
744 hcd->self.is_b_host = 0;
745 }
746 break;
747 }
749 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
750 otg_state_string(musb->xceiv->state), devctl);
751 }
753 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
754 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
755 otg_state_string(musb->xceiv->state),
756 MUSB_MODE(musb), devctl);
757 handled = IRQ_HANDLED;
759 switch (musb->xceiv->state) {
760 case OTG_STATE_A_HOST:
761 case OTG_STATE_A_SUSPEND:
762 usb_hcd_resume_root_hub(musb_to_hcd(musb));
763 musb_root_disconnect(musb);
764 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
765 musb_platform_try_idle(musb, jiffies
766 + msecs_to_jiffies(musb->a_wait_bcon));
767 break;
768 case OTG_STATE_B_HOST:
769 musb_hnp_stop(musb);
770 break;
771 case OTG_STATE_A_PERIPHERAL:
772 musb_hnp_stop(musb);
773 musb_root_disconnect(musb);
774 /* FALLTHROUGH */
775 case OTG_STATE_B_WAIT_ACON:
776 /* FALLTHROUGH */
777 case OTG_STATE_B_PERIPHERAL:
778 case OTG_STATE_B_IDLE:
779 printk(KERN_INFO "musb %s gadget disconnected.\n",
780 musb->gadget_driver
781 ? musb->gadget_driver->driver.name
782 : "");
783 musb_g_disconnect(musb);
784 break;
785 default:
786 WARNING("unhandled DISCONNECT transition (%s)\n",
787 otg_state_string(musb->xceiv->state));
788 break;
789 }
790 }
792 /* mentor saves a bit: bus reset and babble share the same irq.
793 * only host sees babble; only peripheral sees bus reset.
794 */
795 if (int_usb & MUSB_INTR_RESET) {
796 handled = IRQ_HANDLED;
797 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
798 /*
799 * Looks like non-HS BABBLE can be ignored, but
800 * HS BABBLE is an error condition. For HS the solution
801 * is to avoid babble in the first place and fix what
802 * caused BABBLE. When HS BABBLE happens we can only
803 * stop the session.
804 */
805 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
806 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
807 else {
808 ERR("Stopping host session -- babble\n");
809 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
810 }
811 } else if (is_peripheral_capable()) {
812 dev_dbg(musb->controller, "BUS RESET as %s\n",
813 otg_state_string(musb->xceiv->state));
814 switch (musb->xceiv->state) {
815 case OTG_STATE_A_SUSPEND:
816 /* We need to ignore disconnect on suspend
817 * otherwise tusb 2.0 won't reconnect after a
818 * power cycle, which breaks otg compliance.
819 */
820 musb->ignore_disconnect = 1;
821 musb_g_reset(musb);
822 /* FALLTHROUGH */
823 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
824 dev_dbg(musb->controller, "HNP: Setting timer as %s\n",
825 otg_state_string(musb->xceiv->state));
826 mod_timer(&musb->otg_timer, jiffies
827 + msecs_to_jiffies(100));
828 break;
829 case OTG_STATE_A_PERIPHERAL:
830 musb_hnp_stop(musb);
831 break;
832 case OTG_STATE_B_WAIT_ACON:
833 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
834 otg_state_string(musb->xceiv->state));
835 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
836 musb_g_reset(musb);
837 break;
838 case OTG_STATE_B_IDLE:
839 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
840 /* FALLTHROUGH */
841 case OTG_STATE_B_PERIPHERAL:
842 musb_g_reset(musb);
843 break;
844 default:
845 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
846 otg_state_string(musb->xceiv->state));
847 }
848 }
849 }
851 #if 0
852 /* REVISIT ... this would be for multiplexing periodic endpoints, or
853 * supporting transfer phasing to prevent exceeding ISO bandwidth
854 * limits of a given frame or microframe.
855 *
856 * It's not needed for peripheral side, which dedicates endpoints;
857 * though it _might_ use SOF irqs for other purposes.
858 *
859 * And it's not currently needed for host side, which also dedicates
860 * endpoints, relies on TX/RX interval registers, and isn't claimed
861 * to support ISO transfers yet.
862 */
863 if (int_usb & MUSB_INTR_SOF) {
864 void __iomem *mbase = musb->mregs;
865 struct musb_hw_ep *ep;
866 u8 epnum;
867 u16 frame;
869 dev_dbg(musb->controller, "START_OF_FRAME\n");
870 handled = IRQ_HANDLED;
872 /* start any periodic Tx transfers waiting for current frame */
873 frame = musb_readw(mbase, MUSB_FRAME);
874 ep = musb->endpoints;
875 for (epnum = 1; (epnum < musb->nr_endpoints)
876 && (musb->epmask >= (1 << epnum));
877 epnum++, ep++) {
878 /*
879 * FIXME handle framecounter wraps (12 bits)
880 * eliminate duplicated StartUrb logic
881 */
882 if (ep->dwWaitFrame >= frame) {
883 ep->dwWaitFrame = 0;
884 pr_debug("SOF --> periodic TX%s on %d\n",
885 ep->tx_channel ? " DMA" : "",
886 epnum);
887 if (!ep->tx_channel)
888 musb_h_tx_start(musb, epnum);
889 else
890 cppi_hostdma_start(musb, epnum);
891 }
892 } /* end of for loop */
893 }
894 #endif
896 schedule_work(&musb->irq_work);
898 return handled;
899 }
901 /*-------------------------------------------------------------------------*/
903 /*
904 * Program the HDRC to start (enable interrupts, dma, etc.).
905 */
906 void musb_start(struct musb *musb)
907 {
908 void __iomem *regs = musb->mregs;
909 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
911 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
913 /* Set INT enable registers, enable interrupts */
914 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
915 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
916 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
918 musb_writeb(regs, MUSB_TESTMODE, 0);
920 /* put into basic highspeed mode and start session */
921 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
922 | MUSB_POWER_HSENAB
923 /* ENSUSPEND wedges tusb */
924 /* | MUSB_POWER_ENSUSPEND */
925 );
927 musb->is_active = 0;
928 devctl = musb_readb(regs, MUSB_DEVCTL);
929 devctl &= ~MUSB_DEVCTL_SESSION;
931 if (is_otg_enabled(musb)) {
932 /* session started after:
933 * (a) ID-grounded irq, host mode;
934 * (b) vbus present/connect IRQ, peripheral mode;
935 * (c) peripheral initiates, using SRP
936 */
937 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
938 musb->is_active = 1;
939 else
940 devctl |= MUSB_DEVCTL_SESSION;
942 } else if (is_host_enabled(musb)) {
943 /* assume ID pin is hard-wired to ground */
944 devctl |= MUSB_DEVCTL_SESSION;
946 } else /* peripheral is enabled */ {
947 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
948 musb->is_active = 1;
949 }
950 musb_platform_enable(musb);
951 musb_writeb(regs, MUSB_DEVCTL, devctl);
952 }
953 EXPORT_SYMBOL(musb_start);
955 static void musb_generic_disable(struct musb *musb)
956 {
957 void __iomem *mbase = musb->mregs;
958 u16 temp;
960 /* disable interrupts */
961 musb_writeb(mbase, MUSB_INTRUSBE, 0);
962 musb_writew(mbase, MUSB_INTRTXE, 0);
963 musb_writew(mbase, MUSB_INTRRXE, 0);
965 /* off */
966 musb_writeb(mbase, MUSB_DEVCTL, 0);
968 /* flush pending interrupts */
969 temp = musb_readb(mbase, MUSB_INTRUSB);
970 temp = musb_readw(mbase, MUSB_INTRTX);
971 temp = musb_readw(mbase, MUSB_INTRRX);
973 }
975 /*
976 * Make the HDRC stop (disable interrupts, etc.);
977 * reversible by musb_start
978 * called on gadget driver unregister
979 * with controller locked, irqs blocked
980 * acts as a NOP unless some role activated the hardware
981 */
982 void musb_stop(struct musb *musb)
983 {
984 /* stop IRQs, timers, ... */
985 musb_platform_disable(musb);
986 musb_generic_disable(musb);
987 dev_dbg(musb->controller, "HDRC disabled\n");
989 /* FIXME
990 * - mark host and/or peripheral drivers unusable/inactive
991 * - disable DMA (and enable it in HdrcStart)
992 * - make sure we can musb_start() after musb_stop(); with
993 * OTG mode, gadget driver module rmmod/modprobe cycles that
994 * - ...
995 */
996 musb_platform_try_idle(musb, 0);
997 }
999 static void musb_shutdown(struct platform_device *pdev)
1000 {
1001 struct musb *musb = dev_to_musb(&pdev->dev);
1002 unsigned long flags;
1004 pm_runtime_get_sync(musb->controller);
1005 spin_lock_irqsave(&musb->lock, flags);
1006 musb_platform_disable(musb);
1007 musb_generic_disable(musb);
1008 spin_unlock_irqrestore(&musb->lock, flags);
1010 if (!is_otg_enabled(musb) && is_host_enabled(musb))
1011 usb_remove_hcd(musb_to_hcd(musb));
1012 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1013 musb_platform_exit(musb);
1015 pm_runtime_put(musb->controller);
1016 /* FIXME power down */
1017 }
1020 /*-------------------------------------------------------------------------*/
1022 /*
1023 * tables defining fifo_mode values. define more if you like.
1024 * for host side, make sure both halves of ep1 are set up.
1025 */
1027 /* mode 0 - fits in 2KB */
1028 static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = {
1029 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1030 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1031 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1032 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1033 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1034 };
1036 /* mode 1 - fits in 4KB */
1037 static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = {
1038 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1039 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1040 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1041 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1042 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1043 };
1045 /* mode 2 - fits in 4KB */
1046 static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = {
1047 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1048 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1049 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1050 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1051 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1052 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1053 };
1055 /* mode 3 - fits in 4KB */
1056 static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = {
1057 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1058 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1059 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1060 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1061 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1062 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1063 };
1065 /* mode 4 - fits in 16KB */
1066 static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = {
1067 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512,},
1068 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512,},
1069 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512,},
1070 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512,},
1071 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512,},
1072 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512,},
1073 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1074 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1075 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1076 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1077 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1078 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1079 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1080 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1081 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1082 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1083 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1084 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1085 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1086 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1087 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1088 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1089 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1090 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1091 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1092 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1093 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1094 };
1097 /* mode 5 - fits in 8KB */
1098 static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = {
1099 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1100 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1101 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1102 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1103 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1104 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1105 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1106 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1107 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1108 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1109 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1110 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1111 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1112 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1113 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1114 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1115 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1116 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1117 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1118 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1119 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1120 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1121 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1122 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1123 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1124 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1125 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1126 };
1128 /* mode 6 - fits in 32KB */
1129 static struct musb_fifo_cfg __devinitdata mode_6_cfg[] = {
1130 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE,},
1131 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE,},
1132 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE,},
1133 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE,},
1134 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE,},
1135 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE,},
1136 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 64, },
1137 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 64, },
1138 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 64, },
1139 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 64, },
1140 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 64, },
1141 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 64, },
1142 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 64, },
1143 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 64, },
1144 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 64, },
1145 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 64, },
1146 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 64, },
1147 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 64, },
1148 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1149 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1150 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1151 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1152 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1153 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1154 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1155 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1156 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1157 };
1159 /*
1160 * configure a fifo; for non-shared endpoints, this may be called
1161 * once for a tx fifo and once for an rx fifo.
1162 *
1163 * returns negative errno or offset for next fifo.
1164 */
1165 static int __devinit
1166 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1167 const struct musb_fifo_cfg *cfg, u16 offset)
1168 {
1169 void __iomem *mbase = musb->mregs;
1170 int size = 0;
1171 u16 maxpacket = cfg->maxpacket;
1172 u16 c_off = offset >> 3;
1173 u8 c_size;
1175 /* expect hw_ep has already been zero-initialized */
1177 size = ffs(max(maxpacket, (u16) 8)) - 1;
1178 maxpacket = 1 << size;
1180 c_size = size - 3;
1181 if (cfg->mode == BUF_DOUBLE) {
1182 if ((offset + (maxpacket << 1)) >
1183 (1 << (musb->config->ram_bits + 2)))
1184 return -EMSGSIZE;
1185 c_size |= MUSB_FIFOSZ_DPB;
1186 } else {
1187 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1188 return -EMSGSIZE;
1189 }
1191 /* configure the FIFO */
1192 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1194 /* EP0 reserved endpoint for control, bidirectional;
1195 * EP1 reserved for bulk, two unidirection halves.
1196 */
1197 if (hw_ep->epnum == 1)
1198 musb->bulk_ep = hw_ep;
1199 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1200 switch (cfg->style) {
1201 case FIFO_TX:
1202 musb_write_txfifosz(mbase, c_size);
1203 musb_write_txfifoadd(mbase, c_off);
1204 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1205 hw_ep->max_packet_sz_tx = maxpacket;
1206 break;
1207 case FIFO_RX:
1208 musb_write_rxfifosz(mbase, c_size);
1209 musb_write_rxfifoadd(mbase, c_off);
1210 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1211 hw_ep->max_packet_sz_rx = maxpacket;
1212 break;
1213 case FIFO_RXTX:
1214 musb_write_txfifosz(mbase, c_size);
1215 musb_write_txfifoadd(mbase, c_off);
1216 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1217 hw_ep->max_packet_sz_rx = maxpacket;
1219 musb_write_rxfifosz(mbase, c_size);
1220 musb_write_rxfifoadd(mbase, c_off);
1221 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1222 hw_ep->max_packet_sz_tx = maxpacket;
1224 hw_ep->is_shared_fifo = true;
1225 break;
1226 }
1228 /* NOTE rx and tx endpoint irqs aren't managed separately,
1229 * which happens to be ok
1230 */
1231 musb->epmask |= (1 << hw_ep->epnum);
1233 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1234 }
1236 static struct musb_fifo_cfg __devinitdata ep0_cfg = {
1237 .style = FIFO_RXTX, .maxpacket = 64,
1238 };
1240 static int __devinit ep_config_from_table(struct musb *musb)
1241 {
1242 const struct musb_fifo_cfg *cfg;
1243 unsigned i, n;
1244 int offset;
1245 struct musb_hw_ep *hw_ep = musb->endpoints;
1247 if (musb->config->fifo_mode)
1248 musb->fifo_mode = musb->config->fifo_mode;
1249 else if (musb->config->fifo_cfg) {
1250 cfg = musb->config->fifo_cfg;
1251 n = musb->config->fifo_cfg_size;
1252 goto done;
1253 }
1255 switch (musb->fifo_mode) {
1256 default:
1257 musb->fifo_mode = 0;
1258 /* FALLTHROUGH */
1259 case 0:
1260 cfg = mode_0_cfg;
1261 n = ARRAY_SIZE(mode_0_cfg);
1262 break;
1263 case 1:
1264 cfg = mode_1_cfg;
1265 n = ARRAY_SIZE(mode_1_cfg);
1266 break;
1267 case 2:
1268 cfg = mode_2_cfg;
1269 n = ARRAY_SIZE(mode_2_cfg);
1270 break;
1271 case 3:
1272 cfg = mode_3_cfg;
1273 n = ARRAY_SIZE(mode_3_cfg);
1274 break;
1275 case 4:
1276 cfg = mode_4_cfg;
1277 n = ARRAY_SIZE(mode_4_cfg);
1278 break;
1279 case 5:
1280 cfg = mode_5_cfg;
1281 n = ARRAY_SIZE(mode_5_cfg);
1282 break;
1283 case 6:
1284 cfg = mode_6_cfg;
1285 n = ARRAY_SIZE(mode_6_cfg);
1286 break;
1287 }
1289 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1290 musb_driver_name, musb->fifo_mode);
1293 done:
1294 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1295 /* assert(offset > 0) */
1297 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1298 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1299 */
1301 for (i = 0; i < n; i++) {
1302 u8 epn = cfg->hw_ep_num;
1304 if (epn >= musb->config->num_eps) {
1305 pr_debug("%s: invalid ep %d\n",
1306 musb_driver_name, epn);
1307 return -EINVAL;
1308 }
1309 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1310 if (offset < 0) {
1311 pr_debug("%s: mem overrun, ep %d\n",
1312 musb_driver_name, epn);
1313 return -EINVAL;
1314 }
1315 epn++;
1316 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1317 }
1319 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1320 musb_driver_name,
1321 n + 1, musb->config->num_eps * 2 - 1,
1322 offset, (1 << (musb->config->ram_bits + 2)));
1324 if (!musb->bulk_ep) {
1325 pr_debug("%s: missing bulk\n", musb_driver_name);
1326 return -EINVAL;
1327 }
1329 return 0;
1330 }
1332 /*
1333 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1334 * @param musb the controller
1335 */
1336 static int __devinit ep_config_from_hw(struct musb *musb)
1337 {
1338 u8 epnum = 0;
1339 struct musb_hw_ep *hw_ep;
1340 void *mbase = musb->mregs;
1341 int ret = 0;
1343 dev_dbg(musb->controller, "<== static silicon ep config\n");
1345 /* FIXME pick up ep0 maxpacket size */
1347 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1348 musb_ep_select(musb, mbase, epnum);
1349 hw_ep = musb->endpoints + epnum;
1351 ret = musb_read_fifosize(musb, hw_ep, epnum);
1352 if (ret < 0)
1353 break;
1355 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1357 /* pick an RX/TX endpoint for bulk */
1358 if (hw_ep->max_packet_sz_tx < 512
1359 || hw_ep->max_packet_sz_rx < 512)
1360 continue;
1362 /* REVISIT: this algorithm is lazy, we should at least
1363 * try to pick a double buffered endpoint.
1364 */
1365 if (musb->bulk_ep)
1366 continue;
1367 musb->bulk_ep = hw_ep;
1368 }
1370 if (!musb->bulk_ep) {
1371 pr_debug("%s: missing bulk\n", musb_driver_name);
1372 return -EINVAL;
1373 }
1375 return 0;
1376 }
1378 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1380 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1381 * configure endpoints, or take their config from silicon
1382 */
1383 static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
1384 {
1385 u8 reg;
1386 char *type;
1387 char aInfo[90], aRevision[32], aDate[12];
1388 void __iomem *mbase = musb->mregs;
1389 int status = 0;
1390 int i;
1392 /* log core options (read using indexed model) */
1393 reg = musb_read_configdata(mbase);
1395 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1396 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1397 strcat(aInfo, ", dyn FIFOs");
1398 musb->dyn_fifo = true;
1399 }
1400 if (reg & MUSB_CONFIGDATA_MPRXE) {
1401 strcat(aInfo, ", bulk combine");
1402 musb->bulk_combine = true;
1403 }
1404 if (reg & MUSB_CONFIGDATA_MPTXE) {
1405 strcat(aInfo, ", bulk split");
1406 musb->bulk_split = true;
1407 }
1408 if (reg & MUSB_CONFIGDATA_HBRXE) {
1409 strcat(aInfo, ", HB-ISO Rx");
1410 musb->hb_iso_rx = true;
1411 }
1412 if (reg & MUSB_CONFIGDATA_HBTXE) {
1413 strcat(aInfo, ", HB-ISO Tx");
1414 musb->hb_iso_tx = true;
1415 }
1416 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1417 strcat(aInfo, ", SoftConn");
1419 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1420 musb_driver_name, reg, aInfo);
1422 aDate[0] = 0;
1423 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1424 musb->is_multipoint = 1;
1425 type = "M";
1426 } else {
1427 musb->is_multipoint = 0;
1428 type = "";
1429 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1430 printk(KERN_ERR
1431 "%s: kernel must blacklist external hubs\n",
1432 musb_driver_name);
1433 #endif
1434 }
1436 /* log release info */
1437 musb->hwvers = musb_read_hwvers(mbase);
1438 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1439 MUSB_HWVERS_MINOR(musb->hwvers),
1440 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1441 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1442 musb_driver_name, type, aRevision, aDate);
1444 /* configure ep0 */
1445 musb_configure_ep0(musb);
1447 /* discover endpoint configuration */
1448 musb->nr_endpoints = 1;
1449 musb->epmask = 1;
1451 if (musb->dyn_fifo)
1452 status = ep_config_from_table(musb);
1453 else
1454 status = ep_config_from_hw(musb);
1456 if (status < 0)
1457 return status;
1459 /* finish init, and print endpoint config */
1460 for (i = 0; i < musb->nr_endpoints; i++) {
1461 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1463 if (musb->ops->flags & MUSB_GLUE_TUSB_STYLE) {
1464 hw_ep->fifo = MUSB_TUSB_FIFO_OFFSET(i) + mbase;
1465 hw_ep->fifo_async = musb->async +
1466 0x400 + MUSB_TUSB_FIFO_OFFSET(i);
1467 hw_ep->fifo_sync = musb->sync +
1468 0x400 + MUSB_TUSB_FIFO_OFFSET(i);
1469 hw_ep->fifo_sync_va = musb->sync_va + 0x400 +
1470 MUSB_TUSB_FIFO_OFFSET(i);
1472 if (i == 0)
1473 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1474 else
1475 hw_ep->conf = mbase + 0x400 +
1476 (((i - 1) & 0xf) << 2);
1477 } else {
1478 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1479 }
1481 hw_ep->regs = MUSB_EP_OFFSET(musb, i, 0) + mbase;
1482 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1483 hw_ep->rx_reinit = 1;
1484 hw_ep->tx_reinit = 1;
1486 if (hw_ep->max_packet_sz_tx) {
1487 dev_dbg(musb->controller,
1488 "%s: hw_ep %d%s, %smax %d\n",
1489 musb_driver_name, i,
1490 hw_ep->is_shared_fifo ? "shared" : "tx",
1491 hw_ep->tx_double_buffered
1492 ? "doublebuffer, " : "",
1493 hw_ep->max_packet_sz_tx);
1494 }
1495 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1496 dev_dbg(musb->controller,
1497 "%s: hw_ep %d%s, %smax %d\n",
1498 musb_driver_name, i,
1499 "rx",
1500 hw_ep->rx_double_buffered
1501 ? "doublebuffer, " : "",
1502 hw_ep->max_packet_sz_rx);
1503 }
1504 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1505 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1506 }
1508 return 0;
1509 }
1511 /*-------------------------------------------------------------------------*/
1513 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1514 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
1516 static irqreturn_t generic_interrupt(int irq, void *__hci)
1517 {
1518 unsigned long flags;
1519 irqreturn_t retval = IRQ_NONE;
1520 struct musb *musb = __hci;
1522 spin_lock_irqsave(&musb->lock, flags);
1524 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1525 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1526 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1528 if (musb->int_usb || musb->int_tx || musb->int_rx)
1529 retval = musb_interrupt(musb);
1531 spin_unlock_irqrestore(&musb->lock, flags);
1533 return retval;
1534 }
1536 #else
1537 #define generic_interrupt NULL
1538 #endif
1540 /*
1541 * handle all the irqs defined by the HDRC core. for now we expect: other
1542 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1543 * will be assigned, and the irq will already have been acked.
1544 *
1545 * called in irq context with spinlock held, irqs blocked
1546 */
1547 irqreturn_t musb_interrupt(struct musb *musb)
1548 {
1549 irqreturn_t retval = IRQ_NONE;
1550 u8 devctl, power;
1551 int ep_num;
1552 u32 reg;
1554 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1555 power = musb_readb(musb->mregs, MUSB_POWER);
1557 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1558 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1559 musb->int_usb, musb->int_tx, musb->int_rx);
1561 /* the core can interrupt us for multiple reasons; docs have
1562 * a generic interrupt flowchart to follow
1563 */
1564 if (musb->int_usb)
1565 retval |= musb_stage0_irq(musb, musb->int_usb,
1566 devctl, power);
1568 /* "stage 1" is handling endpoint irqs */
1570 /* handle endpoint 0 first */
1571 if (musb->int_tx & 1) {
1572 if (devctl & MUSB_DEVCTL_HM)
1573 retval |= musb_h_ep0_irq(musb);
1574 else
1575 retval |= musb_g_ep0_irq(musb);
1576 }
1578 /* RX on endpoints 1-15 */
1579 reg = musb->int_rx >> 1;
1580 ep_num = 1;
1581 while (reg) {
1582 if (reg & 1) {
1583 /* musb_ep_select(musb, musb->mregs, ep_num); */
1584 /* REVISIT just retval = ep->rx_irq(...) */
1585 retval = IRQ_HANDLED;
1586 if (devctl & MUSB_DEVCTL_HM) {
1587 if (is_host_capable())
1588 musb_host_rx(musb, ep_num);
1589 } else {
1590 if (is_peripheral_capable())
1591 musb_g_rx(musb, ep_num);
1592 }
1593 }
1595 reg >>= 1;
1596 ep_num++;
1597 }
1599 /* TX on endpoints 1-15 */
1600 reg = musb->int_tx >> 1;
1601 ep_num = 1;
1602 while (reg) {
1603 if (reg & 1) {
1604 /* musb_ep_select(musb, musb->mregs, ep_num); */
1605 /* REVISIT just retval |= ep->tx_irq(...) */
1606 retval = IRQ_HANDLED;
1607 if (devctl & MUSB_DEVCTL_HM) {
1608 if (is_host_capable())
1609 musb_host_tx(musb, ep_num);
1610 } else {
1611 if (is_peripheral_capable())
1612 musb_g_tx(musb, ep_num);
1613 }
1614 }
1615 reg >>= 1;
1616 ep_num++;
1617 }
1619 return retval;
1620 }
1621 EXPORT_SYMBOL_GPL(musb_interrupt);
1623 #ifndef CONFIG_MUSB_PIO_ONLY
1624 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1625 {
1626 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1628 /* called with controller lock already held */
1630 if (!epnum) {
1631 if (!tusb_dma_omap(musb) && !is_cppi_enabled(musb)
1632 && !is_cppi41_enabled(musb)) {
1633 /* endpoint 0 */
1634 if (devctl & MUSB_DEVCTL_HM)
1635 musb_h_ep0_irq(musb);
1636 else
1637 musb_g_ep0_irq(musb);
1638 }
1639 } else {
1640 /* endpoints 1..15 */
1641 if (transmit) {
1642 if (devctl & MUSB_DEVCTL_HM) {
1643 if (is_host_capable())
1644 musb_host_tx(musb, epnum);
1645 } else {
1646 if (is_peripheral_capable())
1647 musb_g_tx(musb, epnum);
1648 }
1649 } else {
1650 /* receive */
1651 if (devctl & MUSB_DEVCTL_HM) {
1652 if (is_host_capable())
1653 musb_host_rx(musb, epnum);
1654 } else {
1655 if (is_peripheral_capable())
1656 musb_g_rx(musb, epnum);
1657 }
1658 }
1659 }
1660 }
1661 EXPORT_SYMBOL_GPL(musb_dma_completion);
1662 #endif
1664 /*-------------------------------------------------------------------------*/
1666 #ifdef CONFIG_SYSFS
1668 static ssize_t
1669 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1670 {
1671 struct musb *musb = dev_to_musb(dev);
1672 unsigned long flags;
1673 int ret = -EINVAL;
1675 spin_lock_irqsave(&musb->lock, flags);
1676 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1677 spin_unlock_irqrestore(&musb->lock, flags);
1679 return ret;
1680 }
1682 static ssize_t
1683 musb_mode_store(struct device *dev, struct device_attribute *attr,
1684 const char *buf, size_t n)
1685 {
1686 struct musb *musb = dev_to_musb(dev);
1687 unsigned long flags;
1688 int status;
1690 spin_lock_irqsave(&musb->lock, flags);
1691 if (sysfs_streq(buf, "host"))
1692 status = musb_platform_set_mode(musb, MUSB_HOST);
1693 else if (sysfs_streq(buf, "peripheral"))
1694 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1695 else if (sysfs_streq(buf, "otg"))
1696 status = musb_platform_set_mode(musb, MUSB_OTG);
1697 else
1698 status = -EINVAL;
1699 spin_unlock_irqrestore(&musb->lock, flags);
1701 return (status == 0) ? n : status;
1702 }
1703 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1705 static ssize_t
1706 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1707 const char *buf, size_t n)
1708 {
1709 struct musb *musb = dev_to_musb(dev);
1710 unsigned long flags;
1711 unsigned long val;
1713 if (sscanf(buf, "%lu", &val) < 1) {
1714 dev_err(dev, "Invalid VBUS timeout ms value\n");
1715 return -EINVAL;
1716 }
1718 spin_lock_irqsave(&musb->lock, flags);
1719 musb->a_wait_bcon = val;
1720 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1721 musb->is_active = 0;
1722 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1723 spin_unlock_irqrestore(&musb->lock, flags);
1725 return n;
1726 }
1728 static ssize_t
1729 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1730 {
1731 struct musb *musb = dev_to_musb(dev);
1732 unsigned long flags;
1733 unsigned long val;
1734 int vbus;
1736 spin_lock_irqsave(&musb->lock, flags);
1737 val = musb->a_wait_bcon;
1738 vbus = musb_platform_get_vbus_status(musb);
1739 spin_unlock_irqrestore(&musb->lock, flags);
1741 return sprintf(buf, "Vbus %s, timeout %lu\n",
1742 vbus ? "on" : "off", val);
1743 }
1744 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1746 /* Gadget drivers can't know that a host is connected so they might want
1747 * to start SRP, but users can. This allows userspace to trigger SRP.
1748 */
1749 static ssize_t
1750 musb_srp_store(struct device *dev, struct device_attribute *attr,
1751 const char *buf, size_t n)
1752 {
1753 struct musb *musb = dev_to_musb(dev);
1754 unsigned short srp;
1756 if (sscanf(buf, "%hu", &srp) != 1
1757 || (srp != 1)) {
1758 dev_err(dev, "SRP: Value must be 1\n");
1759 return -EINVAL;
1760 }
1762 if (srp == 1)
1763 musb_g_wakeup(musb);
1765 return n;
1766 }
1767 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1769 static struct attribute *musb_attributes[] = {
1770 &dev_attr_mode.attr,
1771 &dev_attr_vbus.attr,
1772 &dev_attr_srp.attr,
1773 NULL
1774 };
1776 static const struct attribute_group musb_attr_group = {
1777 .attrs = musb_attributes,
1778 };
1780 #endif /* sysfs */
1782 /* Only used to provide driver mode change events */
1783 static void musb_irq_work(struct work_struct *data)
1784 {
1785 struct musb *musb = container_of(data, struct musb, irq_work);
1787 if (musb->xceiv->state != musb->old_state) {
1788 musb->old_state = musb->xceiv->state;
1789 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1790 }
1791 }
1793 /* --------------------------------------------------------------------------
1794 * Init support
1795 */
1797 static struct musb *__devinit
1798 allocate_instance(struct device *dev,
1799 struct musb_hdrc_config *config, void __iomem *mbase)
1800 {
1801 struct musb *musb;
1802 struct musb_hw_ep *ep;
1803 int epnum;
1804 struct usb_hcd *hcd;
1806 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1807 if (!hcd)
1808 return NULL;
1809 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1811 musb = hcd_to_musb(hcd);
1812 INIT_LIST_HEAD(&musb->control);
1813 INIT_LIST_HEAD(&musb->in_bulk);
1814 INIT_LIST_HEAD(&musb->out_bulk);
1815 INIT_LIST_HEAD(&musb->gb_list);
1817 hcd->uses_new_polling = 1;
1818 hcd->has_tt = 1;
1820 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1821 dev_set_drvdata(dev, musb);
1822 musb->mregs = mbase;
1823 musb->ctrl_base = mbase;
1824 musb->nIrq = -ENODEV;
1825 musb->config = config;
1826 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1827 for (epnum = 0, ep = musb->endpoints;
1828 epnum < musb->config->num_eps;
1829 epnum++, ep++) {
1830 ep->musb = musb;
1831 ep->epnum = epnum;
1832 }
1834 musb->controller = dev;
1836 return musb;
1837 }
1839 static void musb_free(struct musb *musb)
1840 {
1841 /* this has multiple entry modes. it handles fault cleanup after
1842 * probe(), where things may be partially set up, as well as rmmod
1843 * cleanup after everything's been de-activated.
1844 */
1846 #ifdef CONFIG_SYSFS
1847 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1848 #endif
1850 musb_gadget_cleanup(musb);
1852 if (musb->nIrq >= 0) {
1853 if (musb->irq_wake)
1854 disable_irq_wake(musb->nIrq);
1855 free_irq(musb->nIrq, musb);
1856 }
1857 if (is_dma_capable() && musb->dma_controller) {
1858 struct dma_controller *c = musb->dma_controller;
1860 (void) c->stop(c);
1861 musb->ops->dma_controller_destroy(c);
1862 }
1864 if (musb->gb_queue)
1865 destroy_workqueue(musb->gb_queue);
1867 del_timer_sync(&musb->otg_timer);
1869 kfree(musb);
1870 }
1872 /*
1873 * Perform generic per-controller initialization.
1874 *
1875 * @pDevice: the controller (already clocked, etc)
1876 * @nIrq: irq
1877 * @mregs: virtual address of controller registers,
1878 * not yet corrected for platform-specific offsets
1879 */
1880 static int __devinit
1881 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1882 {
1883 int status;
1884 struct musb *musb;
1885 struct musb_hdrc_platform_data *plat = dev->platform_data;
1886 struct platform_device *pdev = to_platform_device(dev);
1888 /* The driver might handle more features than the board; OK.
1889 * Fail when the board needs a feature that's not enabled.
1890 */
1891 if (!plat) {
1892 dev_dbg(dev, "no platform_data?\n");
1893 status = -ENODEV;
1894 goto fail0;
1895 }
1897 /* allocate */
1898 musb = allocate_instance(dev, plat->config, ctrl);
1899 if (!musb) {
1900 status = -ENOMEM;
1901 goto fail0;
1902 }
1904 pm_runtime_use_autosuspend(musb->controller);
1905 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1906 pm_runtime_enable(musb->controller);
1908 spin_lock_init(&musb->lock);
1909 spin_lock_init(&musb->gb_lock);
1910 musb->board_mode = plat->mode;
1911 musb->board_set_power = plat->set_power;
1912 musb->min_power = plat->min_power;
1913 musb->ops = plat->platform_ops;
1914 musb->id = pdev->id;
1915 musb->first = 1;
1917 musb->fifo_mode = musb->ops->fifo_mode;
1919 #ifndef CONFIG_MUSB_PIO_ONLY
1920 musb->orig_dma_mask = dev->dma_mask;
1921 #endif
1922 if (musb->ops->flags & MUSB_GLUE_TUSB_STYLE) {
1923 musb_readb = __tusb_musb_readb;
1924 musb_writeb = __tusb_musb_writeb;
1925 } else {
1926 musb_readb = __musb_readb;
1927 musb_writeb = __musb_writeb;
1928 }
1930 dev_info(dev, "dma type: %s\n", get_dma_name(musb));
1932 /* The musb_platform_init() call:
1933 * - adjusts musb->mregs and musb->isr if needed,
1934 * - may initialize an integrated tranceiver
1935 * - initializes musb->xceiv, usually by otg_get_transceiver()
1936 * - stops powering VBUS
1937 *
1938 * There are various transceiver configurations. Blackfin,
1939 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1940 * external/discrete ones in various flavors (twl4030 family,
1941 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1942 */
1943 musb->isr = generic_interrupt;
1944 status = musb_platform_init(musb);
1945 if (status < 0)
1946 goto fail1;
1948 if (!musb->isr) {
1949 status = -ENODEV;
1950 goto fail3;
1951 }
1953 if (!musb->xceiv->io_ops) {
1954 musb->xceiv->io_priv = musb->mregs;
1955 musb->xceiv->io_ops = &musb_ulpi_access;
1956 }
1958 #ifndef CONFIG_MUSB_PIO_ONLY
1959 if (dev->dma_mask) {
1960 struct dma_controller *c;
1962 if (!musb->ops->dma_controller_create) {
1963 dev_err(dev, "no dma_controller_create for non-PIO mode!\n");
1964 status = -ENODEV;
1965 goto fail3;
1966 }
1967 c = musb->ops->dma_controller_create(musb, musb->mregs);
1968 musb->dma_controller = c;
1969 if (c)
1970 (void) c->start(c);
1971 }
1972 #endif
1973 /* ideally this would be abstracted in platform setup */
1974 if (!is_dma_capable() || !musb->dma_controller)
1975 dev->dma_mask = NULL;
1977 /* be sure interrupts are disabled before connecting ISR */
1978 musb_platform_disable(musb);
1979 musb_generic_disable(musb);
1981 /* setup musb parts of the core (especially endpoints) */
1982 status = musb_core_init(plat->config->multipoint
1983 ? MUSB_CONTROLLER_MHDRC
1984 : MUSB_CONTROLLER_HDRC, musb);
1985 if (status < 0)
1986 goto fail3;
1988 /* Init IRQ workqueue before request_irq */
1989 INIT_WORK(&musb->irq_work, musb_irq_work);
1991 /* attach to the IRQ */
1992 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1993 dev_err(dev, "request_irq %d failed!\n", nIrq);
1994 status = -ENODEV;
1995 goto fail3;
1996 }
1997 musb->nIrq = nIrq;
1998 /* FIXME this handles wakeup irqs wrong */
1999 if (enable_irq_wake(nIrq) == 0) {
2000 musb->irq_wake = 1;
2001 device_init_wakeup(dev, 1);
2002 } else {
2003 musb->irq_wake = 0;
2004 }
2006 /* host side needs more setup */
2007 if (is_host_enabled(musb)) {
2008 struct usb_hcd *hcd = musb_to_hcd(musb);
2010 otg_set_host(musb->xceiv, &hcd->self);
2012 if (is_otg_enabled(musb))
2013 hcd->self.otg_port = 1;
2014 musb->xceiv->host = &hcd->self;
2015 hcd->power_budget = 2 * (plat->power ? : 250);
2017 /* program PHY to use external vBus if required */
2018 if (plat->extvbus) {
2019 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2020 busctl |= MUSB_ULPI_USE_EXTVBUS;
2021 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2022 }
2023 }
2025 /* For the host-only role, we can activate right away.
2026 * (We expect the ID pin to be forcibly grounded!!)
2027 * Otherwise, wait till the gadget driver hooks up.
2028 */
2029 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2030 struct usb_hcd *hcd = musb_to_hcd(musb);
2032 MUSB_HST_MODE(musb);
2033 musb->xceiv->default_a = 1;
2034 musb->xceiv->state = OTG_STATE_A_IDLE;
2036 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2038 hcd->self.uses_pio_for_control = 1;
2039 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2040 "HOST", status,
2041 musb_readb(musb->mregs, MUSB_DEVCTL),
2042 (musb_readb(musb->mregs, MUSB_DEVCTL)
2043 & MUSB_DEVCTL_BDEVICE
2044 ? 'B' : 'A'));
2046 } else /* peripheral is enabled */ {
2047 MUSB_DEV_MODE(musb);
2048 musb->xceiv->default_a = 0;
2049 musb->xceiv->state = OTG_STATE_B_IDLE;
2051 status = musb_gadget_setup(musb);
2053 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2054 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2055 status,
2056 musb_readb(musb->mregs, MUSB_DEVCTL));
2058 }
2059 if (status < 0)
2060 goto fail3;
2062 status = musb_init_debugfs(musb);
2063 if (status < 0)
2064 goto fail4;
2066 #ifdef CONFIG_SYSFS
2067 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2068 if (status)
2069 goto fail5;
2070 #endif
2072 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2073 ({char *s;
2074 switch (musb->board_mode) {
2075 case MUSB_HOST: s = "Host"; break;
2076 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2077 default: s = "OTG"; break;
2078 }; s; }),
2079 ctrl,
2080 (is_dma_capable() && musb->dma_controller)
2081 ? "DMA" : "PIO",
2082 musb->nIrq);
2084 if (status == 0) {
2085 u8 drvbuf[19];
2086 sprintf(drvbuf, "driver/musb_hdrc.%d", musb->id);
2087 musb_debug_create(drvbuf, musb);
2088 }
2090 musb->gb_queue = create_singlethread_workqueue(dev_name(dev));
2091 if (musb->gb_queue == NULL)
2092 goto fail6;
2093 /* Init giveback workqueue */
2094 INIT_WORK(&musb->gb_work, musb_gb_work);
2096 /* setup otg_timer */
2097 setup_timer(&musb->otg_timer, musb_otg_timer_func,
2098 (unsigned long) musb);
2099 return 0;
2101 fail6:
2102 destroy_workqueue(musb->gb_queue);
2104 fail5:
2105 musb_exit_debugfs(musb);
2107 fail4:
2108 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2109 usb_remove_hcd(musb_to_hcd(musb));
2110 else
2111 musb_gadget_cleanup(musb);
2113 fail3:
2114 if (musb->irq_wake)
2115 device_init_wakeup(dev, 0);
2116 musb_platform_exit(musb);
2118 fail1:
2119 dev_err(musb->controller,
2120 "musb_init_controller failed with status %d\n", status);
2122 musb_free(musb);
2124 fail0:
2126 return status;
2128 }
2130 /*-------------------------------------------------------------------------*/
2132 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2133 * bridge to a platform device; this driver then suffices.
2134 */
2135 static int __devinit musb_probe(struct platform_device *pdev)
2136 {
2137 struct device *dev = &pdev->dev;
2138 int irq = platform_get_irq_byname(pdev, "mc");
2139 int status;
2140 struct resource *iomem;
2141 void __iomem *base;
2142 char res_name[20];
2144 if (pdev->id == -1)
2145 strcpy(res_name, "mc");
2146 else
2147 sprintf(res_name, "musb%d-irq", pdev->id);
2148 irq = platform_get_irq_byname(pdev, res_name);
2150 if (pdev->id == -1)
2151 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2152 else {
2153 sprintf(res_name, "musb%d", pdev->id);
2154 iomem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2155 res_name);
2156 }
2158 if (!iomem || irq <= 0)
2159 return -ENODEV;
2161 base = ioremap(iomem->start, resource_size(iomem));
2162 if (!base) {
2163 dev_err(dev, "ioremap failed\n");
2164 return -ENOMEM;
2165 }
2167 status = musb_init_controller(dev, irq, base);
2168 if (status < 0)
2169 iounmap(base);
2171 return status;
2172 }
2174 static int __exit musb_remove(struct platform_device *pdev)
2175 {
2176 struct musb *musb = dev_to_musb(&pdev->dev);
2177 void __iomem *ctrl_base = musb->ctrl_base;
2178 u8 drvbuf[19];
2180 /* this gets called on rmmod.
2181 * - Host mode: host may still be active
2182 * - Peripheral mode: peripheral is deactivated (or never-activated)
2183 * - OTG mode: both roles are deactivated (or never-activated)
2184 */
2185 pm_runtime_get_sync(musb->controller);
2186 musb_exit_debugfs(musb);
2187 musb_shutdown(pdev);
2188 sprintf(drvbuf, "driver/musb_hdrc.%d", musb->id);
2189 musb_debug_delete(drvbuf, musb);
2191 pm_runtime_put(musb->controller);
2192 musb_free(musb);
2193 iounmap(ctrl_base);
2194 device_init_wakeup(&pdev->dev, 0);
2195 #ifndef CONFIG_MUSB_PIO_ONLY
2196 pdev->dev.dma_mask = musb->orig_dma_mask;
2197 #endif
2198 return 0;
2199 }
2201 #ifdef CONFIG_PM
2203 static void musb_save_context(struct musb *musb)
2204 {
2205 int i;
2206 void __iomem *musb_base = musb->mregs;
2207 void __iomem *epio;
2209 if (is_host_enabled(musb)) {
2210 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2211 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2212 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2213 }
2214 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2215 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2216 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2217 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2218 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2219 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2221 for (i = 0; i < musb->config->num_eps; ++i) {
2222 struct musb_hw_ep *hw_ep;
2224 hw_ep = &musb->endpoints[i];
2225 if (!hw_ep)
2226 continue;
2228 epio = hw_ep->regs;
2229 if (!epio)
2230 continue;
2232 musb_writeb(musb_base, MUSB_INDEX, i);
2233 musb->context.index_regs[i].txmaxp =
2234 musb_readw(epio, MUSB_TXMAXP);
2235 musb->context.index_regs[i].txcsr =
2236 musb_readw(epio, MUSB_TXCSR);
2237 musb->context.index_regs[i].rxmaxp =
2238 musb_readw(epio, MUSB_RXMAXP);
2239 musb->context.index_regs[i].rxcsr =
2240 musb_readw(epio, MUSB_RXCSR);
2242 if (musb->dyn_fifo) {
2243 musb->context.index_regs[i].txfifoadd =
2244 musb_read_txfifoadd(musb_base);
2245 musb->context.index_regs[i].rxfifoadd =
2246 musb_read_rxfifoadd(musb_base);
2247 musb->context.index_regs[i].txfifosz =
2248 musb_read_txfifosz(musb_base);
2249 musb->context.index_regs[i].rxfifosz =
2250 musb_read_rxfifosz(musb_base);
2251 }
2252 if (is_host_enabled(musb)) {
2253 musb->context.index_regs[i].txtype =
2254 musb_readb(epio, MUSB_TXTYPE);
2255 musb->context.index_regs[i].txinterval =
2256 musb_readb(epio, MUSB_TXINTERVAL);
2257 musb->context.index_regs[i].rxtype =
2258 musb_readb(epio, MUSB_RXTYPE);
2259 musb->context.index_regs[i].rxinterval =
2260 musb_readb(epio, MUSB_RXINTERVAL);
2262 musb->context.index_regs[i].txfunaddr =
2263 musb_read_txfunaddr(musb_base, i);
2264 musb->context.index_regs[i].txhubaddr =
2265 musb_read_txhubaddr(musb_base, i);
2266 musb->context.index_regs[i].txhubport =
2267 musb_read_txhubport(musb_base, i);
2269 musb->context.index_regs[i].rxfunaddr =
2270 musb_read_rxfunaddr(musb_base, i);
2271 musb->context.index_regs[i].rxhubaddr =
2272 musb_read_rxhubaddr(musb_base, i);
2273 musb->context.index_regs[i].rxhubport =
2274 musb_read_rxhubport(musb_base, i);
2275 }
2276 }
2277 }
2279 static void musb_restore_context(struct musb *musb)
2280 {
2281 int i;
2282 void __iomem *musb_base = musb->mregs;
2283 void __iomem *ep_target_regs;
2284 void __iomem *epio;
2286 if (is_host_enabled(musb)) {
2287 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2288 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2289 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2290 }
2291 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2292 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2293 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2294 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2295 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2297 for (i = 0; i < musb->config->num_eps; ++i) {
2298 struct musb_hw_ep *hw_ep;
2300 hw_ep = &musb->endpoints[i];
2301 if (!hw_ep)
2302 continue;
2304 epio = hw_ep->regs;
2305 if (!epio)
2306 continue;
2308 musb_writeb(musb_base, MUSB_INDEX, i);
2309 musb_writew(epio, MUSB_TXMAXP,
2310 musb->context.index_regs[i].txmaxp);
2311 musb_writew(epio, MUSB_TXCSR,
2312 musb->context.index_regs[i].txcsr);
2313 musb_writew(epio, MUSB_RXMAXP,
2314 musb->context.index_regs[i].rxmaxp);
2315 musb_writew(epio, MUSB_RXCSR,
2316 musb->context.index_regs[i].rxcsr);
2318 if (musb->dyn_fifo) {
2319 musb_write_txfifosz(musb_base,
2320 musb->context.index_regs[i].txfifosz);
2321 musb_write_rxfifosz(musb_base,
2322 musb->context.index_regs[i].rxfifosz);
2323 musb_write_txfifoadd(musb_base,
2324 musb->context.index_regs[i].txfifoadd);
2325 musb_write_rxfifoadd(musb_base,
2326 musb->context.index_regs[i].rxfifoadd);
2327 }
2329 if (is_host_enabled(musb)) {
2330 musb_writeb(epio, MUSB_TXTYPE,
2331 musb->context.index_regs[i].txtype);
2332 musb_writeb(epio, MUSB_TXINTERVAL,
2333 musb->context.index_regs[i].txinterval);
2334 musb_writeb(epio, MUSB_RXTYPE,
2335 musb->context.index_regs[i].rxtype);
2336 musb_writeb(epio, MUSB_RXINTERVAL,
2338 musb->context.index_regs[i].rxinterval);
2339 musb_write_txfunaddr(musb_base, i,
2340 musb->context.index_regs[i].txfunaddr);
2341 musb_write_txhubaddr(musb_base, i,
2342 musb->context.index_regs[i].txhubaddr);
2343 musb_write_txhubport(musb_base, i,
2344 musb->context.index_regs[i].txhubport);
2346 ep_target_regs =
2347 musb_read_target_reg_base(i, musb_base);
2349 musb_write_rxfunaddr(ep_target_regs,
2350 musb->context.index_regs[i].rxfunaddr);
2351 musb_write_rxhubaddr(ep_target_regs,
2352 musb->context.index_regs[i].rxhubaddr);
2353 musb_write_rxhubport(ep_target_regs,
2354 musb->context.index_regs[i].rxhubport);
2355 }
2356 }
2357 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2358 }
2360 static int musb_suspend(struct device *dev)
2361 {
2362 struct musb *musb = dev_to_musb(dev);
2363 unsigned long flags;
2364 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2365 int ret = 0;
2367 spin_lock_irqsave(&musb->lock, flags);
2369 if (is_peripheral_active(musb)) {
2370 /*
2371 * Don't allow system suspend while peripheral mode
2372 * is actve and cable is connected to host.
2373 */
2374 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
2375 && (devctl & MUSB_DEVCTL_BDEVICE))
2376 ret = -EBUSY;
2377 } else if (is_host_active(musb)) {
2378 /* we know all the children are suspended; sometimes
2379 * they will even be wakeup-enabled.
2380 */
2381 }
2383 spin_unlock_irqrestore(&musb->lock, flags);
2384 return ret;
2385 }
2387 static int musb_resume_noirq(struct device *dev)
2388 {
2389 /* for static cmos like DaVinci, register values were preserved
2390 * unless for some reason the whole soc powered down or the USB
2391 * module got reset through the PSC (vs just being disabled).
2392 */
2393 return 0;
2394 }
2396 static int musb_runtime_suspend(struct device *dev)
2397 {
2398 struct musb *musb = dev_to_musb(dev);
2400 musb_save_context(musb);
2402 return 0;
2403 }
2405 static int musb_runtime_resume(struct device *dev)
2406 {
2407 struct musb *musb = dev_to_musb(dev);
2409 /*
2410 * When pm_runtime_get_sync called for the first time in driver
2411 * init, some of the structure is still not initialized which is
2412 * used in restore function. But clock needs to be
2413 * enabled before any register access, so
2414 * pm_runtime_get_sync has to be called.
2415 * Also context restore without save does not make
2416 * any sense
2417 */
2418 if (musb->first)
2419 musb->first = 0;
2420 else
2421 musb_restore_context(musb);
2424 return 0;
2425 }
2427 static const struct dev_pm_ops musb_dev_pm_ops = {
2428 .suspend = musb_suspend,
2429 .resume_noirq = musb_resume_noirq,
2430 .runtime_suspend = musb_runtime_suspend,
2431 .runtime_resume = musb_runtime_resume,
2432 };
2434 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2435 #else
2436 #define MUSB_DEV_PM_OPS NULL
2437 #endif
2439 static struct platform_driver musb_driver = {
2440 .driver = {
2441 .name = (char *)musb_driver_name,
2442 .bus = &platform_bus_type,
2443 .owner = THIS_MODULE,
2444 .pm = MUSB_DEV_PM_OPS,
2445 },
2446 .probe = musb_probe,
2447 .remove = __exit_p(musb_remove),
2448 .shutdown = musb_shutdown,
2449 };
2451 /*-------------------------------------------------------------------------*/
2453 static int __init musb_init(void)
2454 {
2455 if (usb_disabled())
2456 return 0;
2458 pr_info("%s: version " MUSB_VERSION ", "
2459 "?dma?"
2460 ", "
2461 "otg (peripheral+host)",
2462 musb_driver_name);
2463 return platform_driver_register(&musb_driver);
2464 }
2466 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2467 * and before usb gadget and host-side drivers start to register
2468 */
2469 fs_initcall(musb_init);
2471 static void __exit musb_cleanup(void)
2472 {
2473 platform_driver_unregister(&musb_driver);
2474 }
2475 module_exit(musb_cleanup);