1 /*
2 * MUSB OTG driver peripheral support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
46 #include "musb_core.h"
49 /* MUSB PERIPHERAL status 3-mar-2006:
50 *
51 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
52 * Minor glitches:
53 *
54 * + remote wakeup to Linux hosts work, but saw USBCV failures;
55 * in one test run (operator error?)
56 * + endpoint halt tests -- in both usbtest and usbcv -- seem
57 * to break when dma is enabled ... is something wrongly
58 * clearing SENDSTALL?
59 *
60 * - Mass storage behaved ok when last tested. Network traffic patterns
61 * (with lots of short transfers etc) need retesting; they turn up the
62 * worst cases of the DMA, since short packets are typical but are not
63 * required.
64 *
65 * - TX/IN
66 * + both pio and dma behave in with network and g_zero tests
67 * + no cppi throughput issues other than no-hw-queueing
68 * + failed with FLAT_REG (DaVinci)
69 * + seems to behave with double buffering, PIO -and- CPPI
70 * + with gadgetfs + AIO, requests got lost?
71 *
72 * - RX/OUT
73 * + both pio and dma behave in with network and g_zero tests
74 * + dma is slow in typical case (short_not_ok is clear)
75 * + double buffering ok with PIO
76 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
77 * + request lossage observed with gadgetfs
78 *
79 * - ISO not tested ... might work, but only weakly isochronous
80 *
81 * - Gadget driver disabling of softconnect during bind() is ignored; so
82 * drivers can't hold off host requests until userspace is ready.
83 * (Workaround: they can turn it off later.)
84 *
85 * - PORTABILITY (assumes PIO works):
86 * + DaVinci, basically works with cppi dma
87 * + OMAP 2430, ditto with mentor dma
88 * + TUSB 6010, platform-specific dma in the works
89 */
91 /* ----------------------------------------------------------------------- */
93 #define is_buffer_mapped(req) (is_dma_capable() && \
94 (req->map_state != UN_MAPPED))
96 /* Maps the buffer to dma */
98 static inline void map_dma_buffer(struct musb_request *request,
99 struct musb *musb, struct musb_ep *musb_ep)
100 {
101 int compatible = true;
102 struct dma_controller *dma = musb->dma_controller;
104 request->map_state = UN_MAPPED;
106 if (!is_dma_capable() || !musb_ep->dma)
107 return;
109 /* Check if DMA engine can handle this request.
110 * DMA code must reject the USB request explicitly.
111 * Default behaviour is to map the request.
112 */
113 if (dma->is_compatible)
114 compatible = dma->is_compatible(musb_ep->dma,
115 musb_ep->packet_sz, request->request.buf,
116 request->request.length);
117 if (!compatible)
118 return;
120 if (request->request.dma == DMA_ADDR_INVALID) {
121 request->request.dma = dma_map_single(
122 musb->controller,
123 request->request.buf,
124 request->request.length,
125 request->tx
126 ? DMA_TO_DEVICE
127 : DMA_FROM_DEVICE);
128 request->map_state = MUSB_MAPPED;
129 } else {
130 dma_sync_single_for_device(musb->controller,
131 request->request.dma,
132 request->request.length,
133 request->tx
134 ? DMA_TO_DEVICE
135 : DMA_FROM_DEVICE);
136 request->map_state = PRE_MAPPED;
137 }
138 }
140 /* Unmap the buffer from dma and maps it back to cpu */
141 static inline void unmap_dma_buffer(struct musb_request *request,
142 struct musb *musb)
143 {
144 if (!is_buffer_mapped(request))
145 return;
147 if (request->request.dma == DMA_ADDR_INVALID) {
148 dev_vdbg(musb->controller,
149 "not unmapping a never mapped buffer\n");
150 return;
151 }
152 if (request->map_state == MUSB_MAPPED) {
153 dma_unmap_single(musb->controller,
154 request->request.dma,
155 request->request.length,
156 request->tx
157 ? DMA_TO_DEVICE
158 : DMA_FROM_DEVICE);
159 request->request.dma = DMA_ADDR_INVALID;
160 } else { /* PRE_MAPPED */
161 dma_sync_single_for_cpu(musb->controller,
162 request->request.dma,
163 request->request.length,
164 request->tx
165 ? DMA_TO_DEVICE
166 : DMA_FROM_DEVICE);
167 }
168 request->map_state = UN_MAPPED;
169 }
171 /*
172 * Immediately complete a request.
173 *
174 * @param request the request to complete
175 * @param status the status to complete the request with
176 * Context: controller locked, IRQs blocked.
177 */
178 void musb_g_giveback(
179 struct musb_ep *ep,
180 struct usb_request *request,
181 int status)
182 __releases(ep->musb->lock)
183 __acquires(ep->musb->lock)
184 {
185 struct musb_request *req;
186 struct musb *musb;
187 int busy = ep->busy;
189 req = to_musb_request(request);
191 list_del(&req->list);
192 if (req->request.status == -EINPROGRESS)
193 req->request.status = status;
194 musb = req->musb;
196 ep->busy = 1;
197 spin_unlock(&musb->lock);
198 unmap_dma_buffer(req, musb);
199 if (request->status == 0)
200 dev_dbg(musb->controller, "%s done request %p, %d/%d\n",
201 ep->end_point.name, request,
202 req->request.actual, req->request.length);
203 else
204 dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
205 ep->end_point.name, request,
206 req->request.actual, req->request.length,
207 request->status);
208 req->request.complete(&req->ep->end_point, &req->request);
209 spin_lock(&musb->lock);
210 ep->busy = busy;
211 }
213 /* ----------------------------------------------------------------------- */
215 /*
216 * Abort requests queued to an endpoint using the status. Synchronous.
217 * caller locked controller and blocked irqs, and selected this ep.
218 */
219 static void nuke(struct musb_ep *ep, const int status)
220 {
221 struct musb *musb = ep->musb;
222 struct musb_request *req = NULL;
223 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
225 ep->busy = 1;
227 if (is_dma_capable() && ep->dma) {
228 struct dma_controller *c = ep->musb->dma_controller;
229 int value;
231 if (ep->is_in) {
232 /*
233 * The programming guide says that we must not clear
234 * the DMAMODE bit before DMAENAB, so we only
235 * clear it in the second write...
236 */
237 musb_writew(epio, MUSB_TXCSR,
238 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
239 musb_writew(epio, MUSB_TXCSR,
240 0 | MUSB_TXCSR_FLUSHFIFO);
241 } else {
242 musb_writew(epio, MUSB_RXCSR,
243 0 | MUSB_RXCSR_FLUSHFIFO);
244 musb_writew(epio, MUSB_RXCSR,
245 0 | MUSB_RXCSR_FLUSHFIFO);
246 }
248 value = c->channel_abort(ep->dma);
249 dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
250 ep->name, value);
251 c->channel_release(ep->dma);
252 ep->dma = NULL;
253 }
255 while (!list_empty(&ep->req_list)) {
256 req = list_first_entry(&ep->req_list, struct musb_request, list);
257 musb_g_giveback(ep, &req->request, status);
258 }
259 }
261 /* ----------------------------------------------------------------------- */
263 /* Data transfers - pure PIO, pure DMA, or mixed mode */
265 /*
266 * This assumes the separate CPPI engine is responding to DMA requests
267 * from the usb core ... sequenced a bit differently from mentor dma.
268 */
270 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
271 {
272 if (can_bulk_split(musb, ep->type))
273 return ep->hw_ep->max_packet_sz_tx;
274 else
275 return ep->packet_sz;
276 }
279 /* Peripheral tx (IN) using Mentor DMA works as follows:
280 Only mode 0 is used for transfers <= wPktSize,
281 mode 1 is used for larger transfers,
283 One of the following happens:
284 - Host sends IN token which causes an endpoint interrupt
285 -> TxAvail
286 -> if DMA is currently busy, exit.
287 -> if queue is non-empty, txstate().
289 - Request is queued by the gadget driver.
290 -> if queue was previously empty, txstate()
292 txstate()
293 -> start
294 /\ -> setup DMA
295 | (data is transferred to the FIFO, then sent out when
296 | IN token(s) are recd from Host.
297 | -> DMA interrupt on completion
298 | calls TxAvail.
299 | -> stop DMA, ~DMAENAB,
300 | -> set TxPktRdy for last short pkt or zlp
301 | -> Complete Request
302 | -> Continue next request (call txstate)
303 |___________________________________|
305 * Non-Mentor DMA engines can of course work differently, such as by
306 * upleveling from irq-per-packet to irq-per-buffer.
307 */
309 /*
310 * An endpoint is transmitting data. This can be called either from
311 * the IRQ routine or from ep.queue() to kickstart a request on an
312 * endpoint.
313 *
314 * Context: controller locked, IRQs blocked, endpoint selected
315 */
316 static void txstate(struct musb *musb, struct musb_request *req)
317 {
318 u8 epnum = req->epnum;
319 struct musb_ep *musb_ep;
320 void __iomem *epio = musb->endpoints[epnum].regs;
321 struct usb_request *request;
322 u16 fifo_count = 0, csr;
323 int use_dma = 0;
325 musb_ep = req->ep;
327 /* we shouldn't get here while DMA is active ... but we do ... */
328 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
329 dev_dbg(musb->controller, "dma pending...\n");
330 return;
331 }
333 /* read TXCSR before */
334 csr = musb_readw(epio, MUSB_TXCSR);
336 request = &req->request;
337 fifo_count = min(max_ep_writesize(musb, musb_ep),
338 (int)(request->length - request->actual));
340 if (csr & MUSB_TXCSR_TXPKTRDY) {
341 dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
342 musb_ep->end_point.name, csr);
343 return;
344 }
346 if (csr & MUSB_TXCSR_P_SENDSTALL) {
347 dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
348 musb_ep->end_point.name, csr);
349 return;
350 }
352 dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
353 epnum, musb_ep->packet_sz, fifo_count,
354 csr);
356 #ifndef CONFIG_MUSB_PIO_ONLY
357 if (is_buffer_mapped(req)) {
358 struct dma_controller *c = musb->dma_controller;
359 size_t request_size;
361 /* setup DMA, then program endpoint CSR */
362 request_size = min_t(size_t, request->length - request->actual,
363 musb_ep->dma->max_len);
365 use_dma = (request->dma != DMA_ADDR_INVALID);
367 /* MUSB_TXCSR_P_ISO is still set correctly */
369 if (is_inventra_dma(musb) || is_ux500_dma(musb)) {
370 if (request_size < musb_ep->packet_sz)
371 musb_ep->dma->desired_mode = 0;
372 else
373 musb_ep->dma->desired_mode = 1;
375 use_dma = use_dma && c->channel_program(
376 musb_ep->dma, musb_ep->packet_sz,
377 musb_ep->dma->desired_mode,
378 request->dma + request->actual, request_size);
379 if (use_dma) {
380 if (musb_ep->dma->desired_mode == 0) {
381 /*
382 * We must not clear the DMAMODE bit
383 * before the DMAENAB bit -- and the
384 * latter doesn't always get cleared
385 * before we get here...
386 */
387 csr &= ~(MUSB_TXCSR_AUTOSET
388 | MUSB_TXCSR_DMAENAB);
389 musb_writew(epio, MUSB_TXCSR, csr
390 | MUSB_TXCSR_P_WZC_BITS);
391 csr &= ~MUSB_TXCSR_DMAMODE;
392 csr |= (MUSB_TXCSR_DMAENAB |
393 MUSB_TXCSR_MODE);
394 /* against programming guide */
395 } else {
396 csr |= (MUSB_TXCSR_DMAENAB
397 | MUSB_TXCSR_DMAMODE
398 | MUSB_TXCSR_MODE);
399 if (!musb_ep->hb_mult)
400 csr |= MUSB_TXCSR_AUTOSET;
401 }
402 csr &= ~MUSB_TXCSR_P_UNDERRUN;
404 musb_writew(epio, MUSB_TXCSR, csr);
405 }
406 } else if (is_cppi_enabled(musb) || is_cppi41_enabled(musb)) {
407 /* program endpoint CSR first, then setup DMA */
408 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
409 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
410 MUSB_TXCSR_MODE;
411 musb_writew(epio, MUSB_TXCSR,
412 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
413 | csr);
415 /* ensure writebuffer is empty */
416 csr = musb_readw(epio, MUSB_TXCSR);
418 /* NOTE host side sets DMAENAB later than this; both are
419 * OK since the transfer dma glue (between CPPI & Mentor
420 * fifos) just tells CPPI it could start. Data only
421 * moves to the USB TX fifo when both fifos are ready.
422 */
424 /* "mode" is irrelevant here; handle terminating ZLPs
425 * like PIO does, since the hardware RNDIS mode seems
426 * unreliable except for the last-packet-is-already-
427 * short case.
428 */
429 use_dma = use_dma && c->channel_program(
430 musb_ep->dma, musb_ep->packet_sz,
431 0,
432 request->dma + request->actual,
433 request_size);
434 if (!use_dma) {
435 c->channel_release(musb_ep->dma);
436 musb_ep->dma = NULL;
437 csr &= ~MUSB_TXCSR_DMAENAB;
438 musb_writew(epio, MUSB_TXCSR, csr);
439 /* invariant: prequest->buf is non-null */
440 }
441 } else if (tusb_dma_omap(musb)) {
442 use_dma = use_dma && c->channel_program(
443 musb_ep->dma, musb_ep->packet_sz,
444 request->zero,
445 request->dma + request->actual,
446 request_size);
447 }
448 }
449 #endif
451 if (!use_dma) {
452 /*
453 * Unmap the dma buffer back to cpu if dma channel
454 * programming fails
455 */
456 unmap_dma_buffer(req, musb);
458 musb->ops->write_fifo(musb_ep->hw_ep, fifo_count,
459 (u8 *) (request->buf + request->actual));
460 request->actual += fifo_count;
461 csr |= MUSB_TXCSR_TXPKTRDY;
462 csr &= ~MUSB_TXCSR_P_UNDERRUN;
463 musb_writew(epio, MUSB_TXCSR, csr);
464 }
466 /* host may already have the data when this message shows... */
467 dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
468 musb_ep->end_point.name, use_dma ? "dma" : "pio",
469 request->actual, request->length,
470 musb_readw(epio, MUSB_TXCSR),
471 fifo_count,
472 musb_readw(epio, MUSB_TXMAXP));
473 }
475 /*
476 * FIFO state update (e.g. data ready).
477 * Called from IRQ, with controller locked.
478 */
479 void musb_g_tx(struct musb *musb, u8 epnum)
480 {
481 u16 csr;
482 struct musb_request *req;
483 struct usb_request *request;
484 u8 __iomem *mbase = musb->mregs;
485 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
486 void __iomem *epio = musb->endpoints[epnum].regs;
487 struct dma_channel *dma;
489 musb_ep_select(musb, mbase, epnum);
490 req = next_request(musb_ep);
491 request = &req->request;
493 csr = musb_readw(epio, MUSB_TXCSR);
494 dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
496 dma = is_dma_capable() ? musb_ep->dma : NULL;
498 /*
499 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
500 * probably rates reporting as a host error.
501 */
502 if (csr & MUSB_TXCSR_P_SENTSTALL) {
503 csr |= MUSB_TXCSR_P_WZC_BITS;
504 csr &= ~MUSB_TXCSR_P_SENTSTALL;
505 musb_writew(epio, MUSB_TXCSR, csr);
506 return;
507 }
509 if (csr & MUSB_TXCSR_P_UNDERRUN) {
510 /* We NAKed, no big deal... little reason to care. */
511 csr |= MUSB_TXCSR_P_WZC_BITS;
512 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
513 musb_writew(epio, MUSB_TXCSR, csr);
514 dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
515 epnum, request);
516 }
518 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
519 /*
520 * SHOULD NOT HAPPEN... has with CPPI though, after
521 * changing SENDSTALL (and other cases); harmless?
522 */
523 dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
524 return;
525 }
527 if (request) {
528 u8 is_dma = 0;
530 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
531 is_dma = 1;
532 csr |= MUSB_TXCSR_P_WZC_BITS;
533 csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN |
534 MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET);
535 musb_writew(epio, MUSB_TXCSR, csr);
536 /* Ensure writebuffer is empty. */
537 csr = musb_readw(epio, MUSB_TXCSR);
538 request->actual += musb_ep->dma->actual_len;
539 dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
540 epnum, csr, musb_ep->dma->actual_len, request);
541 }
543 /*
544 * First, maybe a terminating short packet. Some DMA
545 * engines might handle this by themselves.
546 */
547 if ((request->zero && request->length
548 && (request->length % musb_ep->packet_sz == 0)
549 && (request->actual == request->length))
550 || ((is_inventra_dma(musb) || is_ux500_dma(musb)) &&
551 is_dma && (!dma->desired_mode || (request->actual &
552 (musb_ep->packet_sz - 1))))
553 ) {
554 /*
555 * On DMA completion, FIFO may not be
556 * available yet...
557 */
558 if (csr & MUSB_TXCSR_TXPKTRDY)
559 return;
561 dev_dbg(musb->controller, "sending zero pkt\n");
562 musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
563 | MUSB_TXCSR_TXPKTRDY);
564 request->zero = 0;
565 }
567 if (request->actual == request->length) {
568 musb_g_giveback(musb_ep, request, 0);
569 req = musb_ep->desc ? next_request(musb_ep) : NULL;
570 if (!req) {
571 dev_dbg(musb->controller, "%s idle now\n",
572 musb_ep->end_point.name);
573 return;
574 }
575 }
577 txstate(musb, req);
578 }
579 }
581 /* ------------------------------------------------------------ */
583 /* Peripheral rx (OUT) using Mentor DMA works as follows:
584 - Only mode 0 is used.
586 - Request is queued by the gadget class driver.
587 -> if queue was previously empty, rxstate()
589 - Host sends OUT token which causes an endpoint interrupt
590 /\ -> RxReady
591 | -> if request queued, call rxstate
592 | /\ -> setup DMA
593 | | -> DMA interrupt on completion
594 | | -> RxReady
595 | | -> stop DMA
596 | | -> ack the read
597 | | -> if data recd = max expected
598 | | by the request, or host
599 | | sent a short packet,
600 | | complete the request,
601 | | and start the next one.
602 | |_____________________________________|
603 | else just wait for the host
604 | to send the next OUT token.
605 |__________________________________________________|
607 * Non-Mentor DMA engines can of course work differently.
608 */
610 /*
611 * Context: controller locked, IRQs blocked, endpoint selected
612 */
613 static void rxstate(struct musb *musb, struct musb_request *req)
614 {
615 const u8 epnum = req->epnum;
616 struct usb_request *request = &req->request;
617 struct musb_ep *musb_ep;
618 void __iomem *epio = musb->endpoints[epnum].regs;
619 unsigned fifo_count = 0;
620 u16 len;
621 u16 csr = musb_readw(epio, MUSB_RXCSR);
622 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
623 u8 use_mode_1;
625 if (hw_ep->is_shared_fifo)
626 musb_ep = &hw_ep->ep_in;
627 else
628 musb_ep = &hw_ep->ep_out;
630 len = musb_ep->packet_sz;
632 /* We shouldn't get here while DMA is active, but we do... */
633 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
634 dev_dbg(musb->controller, "DMA pending...\n");
635 return;
636 }
638 if (csr & MUSB_RXCSR_P_SENDSTALL) {
639 dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
640 musb_ep->end_point.name, csr);
641 return;
642 }
644 if ((is_cppi_enabled(musb) || is_cppi41_enabled(musb)) &&
645 is_buffer_mapped(req)) {
646 struct dma_controller *c = musb->dma_controller;
647 struct dma_channel *channel = musb_ep->dma;
649 /* NOTE: CPPI won't actually stop advancing the DMA
650 * queue after short packet transfers, so this is almost
651 * always going to run as IRQ-per-packet DMA so that
652 * faults will be handled correctly.
653 */
654 if (c->channel_program(channel,
655 musb_ep->packet_sz,
656 !request->short_not_ok,
657 request->dma + request->actual,
658 request->length - request->actual)) {
660 /* make sure that if an rxpkt arrived after the irq,
661 * the cppi engine will be ready to take it as soon
662 * as DMA is enabled
663 */
664 csr &= ~(MUSB_RXCSR_AUTOCLEAR
665 | MUSB_RXCSR_DMAMODE);
666 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
667 musb_writew(epio, MUSB_RXCSR, csr);
668 return;
669 }
670 }
672 if (csr & MUSB_RXCSR_RXPKTRDY) {
673 len = musb_readw(epio, MUSB_RXCOUNT);
675 /*
676 * Enable Mode 1 on RX transfers only when short_not_ok flag
677 * is set. Currently short_not_ok flag is set only from
678 * file_storage and f_mass_storage drivers
679 */
681 if (request->short_not_ok && len == musb_ep->packet_sz)
682 use_mode_1 = 1;
683 else
684 use_mode_1 = 0;
686 if (request->actual < request->length) {
687 if (is_buffer_mapped(req) && is_inventra_dma(musb)) {
688 struct dma_controller *c;
689 struct dma_channel *channel;
690 int use_dma = 0;
692 c = musb->dma_controller;
693 channel = musb_ep->dma;
695 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
696 * mode 0 only. So we do not get endpoint interrupts due to DMA
697 * completion. We only get interrupts from DMA controller.
698 *
699 * We could operate in DMA mode 1 if we knew the size of the tranfer
700 * in advance. For mass storage class, request->length = what the host
701 * sends, so that'd work. But for pretty much everything else,
702 * request->length is routinely more than what the host sends. For
703 * most these gadgets, end of is signified either by a short packet,
704 * or filling the last byte of the buffer. (Sending extra data in
705 * that last pckate should trigger an overflow fault.) But in mode 1,
706 * we don't get DMA completion interrupt for short packets.
707 *
708 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
709 * to get endpoint interrupt on every DMA req, but that didn't seem
710 * to work reliably.
711 *
712 * REVISIT an updated g_file_storage can set req->short_not_ok, which
713 * then becomes usable as a runtime "use mode 1" hint...
714 */
716 /* Experimental: Mode1 works with mass storage use cases */
717 if (use_mode_1) {
718 csr |= MUSB_RXCSR_AUTOCLEAR;
719 musb_writew(epio, MUSB_RXCSR, csr);
720 csr |= MUSB_RXCSR_DMAENAB;
721 musb_writew(epio, MUSB_RXCSR, csr);
723 /*
724 * this special sequence (enabling and then
725 * disabling MUSB_RXCSR_DMAMODE) is required
726 * to get DMAReq to activate
727 */
728 musb_writew(epio, MUSB_RXCSR,
729 csr | MUSB_RXCSR_DMAMODE);
730 musb_writew(epio, MUSB_RXCSR, csr);
732 } else {
733 if (!musb_ep->hb_mult &&
734 musb_ep->hw_ep->rx_double_buffered)
735 csr |= MUSB_RXCSR_AUTOCLEAR;
736 csr |= MUSB_RXCSR_DMAENAB;
737 musb_writew(epio, MUSB_RXCSR, csr);
738 }
740 if (request->actual < request->length) {
741 int transfer_size = 0;
742 if (use_mode_1) {
743 transfer_size = min(request->length - request->actual,
744 channel->max_len);
745 musb_ep->dma->desired_mode = 1;
746 } else {
747 transfer_size = min(request->length - request->actual,
748 (unsigned)len);
749 musb_ep->dma->desired_mode = 0;
750 }
752 use_dma = c->channel_program(
753 channel,
754 musb_ep->packet_sz,
755 channel->desired_mode,
756 request->dma
757 + request->actual,
758 transfer_size);
759 }
761 if (use_dma)
762 return;
763 }
764 if (is_ux500_dma(musb) && (is_buffer_mapped(req)) &&
765 (request->actual < request->length)) {
767 struct dma_controller *c;
768 struct dma_channel *channel;
769 int transfer_size = 0;
771 c = musb->dma_controller;
772 channel = musb_ep->dma;
774 /* In case first packet is short */
775 if (len < musb_ep->packet_sz)
776 transfer_size = len;
777 else if (request->short_not_ok)
778 transfer_size = min(request->length -
779 request->actual,
780 channel->max_len);
781 else
782 transfer_size = min(request->length -
783 request->actual,
784 (unsigned)len);
786 csr &= ~MUSB_RXCSR_DMAMODE;
787 csr |= (MUSB_RXCSR_DMAENAB |
788 MUSB_RXCSR_AUTOCLEAR);
790 musb_writew(epio, MUSB_RXCSR, csr);
792 if (transfer_size <= musb_ep->packet_sz) {
793 musb_ep->dma->desired_mode = 0;
794 } else {
795 musb_ep->dma->desired_mode = 1;
796 /* Mode must be set after DMAENAB */
797 csr |= MUSB_RXCSR_DMAMODE;
798 musb_writew(epio, MUSB_RXCSR, csr);
799 }
801 if (c->channel_program(channel,
802 musb_ep->packet_sz,
803 channel->desired_mode,
804 request->dma
805 + request->actual,
806 transfer_size))
808 return;
809 }
811 fifo_count = request->length - request->actual;
812 dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
813 musb_ep->end_point.name,
814 len, fifo_count,
815 musb_ep->packet_sz);
817 fifo_count = min_t(unsigned, len, fifo_count);
819 if (tusb_dma_omap(musb) && is_buffer_mapped(req)) {
820 struct dma_controller *c = musb->dma_controller;
821 struct dma_channel *channel = musb_ep->dma;
822 u32 dma_addr = request->dma + request->actual;
823 int ret;
825 ret = c->channel_program(channel,
826 musb_ep->packet_sz,
827 channel->desired_mode,
828 dma_addr,
829 fifo_count);
830 if (ret)
831 return;
832 }
834 /*
835 * Unmap the dma buffer back to cpu if dma channel
836 * programming fails. This buffer is mapped if the
837 * channel allocation is successful
838 */
839 if (is_buffer_mapped(req)) {
840 unmap_dma_buffer(req, musb);
842 /*
843 * Clear DMAENAB and AUTOCLEAR for the
844 * PIO mode transfer
845 */
846 csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR);
847 musb_writew(epio, MUSB_RXCSR, csr);
848 }
850 musb->ops->read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
851 (request->buf + request->actual));
852 request->actual += fifo_count;
854 /* REVISIT if we left anything in the fifo, flush
855 * it and report -EOVERFLOW
856 */
858 /* ack the read! */
859 csr |= MUSB_RXCSR_P_WZC_BITS;
860 csr &= ~MUSB_RXCSR_RXPKTRDY;
861 musb_writew(epio, MUSB_RXCSR, csr);
862 }
863 }
865 /* reach the end or short packet detected */
866 if (request->actual == request->length || len < musb_ep->packet_sz)
867 musb_g_giveback(musb_ep, request, 0);
868 }
870 /*
871 * Data ready for a request; called from IRQ
872 */
873 void musb_g_rx(struct musb *musb, u8 epnum)
874 {
875 u16 csr;
876 struct musb_request *req;
877 struct usb_request *request;
878 void __iomem *mbase = musb->mregs;
879 struct musb_ep *musb_ep;
880 void __iomem *epio = musb->endpoints[epnum].regs;
881 struct dma_channel *dma;
882 struct musb_hw_ep *hw_ep = &musb->endpoints[epnum];
884 if (hw_ep->is_shared_fifo)
885 musb_ep = &hw_ep->ep_in;
886 else
887 musb_ep = &hw_ep->ep_out;
889 musb_ep_select(musb, mbase, epnum);
891 req = next_request(musb_ep);
892 if (!req)
893 return;
895 request = &req->request;
897 csr = musb_readw(epio, MUSB_RXCSR);
898 dma = is_dma_capable() ? musb_ep->dma : NULL;
900 dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
901 csr, dma ? " (dma)" : "", request);
903 if (csr & MUSB_RXCSR_P_SENTSTALL) {
904 csr |= MUSB_RXCSR_P_WZC_BITS;
905 csr &= ~MUSB_RXCSR_P_SENTSTALL;
906 musb_writew(epio, MUSB_RXCSR, csr);
907 return;
908 }
910 if (csr & MUSB_RXCSR_P_OVERRUN) {
911 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
912 csr &= ~MUSB_RXCSR_P_OVERRUN;
913 musb_writew(epio, MUSB_RXCSR, csr);
915 dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
916 if (request->status == -EINPROGRESS)
917 request->status = -EOVERFLOW;
918 }
919 if (csr & MUSB_RXCSR_INCOMPRX) {
920 /* REVISIT not necessarily an error */
921 dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
922 }
924 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
925 /* "should not happen"; likely RXPKTRDY pending for DMA */
926 dev_dbg(musb->controller, "%s busy, csr %04x\n",
927 musb_ep->end_point.name, csr);
928 return;
929 }
931 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
932 csr &= ~(MUSB_RXCSR_AUTOCLEAR
933 | MUSB_RXCSR_DMAENAB
934 | MUSB_RXCSR_DMAMODE);
935 musb_writew(epio, MUSB_RXCSR,
936 MUSB_RXCSR_P_WZC_BITS | csr);
938 request->actual += musb_ep->dma->actual_len;
940 dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
941 epnum, csr,
942 musb_readw(epio, MUSB_RXCSR),
943 musb_ep->dma->actual_len, request);
945 if (is_inventra_dma(musb) || tusb_dma_omap(musb)
946 || is_ux500_dma(musb)) {
947 /* Autoclear doesn't clear RxPktRdy for short packets */
948 if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
949 || (dma->actual_len
950 & (musb_ep->packet_sz - 1))) {
951 /* ack the read! */
952 csr &= ~MUSB_RXCSR_RXPKTRDY;
953 musb_writew(epio, MUSB_RXCSR, csr);
954 }
956 /* incomplete, and not short? wait for next IN packet */
957 if ((request->actual < request->length)
958 && (musb_ep->dma->actual_len
959 == musb_ep->packet_sz)) {
960 /* In double buffer case, continue to unload
961 * fifo if there is Rx packet in FIFO.
962 **/
963 csr = musb_readw(epio, MUSB_RXCSR);
964 if ((csr & MUSB_RXCSR_RXPKTRDY) &&
965 hw_ep->rx_double_buffered)
966 rxstate(musb, to_musb_request(request));
967 return;
968 }
969 }
970 musb_g_giveback(musb_ep, request, 0);
972 req = next_request(musb_ep);
973 if (!req)
974 return;
975 }
976 /* Analyze request */
977 rxstate(musb, req);
978 }
980 /* ------------------------------------------------------------ */
982 static int musb_gadget_enable(struct usb_ep *ep,
983 const struct usb_endpoint_descriptor *desc)
984 {
985 unsigned long flags;
986 struct musb_ep *musb_ep;
987 struct musb_hw_ep *hw_ep;
988 void __iomem *regs;
989 struct musb *musb;
990 void __iomem *mbase;
991 u8 epnum;
992 u16 csr;
993 unsigned tmp;
994 int status = -EINVAL;
996 if (!ep || !desc)
997 return -EINVAL;
999 musb_ep = to_musb_ep(ep);
1000 hw_ep = musb_ep->hw_ep;
1001 regs = hw_ep->regs;
1002 musb = musb_ep->musb;
1003 mbase = musb->mregs;
1004 epnum = musb_ep->current_epnum;
1006 spin_lock_irqsave(&musb->lock, flags);
1008 if (musb_ep->desc) {
1009 status = -EBUSY;
1010 goto fail;
1011 }
1012 musb_ep->type = usb_endpoint_type(desc);
1014 /* check direction and (later) maxpacket size against endpoint */
1015 if (usb_endpoint_num(desc) != epnum)
1016 goto fail;
1018 /* REVISIT this rules out high bandwidth periodic transfers */
1019 tmp = usb_endpoint_maxp(desc);
1020 if (tmp & ~0x07ff) {
1021 int ok;
1023 if (usb_endpoint_dir_in(desc))
1024 ok = musb->hb_iso_tx;
1025 else
1026 ok = musb->hb_iso_rx;
1028 if (!ok) {
1029 dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
1030 goto fail;
1031 }
1032 musb_ep->hb_mult = (tmp >> 11) & 3;
1033 } else {
1034 musb_ep->hb_mult = 0;
1035 }
1037 musb_ep->packet_sz = tmp & 0x7ff;
1038 tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1);
1040 /* enable the interrupts for the endpoint, set the endpoint
1041 * packet size (or fail), set the mode, clear the fifo
1042 */
1043 musb_ep_select(musb, mbase, epnum);
1044 if (usb_endpoint_dir_in(desc)) {
1045 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1047 if (hw_ep->is_shared_fifo)
1048 musb_ep->is_in = 1;
1049 if (!musb_ep->is_in)
1050 goto fail;
1052 if (tmp > hw_ep->max_packet_sz_tx) {
1053 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1054 goto fail;
1055 }
1057 int_txe |= (1 << epnum);
1058 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1060 /* REVISIT if can_bulk_split(), use by updating "tmp";
1061 * likewise high bandwidth periodic tx
1062 */
1063 /* Set TXMAXP with the FIFO size of the endpoint
1064 * to disable double buffering mode.
1065 */
1066 if (musb->double_buffer_not_ok)
1067 musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx);
1068 else
1069 musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz
1070 | (musb_ep->hb_mult << 11));
1072 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
1073 if (musb_readw(regs, MUSB_TXCSR)
1074 & MUSB_TXCSR_FIFONOTEMPTY)
1075 csr |= MUSB_TXCSR_FLUSHFIFO;
1076 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1077 csr |= MUSB_TXCSR_P_ISO;
1079 /* set twice in case of double buffering */
1080 musb_writew(regs, MUSB_TXCSR, csr);
1081 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1082 musb_writew(regs, MUSB_TXCSR, csr);
1084 } else {
1085 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
1087 if (hw_ep->is_shared_fifo)
1088 musb_ep->is_in = 0;
1089 if (musb_ep->is_in)
1090 goto fail;
1092 if (tmp > hw_ep->max_packet_sz_rx) {
1093 dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
1094 goto fail;
1095 }
1097 int_rxe |= (1 << epnum);
1098 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
1100 /* REVISIT if can_bulk_combine() use by updating "tmp"
1101 * likewise high bandwidth periodic rx
1102 */
1103 /* Set RXMAXP with the FIFO size of the endpoint
1104 * to disable double buffering mode.
1105 */
1106 if (musb->double_buffer_not_ok)
1107 musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx);
1108 else
1109 musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz
1110 | (musb_ep->hb_mult << 11));
1112 /* force shared fifo to OUT-only mode */
1113 if (hw_ep->is_shared_fifo) {
1114 csr = musb_readw(regs, MUSB_TXCSR);
1115 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
1116 musb_writew(regs, MUSB_TXCSR, csr);
1117 }
1119 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
1120 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
1121 csr |= MUSB_RXCSR_P_ISO;
1122 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
1123 csr |= MUSB_RXCSR_DISNYET;
1125 /* set twice in case of double buffering */
1126 musb_writew(regs, MUSB_RXCSR, csr);
1127 musb_writew(regs, MUSB_RXCSR, csr);
1128 }
1130 /* NOTE: all the I/O code _should_ work fine without DMA, in case
1131 * for some reason you run out of channels here.
1132 */
1133 if (is_dma_capable() && musb->dma_controller) {
1134 struct dma_controller *c = musb->dma_controller;
1136 musb_ep->dma = c->channel_alloc(c, hw_ep,
1137 (desc->bEndpointAddress & USB_DIR_IN));
1138 } else
1139 musb_ep->dma = NULL;
1141 musb_ep->desc = desc;
1142 musb_ep->busy = 0;
1143 musb_ep->wedged = 0;
1144 status = 0;
1146 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1147 musb_driver_name, musb_ep->end_point.name,
1148 ({ char *s; switch (musb_ep->type) {
1149 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
1150 case USB_ENDPOINT_XFER_INT: s = "int"; break;
1151 default: s = "iso"; break;
1152 }; s; }),
1153 musb_ep->is_in ? "IN" : "OUT",
1154 musb_ep->dma ? "dma, " : "",
1155 musb_ep->packet_sz);
1157 schedule_work(&musb->irq_work);
1159 fail:
1160 spin_unlock_irqrestore(&musb->lock, flags);
1161 return status;
1162 }
1164 /*
1165 * Disable an endpoint flushing all requests queued.
1166 */
1167 static int musb_gadget_disable(struct usb_ep *ep)
1168 {
1169 unsigned long flags;
1170 struct musb *musb;
1171 u8 epnum;
1172 struct musb_ep *musb_ep;
1173 void __iomem *epio;
1174 int status = 0;
1176 musb_ep = to_musb_ep(ep);
1177 musb = musb_ep->musb;
1178 epnum = musb_ep->current_epnum;
1179 epio = musb->endpoints[epnum].regs;
1181 spin_lock_irqsave(&musb->lock, flags);
1182 musb_ep_select(musb, musb->mregs, epnum);
1184 /* zero the endpoint sizes */
1185 if (musb_ep->is_in) {
1186 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1187 int_txe &= ~(1 << epnum);
1188 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1189 musb_writew(epio, MUSB_TXMAXP, 0);
1190 } else {
1191 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1192 int_rxe &= ~(1 << epnum);
1193 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1194 musb_writew(epio, MUSB_RXMAXP, 0);
1195 }
1197 musb_ep->desc = NULL;
1199 /* abort all pending DMA and requests */
1200 nuke(musb_ep, -ESHUTDOWN);
1202 schedule_work(&musb->irq_work);
1204 spin_unlock_irqrestore(&(musb->lock), flags);
1206 dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
1208 return status;
1209 }
1211 /*
1212 * Allocate a request for an endpoint.
1213 * Reused by ep0 code.
1214 */
1215 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1216 {
1217 struct musb_ep *musb_ep = to_musb_ep(ep);
1218 struct musb *musb = musb_ep->musb;
1219 struct musb_request *request = NULL;
1221 request = kzalloc(sizeof *request, gfp_flags);
1222 if (!request) {
1223 dev_dbg(musb->controller, "not enough memory\n");
1224 return NULL;
1225 }
1227 request->request.dma = DMA_ADDR_INVALID;
1228 request->epnum = musb_ep->current_epnum;
1229 request->ep = musb_ep;
1231 return &request->request;
1232 }
1234 /*
1235 * Free a request
1236 * Reused by ep0 code.
1237 */
1238 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1239 {
1240 kfree(to_musb_request(req));
1241 }
1243 static LIST_HEAD(buffers);
1245 struct free_record {
1246 struct list_head list;
1247 struct device *dev;
1248 unsigned bytes;
1249 dma_addr_t dma;
1250 };
1252 /*
1253 * Context: controller locked, IRQs blocked.
1254 */
1255 void musb_ep_restart(struct musb *musb, struct musb_request *req)
1256 {
1257 dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
1258 req->tx ? "TX/IN" : "RX/OUT",
1259 &req->request, req->request.length, req->epnum);
1261 musb_ep_select(musb, musb->mregs, req->epnum);
1262 if (req->tx)
1263 txstate(musb, req);
1264 else
1265 rxstate(musb, req);
1266 }
1268 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1269 gfp_t gfp_flags)
1270 {
1271 struct musb_ep *musb_ep;
1272 struct musb_request *request;
1273 struct musb *musb;
1274 int status = 0;
1275 unsigned long lockflags;
1277 if (!ep || !req)
1278 return -EINVAL;
1279 if (!req->buf)
1280 return -ENODATA;
1282 musb_ep = to_musb_ep(ep);
1283 musb = musb_ep->musb;
1285 request = to_musb_request(req);
1286 request->musb = musb;
1288 if (request->ep != musb_ep)
1289 return -EINVAL;
1291 dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
1293 /* request is mine now... */
1294 request->request.actual = 0;
1295 request->request.status = -EINPROGRESS;
1296 request->epnum = musb_ep->current_epnum;
1297 request->tx = musb_ep->is_in;
1299 map_dma_buffer(request, musb, musb_ep);
1301 spin_lock_irqsave(&musb->lock, lockflags);
1303 /* don't queue if the ep is down */
1304 if (!musb_ep->desc) {
1305 dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
1306 req, ep->name, "disabled");
1307 status = -ESHUTDOWN;
1308 goto cleanup;
1309 }
1311 /* add request to the list */
1312 list_add_tail(&request->list, &musb_ep->req_list);
1314 /* it this is the head of the queue, start i/o ... */
1315 if (!musb_ep->busy && &request->list == musb_ep->req_list.next)
1316 musb_ep_restart(musb, request);
1318 cleanup:
1319 spin_unlock_irqrestore(&musb->lock, lockflags);
1320 return status;
1321 }
1323 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1324 {
1325 struct musb_ep *musb_ep = to_musb_ep(ep);
1326 struct musb_request *req = to_musb_request(request);
1327 struct musb_request *r;
1328 unsigned long flags;
1329 int status = 0;
1330 struct musb *musb = musb_ep->musb;
1332 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1333 return -EINVAL;
1335 spin_lock_irqsave(&musb->lock, flags);
1337 list_for_each_entry(r, &musb_ep->req_list, list) {
1338 if (r == req)
1339 break;
1340 }
1341 if (r != req) {
1342 dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
1343 status = -EINVAL;
1344 goto done;
1345 }
1347 /* if the hardware doesn't have the request, easy ... */
1348 if (musb_ep->req_list.next != &req->list || musb_ep->busy)
1349 musb_g_giveback(musb_ep, request, -ECONNRESET);
1351 /* ... else abort the dma transfer ... */
1352 else if (is_dma_capable() && musb_ep->dma) {
1353 struct dma_controller *c = musb->dma_controller;
1355 musb_ep_select(musb, musb->mregs, musb_ep->current_epnum);
1356 if (c->channel_abort)
1357 status = c->channel_abort(musb_ep->dma);
1358 else
1359 status = -EBUSY;
1360 if (status == 0)
1361 musb_g_giveback(musb_ep, request, -ECONNRESET);
1362 } else {
1363 /* NOTE: by sticking to easily tested hardware/driver states,
1364 * we leave counting of in-flight packets imprecise.
1365 */
1366 musb_g_giveback(musb_ep, request, -ECONNRESET);
1367 }
1369 done:
1370 spin_unlock_irqrestore(&musb->lock, flags);
1371 return status;
1372 }
1374 /*
1375 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1376 * data but will queue requests.
1377 *
1378 * exported to ep0 code
1379 */
1380 static int musb_gadget_set_halt(struct usb_ep *ep, int value)
1381 {
1382 struct musb_ep *musb_ep = to_musb_ep(ep);
1383 u8 epnum = musb_ep->current_epnum;
1384 struct musb *musb = musb_ep->musb;
1385 void __iomem *epio = musb->endpoints[epnum].regs;
1386 void __iomem *mbase;
1387 unsigned long flags;
1388 u16 csr;
1389 struct musb_request *request;
1390 int status = 0;
1392 if (!ep)
1393 return -EINVAL;
1394 mbase = musb->mregs;
1396 spin_lock_irqsave(&musb->lock, flags);
1398 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1399 status = -EINVAL;
1400 goto done;
1401 }
1403 musb_ep_select(musb, mbase, epnum);
1405 request = next_request(musb_ep);
1406 if (value) {
1407 if (request) {
1408 dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
1409 ep->name);
1410 status = -EAGAIN;
1411 goto done;
1412 }
1413 /* Cannot portably stall with non-empty FIFO */
1414 if (musb_ep->is_in) {
1415 csr = musb_readw(epio, MUSB_TXCSR);
1416 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1417 dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
1418 status = -EAGAIN;
1419 goto done;
1420 }
1421 }
1422 } else
1423 musb_ep->wedged = 0;
1425 /* set/clear the stall and toggle bits */
1426 dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1427 if (musb_ep->is_in) {
1428 csr = musb_readw(epio, MUSB_TXCSR);
1429 csr |= MUSB_TXCSR_P_WZC_BITS
1430 | MUSB_TXCSR_CLRDATATOG;
1431 if (value)
1432 csr |= MUSB_TXCSR_P_SENDSTALL;
1433 else
1434 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1435 | MUSB_TXCSR_P_SENTSTALL);
1436 csr &= ~MUSB_TXCSR_TXPKTRDY;
1437 musb_writew(epio, MUSB_TXCSR, csr);
1438 } else {
1439 csr = musb_readw(epio, MUSB_RXCSR);
1440 csr |= MUSB_RXCSR_P_WZC_BITS
1441 | MUSB_RXCSR_FLUSHFIFO
1442 | MUSB_RXCSR_CLRDATATOG;
1443 if (value)
1444 csr |= MUSB_RXCSR_P_SENDSTALL;
1445 else
1446 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1447 | MUSB_RXCSR_P_SENTSTALL);
1448 musb_writew(epio, MUSB_RXCSR, csr);
1449 }
1451 /* maybe start the first request in the queue */
1452 if (!musb_ep->busy && !value && request) {
1453 dev_dbg(musb->controller, "restarting the request\n");
1454 musb_ep_restart(musb, request);
1455 }
1457 done:
1458 spin_unlock_irqrestore(&musb->lock, flags);
1459 return status;
1460 }
1462 /*
1463 * Sets the halt feature with the clear requests ignored
1464 */
1465 static int musb_gadget_set_wedge(struct usb_ep *ep)
1466 {
1467 struct musb_ep *musb_ep = to_musb_ep(ep);
1469 if (!ep)
1470 return -EINVAL;
1472 musb_ep->wedged = 1;
1474 return usb_ep_set_halt(ep);
1475 }
1477 static int musb_gadget_fifo_status(struct usb_ep *ep)
1478 {
1479 struct musb_ep *musb_ep = to_musb_ep(ep);
1480 void __iomem *epio = musb_ep->hw_ep->regs;
1481 int retval = -EINVAL;
1483 if (musb_ep->desc && !musb_ep->is_in) {
1484 struct musb *musb = musb_ep->musb;
1485 int epnum = musb_ep->current_epnum;
1486 void __iomem *mbase = musb->mregs;
1487 unsigned long flags;
1489 spin_lock_irqsave(&musb->lock, flags);
1491 musb_ep_select(musb, mbase, epnum);
1492 /* FIXME return zero unless RXPKTRDY is set */
1493 retval = musb_readw(epio, MUSB_RXCOUNT);
1495 spin_unlock_irqrestore(&musb->lock, flags);
1496 }
1497 return retval;
1498 }
1500 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1501 {
1502 struct musb_ep *musb_ep = to_musb_ep(ep);
1503 struct musb *musb = musb_ep->musb;
1504 u8 epnum = musb_ep->current_epnum;
1505 void __iomem *epio = musb->endpoints[epnum].regs;
1506 void __iomem *mbase;
1507 unsigned long flags;
1508 u16 csr, int_txe;
1510 mbase = musb->mregs;
1512 spin_lock_irqsave(&musb->lock, flags);
1513 musb_ep_select(musb, mbase, (u8) epnum);
1515 /* disable interrupts */
1516 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1517 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1519 if (musb_ep->is_in) {
1520 csr = musb_readw(epio, MUSB_TXCSR);
1521 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1522 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1523 /*
1524 * Setting both TXPKTRDY and FLUSHFIFO makes controller
1525 * to interrupt current FIFO loading, but not flushing
1526 * the already loaded ones.
1527 */
1528 csr &= ~MUSB_TXCSR_TXPKTRDY;
1529 musb_writew(epio, MUSB_TXCSR, csr);
1530 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1531 musb_writew(epio, MUSB_TXCSR, csr);
1532 }
1533 } else {
1534 csr = musb_readw(epio, MUSB_RXCSR);
1535 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1536 musb_writew(epio, MUSB_RXCSR, csr);
1537 musb_writew(epio, MUSB_RXCSR, csr);
1538 }
1540 /* re-enable interrupt */
1541 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1542 spin_unlock_irqrestore(&musb->lock, flags);
1543 }
1545 static const struct usb_ep_ops musb_ep_ops = {
1546 .enable = musb_gadget_enable,
1547 .disable = musb_gadget_disable,
1548 .alloc_request = musb_alloc_request,
1549 .free_request = musb_free_request,
1550 .queue = musb_gadget_queue,
1551 .dequeue = musb_gadget_dequeue,
1552 .set_halt = musb_gadget_set_halt,
1553 .set_wedge = musb_gadget_set_wedge,
1554 .fifo_status = musb_gadget_fifo_status,
1555 .fifo_flush = musb_gadget_fifo_flush
1556 };
1558 /* ----------------------------------------------------------------------- */
1560 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1561 {
1562 struct musb *musb = gadget_to_musb(gadget);
1564 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1565 }
1567 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1568 {
1569 struct musb *musb = gadget_to_musb(gadget);
1570 void __iomem *mregs = musb->mregs;
1571 unsigned long flags;
1572 int status = -EINVAL;
1573 u8 power, devctl;
1574 int retries;
1576 spin_lock_irqsave(&musb->lock, flags);
1578 switch (musb->xceiv->state) {
1579 case OTG_STATE_B_PERIPHERAL:
1580 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1581 * that's part of the standard usb 1.1 state machine, and
1582 * doesn't affect OTG transitions.
1583 */
1584 if (musb->may_wakeup && musb->is_suspended)
1585 break;
1586 goto done;
1587 case OTG_STATE_B_IDLE:
1588 /* Start SRP ... OTG not required. */
1589 devctl = musb_readb(mregs, MUSB_DEVCTL);
1590 dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
1591 devctl |= MUSB_DEVCTL_SESSION;
1592 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1593 devctl = musb_readb(mregs, MUSB_DEVCTL);
1594 retries = 100;
1595 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1596 devctl = musb_readb(mregs, MUSB_DEVCTL);
1597 if (retries-- < 1)
1598 break;
1599 }
1600 retries = 10000;
1601 while (devctl & MUSB_DEVCTL_SESSION) {
1602 devctl = musb_readb(mregs, MUSB_DEVCTL);
1603 if (retries-- < 1)
1604 break;
1605 }
1607 spin_unlock_irqrestore(&musb->lock, flags);
1608 otg_start_srp(musb->xceiv);
1609 spin_lock_irqsave(&musb->lock, flags);
1611 /* Block idling for at least 1s */
1612 musb_platform_try_idle(musb,
1613 jiffies + msecs_to_jiffies(1 * HZ));
1615 status = 0;
1616 goto done;
1617 default:
1618 dev_dbg(musb->controller, "Unhandled wake: %s\n",
1619 otg_state_string(musb->xceiv->state));
1620 goto done;
1621 }
1623 status = 0;
1625 power = musb_readb(mregs, MUSB_POWER);
1626 power |= MUSB_POWER_RESUME;
1627 musb_writeb(mregs, MUSB_POWER, power);
1628 dev_dbg(musb->controller, "issue wakeup\n");
1630 /* FIXME do this next chunk in a timer callback, no udelay */
1631 mdelay(2);
1633 power = musb_readb(mregs, MUSB_POWER);
1634 power &= ~MUSB_POWER_RESUME;
1635 musb_writeb(mregs, MUSB_POWER, power);
1636 done:
1637 spin_unlock_irqrestore(&musb->lock, flags);
1638 return status;
1639 }
1641 static int
1642 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1643 {
1644 struct musb *musb = gadget_to_musb(gadget);
1646 musb->is_self_powered = !!is_selfpowered;
1647 return 0;
1648 }
1650 static void musb_pullup(struct musb *musb, int is_on)
1651 {
1652 u8 power;
1654 power = musb_readb(musb->mregs, MUSB_POWER);
1655 if (is_on)
1656 power |= MUSB_POWER_SOFTCONN;
1657 else
1658 power &= ~MUSB_POWER_SOFTCONN;
1660 /* FIXME if on, HdrcStart; if off, HdrcStop */
1662 dev_dbg(musb->controller, "gadget D+ pullup %s\n",
1663 is_on ? "on" : "off");
1664 musb_writeb(musb->mregs, MUSB_POWER, power);
1665 }
1667 #if 0
1668 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1669 {
1670 dev_dbg(musb->controller, "<= %s =>\n", __func__);
1672 /*
1673 * FIXME iff driver's softconnect flag is set (as it is during probe,
1674 * though that can clear it), just musb_pullup().
1675 */
1677 return -EINVAL;
1678 }
1679 #endif
1681 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1682 {
1683 struct musb *musb = gadget_to_musb(gadget);
1685 if (!musb->xceiv->set_power)
1686 return -EOPNOTSUPP;
1687 return otg_set_power(musb->xceiv, mA);
1688 }
1690 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1691 {
1692 struct musb *musb = gadget_to_musb(gadget);
1693 unsigned long flags;
1695 is_on = !!is_on;
1697 pm_runtime_get_sync(musb->controller);
1699 /* NOTE: this assumes we are sensing vbus; we'd rather
1700 * not pullup unless the B-session is active.
1701 */
1702 spin_lock_irqsave(&musb->lock, flags);
1703 if (is_on != musb->softconnect) {
1704 musb->softconnect = is_on;
1705 musb_pullup(musb, is_on);
1706 }
1707 spin_unlock_irqrestore(&musb->lock, flags);
1709 pm_runtime_put(musb->controller);
1711 return 0;
1712 }
1714 static int musb_gadget_start(struct usb_gadget *g,
1715 struct usb_gadget_driver *driver);
1716 static int musb_gadget_stop(struct usb_gadget *g,
1717 struct usb_gadget_driver *driver);
1719 static const struct usb_gadget_ops musb_gadget_operations = {
1720 .get_frame = musb_gadget_get_frame,
1721 .wakeup = musb_gadget_wakeup,
1722 .set_selfpowered = musb_gadget_set_self_powered,
1723 /* .vbus_session = musb_gadget_vbus_session, */
1724 .vbus_draw = musb_gadget_vbus_draw,
1725 .pullup = musb_gadget_pullup,
1726 .udc_start = musb_gadget_start,
1727 .udc_stop = musb_gadget_stop,
1728 };
1730 /* ----------------------------------------------------------------------- */
1732 /* Registration */
1734 /* Only this registration code "knows" the rule (from USB standards)
1735 * about there being only one external upstream port. It assumes
1736 * all peripheral ports are external...
1737 */
1739 static void musb_gadget_release(struct device *dev)
1740 {
1741 /* kref_put(WHAT) */
1742 dev_dbg(dev, "%s\n", __func__);
1743 }
1746 static void __devinit
1747 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1748 {
1749 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1751 memset(ep, 0, sizeof *ep);
1753 ep->current_epnum = epnum;
1754 ep->musb = musb;
1755 ep->hw_ep = hw_ep;
1756 ep->is_in = is_in;
1758 INIT_LIST_HEAD(&ep->req_list);
1760 sprintf(ep->name, "ep%d%s", epnum,
1761 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1762 is_in ? "in" : "out"));
1763 ep->end_point.name = ep->name;
1764 INIT_LIST_HEAD(&ep->end_point.ep_list);
1765 if (!epnum) {
1766 ep->end_point.maxpacket = 64;
1767 ep->end_point.ops = &musb_g_ep0_ops;
1768 musb->g.ep0 = &ep->end_point;
1769 } else {
1770 if (is_in)
1771 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1772 else
1773 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1774 ep->end_point.ops = &musb_ep_ops;
1775 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1776 }
1777 }
1779 /*
1780 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1781 * to the rest of the driver state.
1782 */
1783 static inline void __devinit musb_g_init_endpoints(struct musb *musb)
1784 {
1785 u8 epnum;
1786 struct musb_hw_ep *hw_ep;
1787 unsigned count = 0;
1789 /* initialize endpoint list just once */
1790 INIT_LIST_HEAD(&(musb->g.ep_list));
1792 for (epnum = 0, hw_ep = musb->endpoints;
1793 epnum < musb->nr_endpoints;
1794 epnum++, hw_ep++) {
1795 if (hw_ep->is_shared_fifo /* || !epnum */) {
1796 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1797 count++;
1798 } else {
1799 if (hw_ep->max_packet_sz_tx) {
1800 init_peripheral_ep(musb, &hw_ep->ep_in,
1801 epnum, 1);
1802 count++;
1803 }
1804 if (hw_ep->max_packet_sz_rx) {
1805 init_peripheral_ep(musb, &hw_ep->ep_out,
1806 epnum, 0);
1807 count++;
1808 }
1809 }
1810 }
1811 }
1813 /* called once during driver setup to initialize and link into
1814 * the driver model; memory is zeroed.
1815 */
1816 int __devinit musb_gadget_setup(struct musb *musb)
1817 {
1818 int status;
1820 /* REVISIT minor race: if (erroneously) setting up two
1821 * musb peripherals at the same time, only the bus lock
1822 * is probably held.
1823 */
1825 musb->g.ops = &musb_gadget_operations;
1826 musb->g.max_speed = USB_SPEED_HIGH;
1827 musb->g.speed = USB_SPEED_UNKNOWN;
1829 /* this "gadget" abstracts/virtualizes the controller */
1830 dev_set_name(&musb->g.dev, "gadget");
1831 musb->g.dev.parent = musb->controller;
1832 musb->g.dev.dma_mask = musb->controller->dma_mask;
1833 musb->g.dev.release = musb_gadget_release;
1834 musb->g.name = musb_driver_name;
1836 if (is_otg_enabled(musb))
1837 musb->g.is_otg = 1;
1839 musb_g_init_endpoints(musb);
1841 musb->is_active = 0;
1842 musb_platform_try_idle(musb, 0);
1844 status = device_register(&musb->g.dev);
1845 if (status != 0) {
1846 put_device(&musb->g.dev);
1847 return status;
1848 }
1849 status = usb_add_gadget_udc(musb->controller, &musb->g);
1850 if (status)
1851 goto err;
1853 return 0;
1854 err:
1855 musb->g.dev.parent = NULL;
1856 device_unregister(&musb->g.dev);
1857 return status;
1858 }
1860 void musb_gadget_cleanup(struct musb *musb)
1861 {
1862 usb_del_gadget_udc(&musb->g);
1863 if (musb->g.dev.parent)
1864 device_unregister(&musb->g.dev);
1865 }
1867 /*
1868 * Register the gadget driver. Used by gadget drivers when
1869 * registering themselves with the controller.
1870 *
1871 * -EINVAL something went wrong (not driver)
1872 * -EBUSY another gadget is already using the controller
1873 * -ENOMEM no memory to perform the operation
1874 *
1875 * @param driver the gadget driver
1876 * @return <0 if error, 0 if everything is fine
1877 */
1878 static int musb_gadget_start(struct usb_gadget *g,
1879 struct usb_gadget_driver *driver)
1880 {
1881 struct musb *musb = gadget_to_musb(g);
1882 unsigned long flags;
1883 int retval = -EINVAL;
1885 if (driver->max_speed < USB_SPEED_HIGH)
1886 goto err0;
1888 pm_runtime_get_sync(musb->controller);
1890 dev_dbg(musb->controller, "registering driver %s\n", driver->function);
1892 musb->softconnect = 0;
1893 musb->gadget_driver = driver;
1895 spin_lock_irqsave(&musb->lock, flags);
1896 musb->is_active = 1;
1898 otg_set_peripheral(musb->xceiv, &musb->g);
1899 musb->xceiv->state = OTG_STATE_B_IDLE;
1901 /*
1902 * FIXME this ignores the softconnect flag. Drivers are
1903 * allowed hold the peripheral inactive until for example
1904 * userspace hooks up printer hardware or DSP codecs, so
1905 * hosts only see fully functional devices.
1906 */
1908 if (!is_otg_enabled(musb))
1909 musb_start(musb);
1911 spin_unlock_irqrestore(&musb->lock, flags);
1913 if (is_otg_enabled(musb)) {
1914 struct usb_hcd *hcd = musb_to_hcd(musb);
1916 dev_dbg(musb->controller, "OTG startup...\n");
1918 /* REVISIT: funcall to other code, which also
1919 * handles power budgeting ... this way also
1920 * ensures HdrcStart is indirectly called.
1921 */
1922 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1923 if (retval < 0) {
1924 dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
1925 goto err2;
1926 }
1928 if ((musb->xceiv->last_event == USB_EVENT_ID)
1929 && musb->xceiv->set_vbus)
1930 otg_set_vbus(musb->xceiv, 1);
1932 hcd->self.uses_pio_for_control = 1;
1933 }
1934 if (musb->xceiv->last_event == USB_EVENT_NONE)
1935 pm_runtime_put(musb->controller);
1937 return 0;
1939 err2:
1940 if (!is_otg_enabled(musb))
1941 musb_stop(musb);
1942 err0:
1943 return retval;
1944 }
1946 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1947 {
1948 int i;
1949 struct musb_hw_ep *hw_ep;
1951 /* don't disconnect if it's not connected */
1952 if (musb->g.speed == USB_SPEED_UNKNOWN)
1953 driver = NULL;
1954 else
1955 musb->g.speed = USB_SPEED_UNKNOWN;
1957 /* deactivate the hardware */
1958 if (musb->softconnect) {
1959 musb->softconnect = 0;
1960 musb_pullup(musb, 0);
1961 }
1962 musb_stop(musb);
1964 /* killing any outstanding requests will quiesce the driver;
1965 * then report disconnect
1966 */
1967 if (driver) {
1968 for (i = 0, hw_ep = musb->endpoints;
1969 i < musb->nr_endpoints;
1970 i++, hw_ep++) {
1971 musb_ep_select(musb, musb->mregs, i);
1972 if (hw_ep->is_shared_fifo /* || !epnum */) {
1973 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1974 } else {
1975 if (hw_ep->max_packet_sz_tx)
1976 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1977 if (hw_ep->max_packet_sz_rx)
1978 nuke(&hw_ep->ep_out, -ESHUTDOWN);
1979 }
1980 }
1981 }
1982 }
1984 /*
1985 * Unregister the gadget driver. Used by gadget drivers when
1986 * unregistering themselves from the controller.
1987 *
1988 * @param driver the gadget driver to unregister
1989 */
1990 static int musb_gadget_stop(struct usb_gadget *g,
1991 struct usb_gadget_driver *driver)
1992 {
1993 struct musb *musb = gadget_to_musb(g);
1994 unsigned long flags;
1996 if (musb->xceiv->last_event == USB_EVENT_NONE)
1997 pm_runtime_get_sync(musb->controller);
1999 /*
2000 * REVISIT always use otg_set_peripheral() here too;
2001 * this needs to shut down the OTG engine.
2002 */
2004 spin_lock_irqsave(&musb->lock, flags);
2006 musb_hnp_stop(musb);
2008 (void) musb_gadget_vbus_draw(&musb->g, 0);
2010 musb->xceiv->state = OTG_STATE_UNDEFINED;
2011 stop_activity(musb, driver);
2012 otg_set_peripheral(musb->xceiv, NULL);
2014 dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
2016 musb->is_active = 0;
2017 musb_platform_try_idle(musb, 0);
2018 spin_unlock_irqrestore(&musb->lock, flags);
2020 if (is_otg_enabled(musb)) {
2021 usb_remove_hcd(musb_to_hcd(musb));
2022 /* FIXME we need to be able to register another
2023 * gadget driver here and have everything work;
2024 * that currently misbehaves.
2025 */
2026 }
2028 if (!is_otg_enabled(musb))
2029 musb_stop(musb);
2031 pm_runtime_put(musb->controller);
2033 return 0;
2034 }
2036 /* ----------------------------------------------------------------------- */
2038 /* lifecycle operations called through plat_uds.c */
2040 void musb_g_resume(struct musb *musb)
2041 {
2042 musb->is_suspended = 0;
2043 switch (musb->xceiv->state) {
2044 case OTG_STATE_B_IDLE:
2045 break;
2046 case OTG_STATE_B_WAIT_ACON:
2047 case OTG_STATE_B_PERIPHERAL:
2048 musb->is_active = 1;
2049 if (musb->gadget_driver && musb->gadget_driver->resume) {
2050 spin_unlock(&musb->lock);
2051 musb->gadget_driver->resume(&musb->g);
2052 spin_lock(&musb->lock);
2053 }
2054 break;
2055 default:
2056 WARNING("unhandled RESUME transition (%s)\n",
2057 otg_state_string(musb->xceiv->state));
2058 }
2059 }
2061 /* called when SOF packets stop for 3+ msec */
2062 void musb_g_suspend(struct musb *musb)
2063 {
2064 u8 devctl;
2066 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2067 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2069 switch (musb->xceiv->state) {
2070 case OTG_STATE_B_IDLE:
2071 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2072 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2073 break;
2074 case OTG_STATE_B_PERIPHERAL:
2075 musb->is_suspended = 1;
2076 if (musb->gadget_driver && musb->gadget_driver->suspend) {
2077 spin_unlock(&musb->lock);
2078 musb->gadget_driver->suspend(&musb->g);
2079 spin_lock(&musb->lock);
2080 }
2081 break;
2082 default:
2083 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
2084 * A_PERIPHERAL may need care too
2085 */
2086 WARNING("unhandled SUSPEND transition (%s)\n",
2087 otg_state_string(musb->xceiv->state));
2088 }
2089 }
2091 /* Called during SRP */
2092 void musb_g_wakeup(struct musb *musb)
2093 {
2094 musb_gadget_wakeup(&musb->g);
2095 }
2097 /* called when VBUS drops below session threshold, and in other cases */
2098 void musb_g_disconnect(struct musb *musb)
2099 {
2100 void __iomem *mregs = musb->mregs;
2101 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
2103 dev_dbg(musb->controller, "devctl %02x\n", devctl);
2105 /* clear HR */
2106 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
2108 /* don't draw vbus until new b-default session */
2109 (void) musb_gadget_vbus_draw(&musb->g, 0);
2111 musb->g.speed = USB_SPEED_UNKNOWN;
2112 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
2113 spin_unlock(&musb->lock);
2114 musb->gadget_driver->disconnect(&musb->g);
2115 spin_lock(&musb->lock);
2116 }
2118 switch (musb->xceiv->state) {
2119 default:
2120 dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
2121 otg_state_string(musb->xceiv->state));
2122 musb->xceiv->state = OTG_STATE_A_IDLE;
2123 break;
2124 case OTG_STATE_A_PERIPHERAL:
2125 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
2126 break;
2127 case OTG_STATE_B_WAIT_ACON:
2128 case OTG_STATE_B_HOST:
2129 case OTG_STATE_B_PERIPHERAL:
2130 case OTG_STATE_B_IDLE:
2131 musb->xceiv->state = OTG_STATE_B_IDLE;
2132 break;
2133 case OTG_STATE_B_SRP_INIT:
2134 break;
2135 }
2137 musb->is_active = 0;
2138 }
2140 void musb_g_reset(struct musb *musb)
2141 __releases(musb->lock)
2142 __acquires(musb->lock)
2143 {
2144 void __iomem *mbase = musb->mregs;
2145 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
2146 u8 power;
2148 dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n",
2149 (devctl & MUSB_DEVCTL_BDEVICE)
2150 ? "B-Device" : "A-Device",
2151 musb_readb(mbase, MUSB_FADDR),
2152 musb->gadget_driver
2153 ? musb->gadget_driver->driver.name
2154 : NULL
2155 );
2157 /* report disconnect, if we didn't already (flushing EP state) */
2158 if (musb->g.speed != USB_SPEED_UNKNOWN)
2159 musb_g_disconnect(musb);
2161 /* clear HR */
2162 else if (devctl & MUSB_DEVCTL_HR)
2163 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2166 /* what speed did we negotiate? */
2167 power = musb_readb(mbase, MUSB_POWER);
2168 musb->g.speed = (power & MUSB_POWER_HSMODE)
2169 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2171 /* start in USB_STATE_DEFAULT */
2172 musb->is_active = 1;
2173 musb->is_suspended = 0;
2174 MUSB_DEV_MODE(musb);
2175 musb->address = 0;
2176 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2178 musb->may_wakeup = 0;
2179 musb->g.b_hnp_enable = 0;
2180 musb->g.a_alt_hnp_support = 0;
2181 musb->g.a_hnp_support = 0;
2183 /* Normal reset, as B-Device;
2184 * or else after HNP, as A-Device
2185 */
2186 if (devctl & MUSB_DEVCTL_BDEVICE) {
2187 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2188 musb->g.is_a_peripheral = 0;
2189 } else if (is_otg_enabled(musb)) {
2190 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2191 musb->g.is_a_peripheral = 1;
2192 } else
2193 WARN_ON(1);
2195 /* start with default limits on VBUS power draw */
2196 (void) musb_gadget_vbus_draw(&musb->g,
2197 is_otg_enabled(musb) ? 8 : 100);
2198 }