592e1904ceb0de27476a7b0e519741a90c5d52b7
1 /*
2 * MUSB OTG driver host support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/errno.h>
42 #include <linux/init.h>
43 #include <linux/list.h>
44 #include <linux/dma-mapping.h>
46 #include "musb_core.h"
47 #include "musb_host.h"
50 /* MUSB HOST status 22-mar-2006
51 *
52 * - There's still lots of partial code duplication for fault paths, so
53 * they aren't handled as consistently as they need to be.
54 *
55 * - PIO mostly behaved when last tested.
56 * + including ep0, with all usbtest cases 9, 10
57 * + usbtest 14 (ep0out) doesn't seem to run at all
58 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
59 * configurations, but otherwise double buffering passes basic tests.
60 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
61 *
62 * - DMA (CPPI) ... partially behaves, not currently recommended
63 * + about 1/15 the speed of typical EHCI implementations (PCI)
64 * + RX, all too often reqpkt seems to misbehave after tx
65 * + TX, no known issues (other than evident silicon issue)
66 *
67 * - DMA (Mentor/OMAP) ...has at least toggle update problems
68 *
69 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
70 * starvation ... nothing yet for TX, interrupt, or bulk.
71 *
72 * - Not tested with HNP, but some SRP paths seem to behave.
73 *
74 * NOTE 24-August-2006:
75 *
76 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
77 * extra endpoint for periodic use enabling hub + keybd + mouse. That
78 * mostly works, except that with "usbnet" it's easy to trigger cases
79 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
80 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
81 * although ARP RX wins. (That test was done with a full speed link.)
82 */
85 /*
86 * NOTE on endpoint usage:
87 *
88 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
89 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
90 * (Yes, bulk _could_ use more of the endpoints than that, and would even
91 * benefit from it.)
92 *
93 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
94 * So far that scheduling is both dumb and optimistic: the endpoint will be
95 * "claimed" until its software queue is no longer refilled. No multiplexing
96 * of transfers between endpoints, or anything clever.
97 */
100 static void musb_ep_program(struct musb *musb, u8 epnum,
101 struct urb *urb, int is_out,
102 u8 *buf, u32 offset, u32 len);
104 void push_queue(struct musb *musb, struct urb *urb)
105 {
106 spin_lock(&musb->gb_lock);
107 list_add_tail(&urb->giveback_list, &musb->gb_list);
108 spin_unlock(&musb->gb_lock);
109 }
111 struct urb *pop_queue(struct musb *musb)
112 {
113 struct urb *urb;
114 unsigned long flags;
116 spin_lock_irqsave(&musb->gb_lock, flags);
117 if (list_empty(&musb->gb_list)) {
118 spin_unlock_irqrestore(&musb->gb_lock, flags);
119 return NULL;
120 }
121 urb = list_entry(musb->gb_list.next, struct urb, giveback_list);
122 list_del(&urb->giveback_list);
123 spin_unlock_irqrestore(&musb->gb_lock, flags);
125 return urb;
126 }
128 /*
129 * Clear TX fifo. Needed to avoid BABBLE errors.
130 */
131 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
132 {
133 struct musb *musb = ep->musb;
134 void __iomem *epio = ep->regs;
135 u16 csr;
136 u16 lastcsr = 0;
137 int retries = 1000;
139 csr = musb_readw(epio, MUSB_TXCSR);
140 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
141 if (csr != lastcsr)
142 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
143 lastcsr = csr;
144 csr |= MUSB_TXCSR_FLUSHFIFO;
145 musb_writew(epio, MUSB_TXCSR, csr);
146 csr = musb_readw(epio, MUSB_TXCSR);
147 if (WARN(retries-- < 1,
148 "Could not flush host TX%d fifo: csr: %04x\n",
149 ep->epnum, csr))
150 return;
151 mdelay(1);
152 }
153 }
155 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
156 {
157 void __iomem *epio = ep->regs;
158 u16 csr;
159 int retries = 5;
161 /* scrub any data left in the fifo */
162 do {
163 csr = musb_readw(epio, MUSB_TXCSR);
164 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
165 break;
166 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
167 csr = musb_readw(epio, MUSB_TXCSR);
168 udelay(10);
169 } while (--retries);
171 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
172 ep->epnum, csr);
174 /* and reset for the next transfer */
175 musb_writew(epio, MUSB_TXCSR, 0);
176 }
178 /*
179 * Start transmit. Caller is responsible for locking shared resources.
180 * musb must be locked.
181 */
182 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
183 {
184 u16 txcsr;
186 /* NOTE: no locks here; caller should lock and select EP */
187 if (ep->epnum) {
188 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
189 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
190 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
191 } else {
192 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
193 musb_writew(ep->regs, MUSB_CSR0, txcsr);
194 }
196 }
198 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
199 {
200 u16 txcsr;
202 /* NOTE: no locks here; caller should lock and select EP */
203 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
204 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
205 if (is_cppi_enabled(ep->musb))
206 txcsr |= MUSB_TXCSR_DMAMODE;
207 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
208 }
210 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
211 {
212 if (is_in != 0 || ep->is_shared_fifo)
213 ep->in_qh = qh;
214 if (is_in == 0 || ep->is_shared_fifo)
215 ep->out_qh = qh;
216 }
218 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
219 {
220 return is_in ? ep->in_qh : ep->out_qh;
221 }
223 /*
224 * Start the URB at the front of an endpoint's queue
225 * end must be claimed from the caller.
226 *
227 * Context: controller locked, irqs blocked
228 */
229 static void
230 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
231 {
232 u16 frame;
233 u32 len;
234 void __iomem *mbase = musb->mregs;
235 struct urb *urb = next_urb(qh);
236 void *buf = urb->transfer_buffer;
237 u32 offset = 0;
238 struct musb_hw_ep *hw_ep = qh->hw_ep;
239 unsigned pipe = urb->pipe;
240 u8 address = usb_pipedevice(pipe);
241 int epnum = hw_ep->epnum;
243 /* initialize software qh state */
244 qh->offset = 0;
245 qh->segsize = 0;
247 /* gather right source of data */
248 switch (qh->type) {
249 case USB_ENDPOINT_XFER_CONTROL:
250 /* control transfers always start with SETUP */
251 is_in = 0;
252 musb->ep0_stage = MUSB_EP0_START;
253 buf = urb->setup_packet;
254 len = 8;
255 break;
256 case USB_ENDPOINT_XFER_ISOC:
257 qh->iso_idx = 0;
258 qh->frame = 0;
259 offset = urb->iso_frame_desc[0].offset;
260 len = urb->iso_frame_desc[0].length;
261 break;
262 default: /* bulk, interrupt */
263 /* actual_length may be nonzero on retry paths */
264 buf = urb->transfer_buffer + urb->actual_length;
265 len = urb->transfer_buffer_length - urb->actual_length;
266 }
268 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
269 qh, urb, address, qh->epnum,
270 is_in ? "in" : "out",
271 ({char *s; switch (qh->type) {
272 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
273 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
274 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
275 default: s = "-intr"; break;
276 }; s; }),
277 epnum, buf + offset, len);
279 /* Configure endpoint */
280 musb_ep_set_qh(hw_ep, is_in, qh);
281 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
283 /* transmit may have more work: start it when it is time */
284 if (is_in)
285 return;
287 /* determine if the time is right for a periodic transfer */
288 switch (qh->type) {
289 case USB_ENDPOINT_XFER_ISOC:
290 case USB_ENDPOINT_XFER_INT:
291 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
292 frame = musb_readw(mbase, MUSB_FRAME);
293 /* FIXME this doesn't implement that scheduling policy ...
294 * or handle framecounter wrapping
295 */
296 if ((urb->transfer_flags & URB_ISO_ASAP)
297 || (frame >= urb->start_frame)) {
298 /* REVISIT the SOF irq handler shouldn't duplicate
299 * this code; and we don't init urb->start_frame...
300 */
301 qh->frame = 0;
302 goto start;
303 } else {
304 qh->frame = urb->start_frame;
305 /* enable SOF interrupt so we can count down */
306 dev_dbg(musb->controller, "SOF for %d\n", epnum);
307 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
308 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
309 #endif
310 }
311 break;
312 default:
313 start:
314 dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
315 hw_ep->tx_channel ? "dma" : "pio");
317 if (!hw_ep->tx_channel)
318 musb_h_tx_start(hw_ep);
319 else if (is_cppi_enabled(musb) || tusb_dma_omap(musb))
320 musb_h_tx_dma_start(hw_ep);
321 }
322 }
324 /* Context: caller owns controller lock, IRQs are blocked */
325 static void musb_giveback(struct musb *musb, struct urb *urb, int status)
326 {
327 dev_dbg(musb->controller,
328 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
329 urb, urb->complete, status,
330 usb_pipedevice(urb->pipe),
331 usb_pipeendpoint(urb->pipe),
332 usb_pipein(urb->pipe) ? "in" : "out",
333 urb->actual_length, urb->transfer_buffer_length
334 );
336 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
337 }
339 /* For bulk/interrupt endpoints only */
340 static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
341 struct urb *urb)
342 {
343 void __iomem *epio = qh->hw_ep->regs;
344 u16 csr;
346 /*
347 * FIXME: the current Mentor DMA code seems to have
348 * problems getting toggle correct.
349 */
351 if (is_in)
352 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
353 else
354 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
356 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
357 }
358 /* Used to complete urb giveback */
359 void musb_gb_work(struct work_struct *data)
360 {
361 struct musb *musb = container_of(data, struct musb, gb_work);
362 struct urb *urb;
364 while ((urb = pop_queue(musb)) != 0)
365 musb_giveback(musb, urb, 0);
366 }
368 /*
369 * Advance this hardware endpoint's queue, completing the specified URB and
370 * advancing to either the next URB queued to that qh, or else invalidating
371 * that qh and advancing to the next qh scheduled after the current one.
372 *
373 * Context: caller owns controller lock, IRQs are blocked
374 */
375 static void musb_advance_schedule(struct musb *musb, struct urb *urb,
376 struct musb_hw_ep *hw_ep, int is_in)
377 {
378 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
379 struct musb_hw_ep *ep = qh->hw_ep;
380 int ready = qh->is_ready;
381 int status;
383 status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
385 /* save toggle eagerly, for paranoia */
386 switch (qh->type) {
387 case USB_ENDPOINT_XFER_BULK:
388 case USB_ENDPOINT_XFER_INT:
389 musb_save_toggle(qh, is_in, urb);
390 break;
391 case USB_ENDPOINT_XFER_ISOC:
392 if (status == 0 && urb->error_count)
393 status = -EXDEV;
394 break;
395 }
397 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
399 /* If URB completed with error then giveback first */
400 if (status != 0) {
401 qh->is_ready = 0;
402 spin_unlock(&musb->lock);
403 musb_giveback(musb, urb, status);
404 spin_lock(&musb->lock);
405 qh->is_ready = ready;
406 }
407 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
408 * invalidate qh as soon as list_empty(&hep->urb_list)
409 */
410 if (list_empty(&qh->hep->urb_list)) {
411 struct list_head *head;
413 if (is_in)
414 ep->rx_reinit = 1;
415 else
416 ep->tx_reinit = 1;
418 /* Clobber old pointers to this qh */
419 musb_ep_set_qh(ep, is_in, NULL);
420 qh->hep->hcpriv = NULL;
422 switch (qh->type) {
424 case USB_ENDPOINT_XFER_CONTROL:
425 case USB_ENDPOINT_XFER_BULK:
426 /* fifo policy for these lists, except that NAKing
427 * should rotate a qh to the end (for fairness).
428 */
429 if (qh->mux == 1) {
430 head = qh->ring.prev;
431 list_del(&qh->ring);
432 kfree(qh);
433 qh = first_qh(head);
434 break;
435 }
437 case USB_ENDPOINT_XFER_ISOC:
438 case USB_ENDPOINT_XFER_INT:
439 /* this is where periodic bandwidth should be
440 * de-allocated if it's tracked and allocated;
441 * and where we'd update the schedule tree...
442 */
443 kfree(qh);
444 qh = NULL;
445 break;
446 }
447 }
449 if (qh != NULL && qh->is_ready) {
450 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
451 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
452 musb_start_urb(musb, is_in, qh);
453 }
455 /* if URB is successfully completed then giveback in workqueue */
456 if (status == 0) {
457 push_queue(musb, urb);
458 queue_work(musb->gb_queue, &musb->gb_work);
459 }
460 }
462 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
463 {
464 /* we don't want fifo to fill itself again;
465 * ignore dma (various models),
466 * leave toggle alone (may not have been saved yet)
467 */
468 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
469 csr &= ~(MUSB_RXCSR_H_REQPKT
470 | MUSB_RXCSR_H_AUTOREQ
471 | MUSB_RXCSR_AUTOCLEAR);
473 /* write 2x to allow double buffering */
474 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
475 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
477 /* flush writebuffer */
478 return musb_readw(hw_ep->regs, MUSB_RXCSR);
479 }
481 /*
482 * PIO RX for a packet (or part of it).
483 */
484 static bool
485 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
486 {
487 u16 rx_count;
488 u8 *buf;
489 u16 csr;
490 bool done = false;
491 u32 length;
492 int do_flush = 0;
493 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
494 void __iomem *epio = hw_ep->regs;
495 struct musb_qh *qh = hw_ep->in_qh;
496 int pipe = urb->pipe;
497 void *buffer = urb->transfer_buffer;
499 /* musb_ep_select(musb, mbase, epnum); */
500 rx_count = musb_readw(epio, MUSB_RXCOUNT);
501 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
502 urb->transfer_buffer, qh->offset,
503 urb->transfer_buffer_length);
505 /* unload FIFO */
506 if (usb_pipeisoc(pipe)) {
507 int status = 0;
508 struct usb_iso_packet_descriptor *d;
510 if (iso_err) {
511 status = -EILSEQ;
512 urb->error_count++;
513 }
515 d = urb->iso_frame_desc + qh->iso_idx;
516 buf = buffer + d->offset;
517 length = d->length;
518 if (rx_count > length) {
519 if (status == 0) {
520 status = -EOVERFLOW;
521 urb->error_count++;
522 }
523 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
524 do_flush = 1;
525 } else
526 length = rx_count;
527 urb->actual_length += length;
528 d->actual_length = length;
530 d->status = status;
532 /* see if we are done */
533 done = (++qh->iso_idx >= urb->number_of_packets);
534 } else {
535 /* non-isoch */
536 buf = buffer + qh->offset;
537 length = urb->transfer_buffer_length - qh->offset;
538 if (rx_count > length) {
539 if (urb->status == -EINPROGRESS)
540 urb->status = -EOVERFLOW;
541 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
542 do_flush = 1;
543 } else
544 length = rx_count;
545 urb->actual_length += length;
546 qh->offset += length;
548 /* see if we are done */
549 done = (urb->actual_length == urb->transfer_buffer_length)
550 || (rx_count < qh->maxpacket)
551 || (urb->status != -EINPROGRESS);
552 if (done
553 && (urb->status == -EINPROGRESS)
554 && (urb->transfer_flags & URB_SHORT_NOT_OK)
555 && (urb->actual_length
556 < urb->transfer_buffer_length))
557 urb->status = -EREMOTEIO;
558 }
560 musb->ops->read_fifo(hw_ep, length, buf);
562 csr = musb_readw(epio, MUSB_RXCSR);
563 csr |= MUSB_RXCSR_H_WZC_BITS;
564 if (unlikely(do_flush))
565 musb_h_flush_rxfifo(hw_ep, csr);
566 else {
567 /* REVISIT this assumes AUTOCLEAR is never set */
568 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
569 if (!done)
570 csr |= MUSB_RXCSR_H_REQPKT;
571 musb_writew(epio, MUSB_RXCSR, csr);
572 }
574 return done;
575 }
577 /* we don't always need to reinit a given side of an endpoint...
578 * when we do, use tx/rx reinit routine and then construct a new CSR
579 * to address data toggle, NYET, and DMA or PIO.
580 *
581 * it's possible that driver bugs (especially for DMA) or aborting a
582 * transfer might have left the endpoint busier than it should be.
583 * the busy/not-empty tests are basically paranoia.
584 */
585 static void
586 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
587 {
588 u16 csr;
590 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
591 * That always uses tx_reinit since ep0 repurposes TX register
592 * offsets; the initial SETUP packet is also a kind of OUT.
593 */
595 /* if programmed for Tx, put it in RX mode */
596 if (ep->is_shared_fifo) {
597 csr = musb_readw(ep->regs, MUSB_TXCSR);
598 if (csr & MUSB_TXCSR_MODE) {
599 musb_h_tx_flush_fifo(ep);
600 csr = musb_readw(ep->regs, MUSB_TXCSR);
601 musb_writew(ep->regs, MUSB_TXCSR,
602 csr | MUSB_TXCSR_FRCDATATOG);
603 }
605 /*
606 * Clear the MODE bit (and everything else) to enable Rx.
607 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
608 */
609 if (csr & MUSB_TXCSR_DMAMODE)
610 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
611 musb_writew(ep->regs, MUSB_TXCSR, 0);
613 /* scrub all previous state, clearing toggle */
614 } else {
615 csr = musb_readw(ep->regs, MUSB_RXCSR);
616 if (csr & MUSB_RXCSR_RXPKTRDY)
617 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
618 musb_readw(ep->regs, MUSB_RXCOUNT));
620 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
621 }
623 /* target addr and (for multipoint) hub addr/port */
624 if (musb->is_multipoint) {
625 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
626 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
627 musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
629 } else
630 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
632 /* protocol/endpoint, interval/NAKlimit, i/o size */
633 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
634 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
635 /* NOTE: bulk combining rewrites high bits of maxpacket */
636 /* Set RXMAXP with the FIFO size of the endpoint
637 * to disable double buffer mode.
638 */
639 if (musb->double_buffer_not_ok)
640 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
641 else
642 musb_writew(ep->regs, MUSB_RXMAXP,
643 qh->maxpacket | ((qh->hb_mult - 1) << 11));
645 ep->rx_reinit = 0;
646 }
648 static bool musb_tx_dma_program(struct dma_controller *dma,
649 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
650 struct urb *urb, u32 offset, u32 length)
651 {
652 struct dma_channel *channel = hw_ep->tx_channel;
653 void __iomem *epio = hw_ep->regs;
654 u16 pkt_size = qh->maxpacket;
655 u16 csr;
656 u8 mode;
658 if (is_inventra_dma(hw_ep->musb)) {
659 if (length > channel->max_len)
660 length = channel->max_len;
662 csr = musb_readw(epio, MUSB_TXCSR);
663 if (length > pkt_size) {
664 mode = 1;
665 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
666 /* autoset shouldn't be set in high bandwidth */
667 if (qh->hb_mult == 1)
668 csr |= MUSB_TXCSR_AUTOSET;
669 } else {
670 mode = 0;
671 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
672 csr |= MUSB_TXCSR_DMAENAB; /* against progrmr's guide */
673 }
674 channel->desired_mode = mode;
675 musb_writew(epio, MUSB_TXCSR, csr);
676 } else {
677 if (!is_cppi_enabled(hw_ep->musb) &&
678 !tusb_dma_omap(hw_ep->musb))
679 return false;
681 channel->actual_len = 0;
683 /*
684 * TX uses "RNDIS" mode automatically but needs help
685 * to identify the zero-length-final-packet case.
686 */
687 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
688 }
690 qh->segsize = length;
692 /*
693 * Ensure the data reaches to main memory before starting
694 * DMA transfer
695 */
696 wmb();
698 if (!dma->channel_program(channel, pkt_size, mode,
699 urb->transfer_dma + offset, length)) {
700 dma->channel_release(channel);
701 hw_ep->tx_channel = NULL;
703 csr = musb_readw(epio, MUSB_TXCSR);
704 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
705 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
706 return false;
707 }
708 return true;
709 }
711 /*
712 * Program an HDRC endpoint as per the given URB
713 * Context: irqs blocked, controller lock held
714 */
715 static void musb_ep_program(struct musb *musb, u8 epnum,
716 struct urb *urb, int is_out,
717 u8 *buf, u32 offset, u32 len)
718 {
719 struct dma_controller *dma_controller;
720 struct dma_channel *dma_channel;
721 u8 dma_ok;
722 void __iomem *mbase = musb->mregs;
723 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
724 void __iomem *epio = hw_ep->regs;
725 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
726 u16 packet_sz = qh->maxpacket;
728 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
729 "h_addr%02x h_port%02x bytes %d\n",
730 is_out ? "-->" : "<--",
731 epnum, urb, urb->dev->speed,
732 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
733 qh->h_addr_reg, qh->h_port_reg,
734 len);
736 musb_ep_select(musb, mbase, epnum);
738 /* candidate for DMA? */
739 dma_controller = musb->dma_controller;
740 if (is_dma_capable() && epnum && dma_controller) {
741 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
742 if (!dma_channel) {
743 dma_channel = dma_controller->channel_alloc(
744 dma_controller, hw_ep, is_out);
745 if (is_out)
746 hw_ep->tx_channel = dma_channel;
747 else
748 hw_ep->rx_channel = dma_channel;
749 }
750 } else
751 dma_channel = NULL;
753 /* make sure we clear DMAEnab, autoSet bits from previous run */
755 /* OUT/transmit/EP0 or IN/receive? */
756 if (is_out) {
757 u16 csr;
758 u16 int_txe;
759 u16 load_count;
761 csr = musb_readw(epio, MUSB_TXCSR);
763 /* disable interrupt in case we flush */
764 int_txe = musb_readw(mbase, MUSB_INTRTXE);
765 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
767 /* general endpoint setup */
768 if (epnum) {
769 /* flush all old state, set default */
770 musb_h_tx_flush_fifo(hw_ep);
772 /*
773 * We must not clear the DMAMODE bit before or in
774 * the same cycle with the DMAENAB bit, so we clear
775 * the latter first...
776 */
777 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
778 | MUSB_TXCSR_AUTOSET
779 | MUSB_TXCSR_DMAENAB
780 | MUSB_TXCSR_FRCDATATOG
781 | MUSB_TXCSR_H_RXSTALL
782 | MUSB_TXCSR_H_ERROR
783 | MUSB_TXCSR_TXPKTRDY
784 );
785 csr |= MUSB_TXCSR_MODE;
787 if (usb_gettoggle(urb->dev, qh->epnum, 1))
788 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
789 | MUSB_TXCSR_H_DATATOGGLE;
790 else
791 csr |= MUSB_TXCSR_CLRDATATOG;
793 musb_writew(epio, MUSB_TXCSR, csr);
794 /* REVISIT may need to clear FLUSHFIFO ... */
795 csr &= ~MUSB_TXCSR_DMAMODE;
796 musb_writew(epio, MUSB_TXCSR, csr);
797 csr = musb_readw(epio, MUSB_TXCSR);
798 } else {
799 /* endpoint 0: just flush */
800 musb_h_ep0_flush_fifo(hw_ep);
801 }
803 /* target addr and (for multipoint) hub addr/port */
804 if (musb->is_multipoint) {
805 musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
806 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
807 musb_write_txhubport(mbase, epnum, qh->h_port_reg);
808 /* FIXME if !epnum, do the same for RX ... */
809 } else
810 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
812 /* protocol/endpoint/interval/NAKlimit */
813 if (epnum) {
814 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
815 if (musb->double_buffer_not_ok)
816 musb_writew(epio, MUSB_TXMAXP,
817 hw_ep->max_packet_sz_tx);
818 else if (can_bulk_split(musb, qh->type))
819 musb_writew(epio, MUSB_TXMAXP, packet_sz
820 | ((hw_ep->max_packet_sz_tx /
821 packet_sz) - 1) << 11);
822 else
823 musb_writew(epio, MUSB_TXMAXP,
824 qh->maxpacket |
825 ((qh->hb_mult - 1) << 11));
826 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
827 } else {
828 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
829 if (musb->is_multipoint)
830 musb_writeb(epio, MUSB_TYPE0,
831 qh->type_reg);
832 }
834 if (can_bulk_split(musb, qh->type))
835 load_count = min((u32) hw_ep->max_packet_sz_tx,
836 len);
837 else
838 load_count = min((u32) packet_sz, len);
840 if (dma_channel && musb_tx_dma_program(dma_controller,
841 hw_ep, qh, urb, offset, len))
842 load_count = 0;
844 if (load_count) {
845 /* PIO to load FIFO */
846 qh->segsize = load_count;
847 musb->ops->write_fifo(hw_ep, load_count, buf);
848 }
850 /* re-enable interrupt */
851 musb_writew(mbase, MUSB_INTRTXE, int_txe);
853 /* IN/receive */
854 } else {
855 u16 csr;
857 if (hw_ep->rx_reinit) {
858 musb_rx_reinit(musb, qh, hw_ep);
860 /* init new state: toggle and NYET, maybe DMA later */
861 if (usb_gettoggle(urb->dev, qh->epnum, 0))
862 csr = MUSB_RXCSR_H_WR_DATATOGGLE
863 | MUSB_RXCSR_H_DATATOGGLE;
864 else
865 csr = 0;
866 if (qh->type == USB_ENDPOINT_XFER_INT)
867 csr |= MUSB_RXCSR_DISNYET;
869 } else {
870 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
872 if (csr & (MUSB_RXCSR_RXPKTRDY
873 | MUSB_RXCSR_DMAENAB
874 | MUSB_RXCSR_H_REQPKT))
875 ERR("broken !rx_reinit, ep%d csr %04x\n",
876 hw_ep->epnum, csr);
878 /* scrub any stale state, leaving toggle alone */
879 csr &= MUSB_RXCSR_DISNYET;
880 }
882 /* kick things off */
884 if ((is_cppi_enabled(musb) || tusb_dma_omap(musb))
885 && dma_channel) {
886 /* Candidate for DMA */
887 dma_channel->actual_len = 0L;
888 qh->segsize = len;
890 /* AUTOREQ is in a DMA register */
891 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
892 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
894 /*
895 * Unless caller treats short RX transfers as
896 * errors, we dare not queue multiple transfers.
897 */
898 dma_ok = dma_controller->channel_program(dma_channel,
899 packet_sz, !(urb->transfer_flags &
900 URB_SHORT_NOT_OK),
901 urb->transfer_dma + offset,
902 qh->segsize);
903 if (!dma_ok) {
904 dma_controller->channel_release(dma_channel);
905 hw_ep->rx_channel = dma_channel = NULL;
906 } else
907 csr |= MUSB_RXCSR_DMAENAB;
908 }
910 csr |= MUSB_RXCSR_H_REQPKT;
911 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
912 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
913 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
914 }
915 }
918 /*
919 * Service the default endpoint (ep0) as host.
920 * Return true until it's time to start the status stage.
921 */
922 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
923 {
924 bool more = false;
925 u8 *fifo_dest = NULL;
926 u16 fifo_count = 0;
927 struct musb_hw_ep *hw_ep = musb->control_ep;
928 struct musb_qh *qh = hw_ep->in_qh;
929 struct usb_ctrlrequest *request;
931 switch (musb->ep0_stage) {
932 case MUSB_EP0_IN:
933 fifo_dest = urb->transfer_buffer + urb->actual_length;
934 fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
935 urb->actual_length);
936 if (fifo_count < len)
937 urb->status = -EOVERFLOW;
939 musb->ops->read_fifo(hw_ep, fifo_count, fifo_dest);
941 urb->actual_length += fifo_count;
942 if (len < qh->maxpacket) {
943 /* always terminate on short read; it's
944 * rarely reported as an error.
945 */
946 } else if (urb->actual_length <
947 urb->transfer_buffer_length)
948 more = true;
949 break;
950 case MUSB_EP0_START:
951 request = (struct usb_ctrlrequest *) urb->setup_packet;
953 if (!request->wLength) {
954 dev_dbg(musb->controller, "start no-DATA\n");
955 break;
956 } else if (request->bRequestType & USB_DIR_IN) {
957 dev_dbg(musb->controller, "start IN-DATA\n");
958 musb->ep0_stage = MUSB_EP0_IN;
959 more = true;
960 break;
961 } else {
962 dev_dbg(musb->controller, "start OUT-DATA\n");
963 musb->ep0_stage = MUSB_EP0_OUT;
964 more = true;
965 }
966 /* FALLTHROUGH */
967 case MUSB_EP0_OUT:
968 fifo_count = min_t(size_t, qh->maxpacket,
969 urb->transfer_buffer_length -
970 urb->actual_length);
971 if (fifo_count) {
972 fifo_dest = (u8 *) (urb->transfer_buffer
973 + urb->actual_length);
974 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
975 fifo_count,
976 (fifo_count == 1) ? "" : "s",
977 fifo_dest);
978 musb->ops->write_fifo(hw_ep, fifo_count, fifo_dest);
980 urb->actual_length += fifo_count;
981 more = true;
982 }
983 break;
984 default:
985 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
986 break;
987 }
989 return more;
990 }
992 /*
993 * Handle default endpoint interrupt as host. Only called in IRQ time
994 * from musb_interrupt().
995 *
996 * called with controller irqlocked
997 */
998 irqreturn_t musb_h_ep0_irq(struct musb *musb)
999 {
1000 struct urb *urb;
1001 u16 csr, len;
1002 int status = 0;
1003 void __iomem *mbase = musb->mregs;
1004 struct musb_hw_ep *hw_ep = musb->control_ep;
1005 void __iomem *epio = hw_ep->regs;
1006 struct musb_qh *qh = hw_ep->in_qh;
1007 bool complete = false;
1008 irqreturn_t retval = IRQ_NONE;
1010 /* ep0 only has one queue, "in" */
1011 urb = next_urb(qh);
1013 musb_ep_select(musb, mbase, 0);
1014 csr = musb_readw(epio, MUSB_CSR0);
1015 len = (csr & MUSB_CSR0_RXPKTRDY)
1016 ? musb_readb(epio, MUSB_COUNT0)
1017 : 0;
1019 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
1020 csr, qh, len, urb, musb->ep0_stage);
1022 /* if we just did status stage, we are done */
1023 if (MUSB_EP0_STATUS == musb->ep0_stage) {
1024 retval = IRQ_HANDLED;
1025 complete = true;
1026 }
1028 /* prepare status */
1029 if (csr & MUSB_CSR0_H_RXSTALL) {
1030 dev_dbg(musb->controller, "STALLING ENDPOINT\n");
1031 status = -EPIPE;
1033 } else if (csr & MUSB_CSR0_H_ERROR) {
1034 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
1035 status = -EPROTO;
1037 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1038 dev_dbg(musb->controller, "control NAK timeout\n");
1040 /* NOTE: this code path would be a good place to PAUSE a
1041 * control transfer, if another one is queued, so that
1042 * ep0 is more likely to stay busy. That's already done
1043 * for bulk RX transfers.
1044 *
1045 * if (qh->ring.next != &musb->control), then
1046 * we have a candidate... NAKing is *NOT* an error
1047 */
1048 musb_writew(epio, MUSB_CSR0, 0);
1049 retval = IRQ_HANDLED;
1050 }
1052 if (status) {
1053 dev_dbg(musb->controller, "aborting\n");
1054 retval = IRQ_HANDLED;
1055 if (urb)
1056 urb->status = status;
1057 complete = true;
1059 /* use the proper sequence to abort the transfer */
1060 if (csr & MUSB_CSR0_H_REQPKT) {
1061 csr &= ~MUSB_CSR0_H_REQPKT;
1062 musb_writew(epio, MUSB_CSR0, csr);
1063 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1064 musb_writew(epio, MUSB_CSR0, csr);
1065 } else {
1066 musb_h_ep0_flush_fifo(hw_ep);
1067 }
1069 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1071 /* clear it */
1072 musb_writew(epio, MUSB_CSR0, 0);
1073 }
1075 if (unlikely(!urb)) {
1076 /* stop endpoint since we have no place for its data, this
1077 * SHOULD NEVER HAPPEN! */
1078 ERR("no URB for end 0\n");
1080 musb_h_ep0_flush_fifo(hw_ep);
1081 goto done;
1082 }
1084 if (!complete) {
1085 /* call common logic and prepare response */
1086 if (musb_h_ep0_continue(musb, len, urb)) {
1087 /* more packets required */
1088 csr = (MUSB_EP0_IN == musb->ep0_stage)
1089 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1090 } else {
1091 /* data transfer complete; perform status phase */
1092 if (usb_pipeout(urb->pipe)
1093 || !urb->transfer_buffer_length)
1094 csr = MUSB_CSR0_H_STATUSPKT
1095 | MUSB_CSR0_H_REQPKT;
1096 else
1097 csr = MUSB_CSR0_H_STATUSPKT
1098 | MUSB_CSR0_TXPKTRDY;
1099 /* disable ping token in status phase */
1100 csr |= MUSB_CSR0_H_DIS_PING;
1102 /* flag status stage */
1103 musb->ep0_stage = MUSB_EP0_STATUS;
1105 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
1107 }
1108 musb_writew(epio, MUSB_CSR0, csr);
1109 retval = IRQ_HANDLED;
1110 } else
1111 musb->ep0_stage = MUSB_EP0_IDLE;
1113 /* call completion handler if done */
1114 if (complete)
1115 musb_advance_schedule(musb, urb, hw_ep, 1);
1116 done:
1117 return retval;
1118 }
1121 /* Host side TX (OUT) using Mentor DMA works as follows:
1122 submit_urb ->
1123 - if queue was empty, Program Endpoint
1124 - ... which starts DMA to fifo in mode 1 or 0
1126 DMA Isr (transfer complete) -> TxAvail()
1127 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1128 only in musb_cleanup_urb)
1129 - TxPktRdy has to be set in mode 0 or for
1130 short packets in mode 1.
1131 */
1133 /* Service a Tx-Available or dma completion irq for the endpoint */
1134 void musb_host_tx(struct musb *musb, u8 epnum)
1135 {
1136 int pipe;
1137 bool done = false;
1138 u16 tx_csr;
1139 size_t length = 0;
1140 size_t offset = 0;
1141 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1142 void __iomem *epio = hw_ep->regs;
1143 struct musb_qh *qh = hw_ep->out_qh;
1144 struct urb *urb = next_urb(qh);
1145 u32 status = 0;
1146 void __iomem *mbase = musb->mregs;
1147 struct dma_channel *dma;
1148 bool transfer_pending = false;
1150 musb_ep_select(musb, mbase, epnum);
1151 tx_csr = musb_readw(epio, MUSB_TXCSR);
1153 /* with CPPI, DMA sometimes triggers "extra" irqs */
1154 if (!urb) {
1155 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1156 return;
1157 }
1159 pipe = urb->pipe;
1160 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1161 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1162 dma ? ", dma" : "");
1164 /* check for errors */
1165 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1166 /* dma was disabled, fifo flushed */
1167 dev_dbg(musb->controller, "TX end %d stall\n", epnum);
1169 /* stall; record URB status */
1170 status = -EPIPE;
1172 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1173 /* (NON-ISO) dma was disabled, fifo flushed */
1174 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
1176 status = -ETIMEDOUT;
1178 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1179 dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);
1181 /* NOTE: this code path would be a good place to PAUSE a
1182 * transfer, if there's some other (nonperiodic) tx urb
1183 * that could use this fifo. (dma complicates it...)
1184 * That's already done for bulk RX transfers.
1185 *
1186 * if (bulk && qh->ring.next != &musb->out_bulk), then
1187 * we have a candidate... NAKing is *NOT* an error
1188 */
1189 musb_ep_select(musb, mbase, epnum);
1190 musb_writew(epio, MUSB_TXCSR,
1191 MUSB_TXCSR_H_WZC_BITS
1192 | MUSB_TXCSR_TXPKTRDY);
1193 return;
1194 }
1196 if (status) {
1197 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1198 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1199 (void) musb->dma_controller->channel_abort(dma);
1200 }
1202 /* do the proper sequence to abort the transfer in the
1203 * usb core; the dma engine should already be stopped.
1204 */
1205 musb_h_tx_flush_fifo(hw_ep);
1206 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1207 | MUSB_TXCSR_DMAENAB
1208 | MUSB_TXCSR_H_ERROR
1209 | MUSB_TXCSR_H_RXSTALL
1210 | MUSB_TXCSR_H_NAKTIMEOUT
1211 );
1213 musb_ep_select(musb, mbase, epnum);
1214 musb_writew(epio, MUSB_TXCSR, tx_csr);
1215 /* REVISIT may need to clear FLUSHFIFO ... */
1216 musb_writew(epio, MUSB_TXCSR, tx_csr);
1217 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1219 done = true;
1220 }
1222 /* second cppi case */
1223 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1224 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1225 return;
1226 }
1228 if (is_dma_capable() && dma && !status) {
1229 /*
1230 * DMA has completed. But if we're using DMA mode 1 (multi
1231 * packet DMA), we need a terminal TXPKTRDY interrupt before
1232 * we can consider this transfer completed, lest we trash
1233 * its last packet when writing the next URB's data. So we
1234 * switch back to mode 0 to get that interrupt; we'll come
1235 * back here once it happens.
1236 */
1237 if (tx_csr & MUSB_TXCSR_DMAMODE) {
1238 /*
1239 * We shouldn't clear DMAMODE with DMAENAB set; so
1240 * clear them in a safe order. That should be OK
1241 * once TXPKTRDY has been set (and I've never seen
1242 * it being 0 at this moment -- DMA interrupt latency
1243 * is significant) but if it hasn't been then we have
1244 * no choice but to stop being polite and ignore the
1245 * programmer's guide... :-)
1246 *
1247 * Note that we must write TXCSR with TXPKTRDY cleared
1248 * in order not to re-trigger the packet send (this bit
1249 * can't be cleared by CPU), and there's another caveat:
1250 * TXPKTRDY may be set shortly and then cleared in the
1251 * double-buffered FIFO mode, so we do an extra TXCSR
1252 * read for debouncing...
1253 */
1254 tx_csr &= musb_readw(epio, MUSB_TXCSR);
1255 if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1256 tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1257 MUSB_TXCSR_TXPKTRDY);
1258 musb_writew(epio, MUSB_TXCSR,
1259 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1260 }
1261 tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1262 MUSB_TXCSR_TXPKTRDY);
1263 musb_writew(epio, MUSB_TXCSR,
1264 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1266 /*
1267 * There is no guarantee that we'll get an interrupt
1268 * after clearing DMAMODE as we might have done this
1269 * too late (after TXPKTRDY was cleared by controller).
1270 * Re-read TXCSR as we have spoiled its previous value.
1271 */
1272 tx_csr = musb_readw(epio, MUSB_TXCSR);
1273 }
1275 /*
1276 * We may get here from a DMA completion or TXPKTRDY interrupt.
1277 * In any case, we must check the FIFO status here and bail out
1278 * only if the FIFO still has data -- that should prevent the
1279 * "missed" TXPKTRDY interrupts and deal with double-buffered
1280 * FIFO mode too...
1281 */
1282 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1283 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
1284 "CSR %04x\n", tx_csr);
1285 return;
1286 }
1287 }
1289 if (!status || dma || usb_pipeisoc(pipe)) {
1290 if (dma)
1291 length = dma->actual_len;
1292 else
1293 length = qh->segsize;
1294 qh->offset += length;
1296 if (usb_pipeisoc(pipe)) {
1297 struct usb_iso_packet_descriptor *d;
1299 d = urb->iso_frame_desc + qh->iso_idx;
1300 d->actual_length = length;
1301 d->status = status;
1302 if (++qh->iso_idx >= urb->number_of_packets) {
1303 done = true;
1304 } else {
1305 d++;
1306 offset = d->offset;
1307 length = d->length;
1308 }
1309 } else if (dma && urb->transfer_buffer_length == qh->offset) {
1310 done = true;
1311 } else {
1312 /* see if we need to send more data, or ZLP */
1313 if (qh->segsize < qh->maxpacket)
1314 done = true;
1315 else if (qh->offset == urb->transfer_buffer_length
1316 && !(urb->transfer_flags
1317 & URB_ZERO_PACKET))
1318 done = true;
1319 if (!done) {
1320 offset = qh->offset;
1321 length = urb->transfer_buffer_length - offset;
1322 transfer_pending = true;
1323 }
1324 }
1325 }
1327 /* urb->status != -EINPROGRESS means request has been faulted,
1328 * so we must abort this transfer after cleanup
1329 */
1330 if (urb->status != -EINPROGRESS) {
1331 done = true;
1332 if (status == 0)
1333 status = urb->status;
1334 }
1336 if (done) {
1337 /* set status */
1338 urb->status = status;
1339 urb->actual_length = qh->offset;
1340 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1341 return;
1342 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
1343 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
1344 offset, length)) {
1345 if (is_cppi_enabled(musb) || tusb_dma_omap(musb))
1346 musb_h_tx_dma_start(hw_ep);
1347 return;
1348 }
1349 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1350 dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
1351 return;
1352 }
1354 /*
1355 * PIO: start next packet in this URB.
1356 *
1357 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
1358 * (and presumably, FIFO is not half-full) we should write *two*
1359 * packets before updating TXCSR; other docs disagree...
1360 */
1361 if (length > qh->maxpacket)
1362 length = qh->maxpacket;
1363 /* Unmap the buffer so that CPU can use it */
1364 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
1365 musb->ops->write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1366 qh->segsize = length;
1368 musb_ep_select(musb, mbase, epnum);
1369 musb_writew(epio, MUSB_TXCSR,
1370 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1371 }
1374 /* Host side RX (IN) using Mentor DMA works as follows:
1375 submit_urb ->
1376 - if queue was empty, ProgramEndpoint
1377 - first IN token is sent out (by setting ReqPkt)
1378 LinuxIsr -> RxReady()
1379 /\ => first packet is received
1380 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1381 | -> DMA Isr (transfer complete) -> RxReady()
1382 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1383 | - if urb not complete, send next IN token (ReqPkt)
1384 | | else complete urb.
1385 | |
1386 ---------------------------
1387 *
1388 * Nuances of mode 1:
1389 * For short packets, no ack (+RxPktRdy) is sent automatically
1390 * (even if AutoClear is ON)
1391 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1392 * automatically => major problem, as collecting the next packet becomes
1393 * difficult. Hence mode 1 is not used.
1394 *
1395 * REVISIT
1396 * All we care about at this driver level is that
1397 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1398 * (b) termination conditions are: short RX, or buffer full;
1399 * (c) fault modes include
1400 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1401 * (and that endpoint's dma queue stops immediately)
1402 * - overflow (full, PLUS more bytes in the terminal packet)
1403 *
1404 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1405 * thus be a great candidate for using mode 1 ... for all but the
1406 * last packet of one URB's transfer.
1407 */
1409 /* Schedule next QH from musb->in_bulk and move the current qh to
1410 * the end; avoids starvation for other endpoints.
1411 */
1412 static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
1413 {
1414 struct dma_channel *dma;
1415 struct urb *urb;
1416 void __iomem *mbase = musb->mregs;
1417 void __iomem *epio = ep->regs;
1418 struct musb_qh *cur_qh, *next_qh;
1419 u16 rx_csr;
1421 musb_ep_select(musb, mbase, ep->epnum);
1422 dma = is_dma_capable() ? ep->rx_channel : NULL;
1424 /* clear nak timeout bit */
1425 rx_csr = musb_readw(epio, MUSB_RXCSR);
1426 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1427 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1428 musb_writew(epio, MUSB_RXCSR, rx_csr);
1430 cur_qh = first_qh(&musb->in_bulk);
1431 if (cur_qh) {
1432 urb = next_urb(cur_qh);
1433 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1434 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1435 musb->dma_controller->channel_abort(dma);
1436 urb->actual_length += dma->actual_len;
1437 dma->actual_len = 0L;
1438 }
1439 musb_save_toggle(cur_qh, 1, urb);
1441 /* move cur_qh to end of queue */
1442 list_move_tail(&cur_qh->ring, &musb->in_bulk);
1444 /* get the next qh from musb->in_bulk */
1445 next_qh = first_qh(&musb->in_bulk);
1447 /* set rx_reinit and schedule the next qh */
1448 ep->rx_reinit = 1;
1449 musb_start_urb(musb, 1, next_qh);
1450 }
1451 }
1453 /*
1454 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1455 * and high-bandwidth IN transfer cases.
1456 */
1457 void musb_host_rx(struct musb *musb, u8 epnum)
1458 {
1459 struct urb *urb;
1460 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1461 void __iomem *epio = hw_ep->regs;
1462 struct musb_qh *qh = hw_ep->in_qh;
1463 size_t xfer_len;
1464 void __iomem *mbase = musb->mregs;
1465 int pipe;
1466 u16 rx_csr, val;
1467 bool iso_err = false;
1468 bool done = false;
1469 u32 status;
1470 struct dma_channel *dma;
1472 musb_ep_select(musb, mbase, epnum);
1474 urb = next_urb(qh);
1475 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1476 status = 0;
1477 xfer_len = 0;
1479 rx_csr = musb_readw(epio, MUSB_RXCSR);
1480 val = rx_csr;
1482 if (unlikely(!urb)) {
1483 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1484 * usbtest #11 (unlinks) triggers it regularly, sometimes
1485 * with fifo full. (Only with DMA??)
1486 */
1487 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1488 musb_readw(epio, MUSB_RXCOUNT));
1489 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1490 return;
1491 }
1493 pipe = urb->pipe;
1495 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1496 epnum, rx_csr, urb->actual_length,
1497 dma ? dma->actual_len : 0);
1499 /* check for errors, concurrent stall & unlink is not really
1500 * handled yet! */
1501 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1502 dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
1504 /* stall; record URB status */
1505 status = -EPIPE;
1507 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1508 dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
1510 status = -EPROTO;
1511 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1513 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1515 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1516 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
1518 /* NOTE: NAKing is *NOT* an error, so we want to
1519 * continue. Except ... if there's a request for
1520 * another QH, use that instead of starving it.
1521 *
1522 * Devices like Ethernet and serial adapters keep
1523 * reads posted at all times, which will starve
1524 * other devices without this logic.
1525 */
1526 if (usb_pipebulk(urb->pipe)
1527 && qh->mux == 1
1528 && !list_is_singular(&musb->in_bulk)) {
1529 musb_bulk_rx_nak_timeout(musb, hw_ep);
1530 return;
1531 }
1532 musb_ep_select(musb, mbase, epnum);
1533 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1534 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1535 musb_writew(epio, MUSB_RXCSR, rx_csr);
1537 goto finish;
1538 } else {
1539 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
1540 /* packet error reported later */
1541 iso_err = true;
1542 }
1543 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1544 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
1545 epnum);
1546 status = -EPROTO;
1547 }
1549 /* faults abort the transfer */
1550 if (status) {
1551 /* clean up dma and collect transfer count */
1552 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1553 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1554 (void) musb->dma_controller->channel_abort(dma);
1555 xfer_len = dma->actual_len;
1556 }
1557 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1558 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1559 done = true;
1560 goto finish;
1561 }
1563 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1564 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1565 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1566 goto finish;
1567 }
1569 /* thorough shutdown for now ... given more precise fault handling
1570 * and better queueing support, we might keep a DMA pipeline going
1571 * while processing this irq for earlier completions.
1572 */
1574 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1576 if (!is_inventra_dma(musb) && (rx_csr & MUSB_RXCSR_H_REQPKT)) {
1577 /* REVISIT this happened for a while on some short reads...
1578 * the cleanup still needs investigation... looks bad...
1579 * and also duplicates dma cleanup code above ... plus,
1580 * shouldn't this be the "half full" double buffer case?
1581 */
1582 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1583 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1584 (void) musb->dma_controller->channel_abort(dma);
1585 xfer_len = dma->actual_len;
1586 done = true;
1587 }
1589 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1590 xfer_len, dma ? ", dma" : "");
1591 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1593 musb_ep_select(musb, mbase, epnum);
1594 musb_writew(epio, MUSB_RXCSR,
1595 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1596 }
1597 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1598 xfer_len = dma->actual_len;
1600 val &= ~(MUSB_RXCSR_DMAENAB
1601 | MUSB_RXCSR_H_AUTOREQ
1602 | MUSB_RXCSR_AUTOCLEAR
1603 | MUSB_RXCSR_RXPKTRDY);
1604 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1606 if (is_inventra_dma(musb)) {
1607 if (usb_pipeisoc(pipe)) {
1608 struct usb_iso_packet_descriptor *d;
1610 d = urb->iso_frame_desc + qh->iso_idx;
1611 d->actual_length = xfer_len;
1613 /* even if there was an error, we did the dma
1614 * for iso_frame_desc->length
1615 */
1616 if (d->status != -EILSEQ
1617 && d->status != -EOVERFLOW)
1618 d->status = 0;
1620 if (++qh->iso_idx >= urb->number_of_packets)
1621 done = true;
1622 else
1623 done = false;
1625 } else {
1626 /* done if urb buffer is full or short packet is recd */
1627 done = (urb->actual_length + xfer_len >=
1628 urb->transfer_buffer_length
1629 || dma->actual_len < qh->maxpacket);
1630 }
1632 /* send IN token for next packet, without AUTOREQ */
1633 if (!done) {
1634 val |= MUSB_RXCSR_H_REQPKT;
1635 musb_writew(epio, MUSB_RXCSR,
1636 MUSB_RXCSR_H_WZC_BITS | val);
1637 }
1639 dev_dbg(musb->controller,
1640 "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
1641 done ? "off" : "reset",
1642 musb_readw(epio, MUSB_RXCSR),
1643 musb_readw(epio, MUSB_RXCOUNT));
1644 } else {
1645 done = true;
1646 }
1647 } else if (urb->status == -EINPROGRESS) {
1648 /* if no errors, be sure a packet is ready for unloading */
1649 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1650 status = -EPROTO;
1651 ERR("Rx interrupt with no errors or packet!\n");
1653 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1655 /* SCRUB (RX) */
1656 /* do the proper sequence to abort the transfer */
1657 musb_ep_select(musb, mbase, epnum);
1658 val &= ~MUSB_RXCSR_H_REQPKT;
1659 musb_writew(epio, MUSB_RXCSR, val);
1660 goto finish;
1661 }
1663 /* we are expecting IN packets */
1664 if (is_inventra_dma(musb) && dma) {
1665 struct dma_controller *c;
1666 u16 rx_count;
1667 int ret, length;
1668 dma_addr_t buf;
1670 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1672 dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n",
1673 epnum, rx_count,
1674 urb->transfer_dma
1675 + urb->actual_length,
1676 qh->offset,
1677 urb->transfer_buffer_length);
1679 c = musb->dma_controller;
1681 if (usb_pipeisoc(pipe)) {
1682 int d_status = 0;
1683 struct usb_iso_packet_descriptor *d;
1685 d = urb->iso_frame_desc + qh->iso_idx;
1687 if (iso_err) {
1688 d_status = -EILSEQ;
1689 urb->error_count++;
1690 }
1691 if (rx_count > d->length) {
1692 if (d_status == 0) {
1693 d_status = -EOVERFLOW;
1694 urb->error_count++;
1695 }
1696 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
1697 rx_count, d->length);
1699 length = d->length;
1700 } else
1701 length = rx_count;
1702 d->status = d_status;
1703 buf = urb->transfer_dma + d->offset;
1704 } else {
1705 length = rx_count;
1706 buf = urb->transfer_dma +
1707 urb->actual_length;
1708 }
1710 dma->desired_mode = 0;
1711 #ifdef USE_MODE1
1712 /* because of the issue below, mode 1 will
1713 * only rarely behave with correct semantics.
1714 */
1715 if ((urb->transfer_flags &
1716 URB_SHORT_NOT_OK)
1717 && (urb->transfer_buffer_length -
1718 urb->actual_length)
1719 > qh->maxpacket)
1720 dma->desired_mode = 1;
1721 if (rx_count < hw_ep->max_packet_sz_rx) {
1722 length = rx_count;
1723 dma->desired_mode = 0;
1724 } else {
1725 length = urb->transfer_buffer_length;
1726 }
1727 #endif
1729 /* Disadvantage of using mode 1:
1730 * It's basically usable only for mass storage class; essentially all
1731 * other protocols also terminate transfers on short packets.
1732 *
1733 * Details:
1734 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1735 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1736 * to use the extra IN token to grab the last packet using mode 0, then
1737 * the problem is that you cannot be sure when the device will send the
1738 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1739 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1740 * transfer, while sometimes it is recd just a little late so that if you
1741 * try to configure for mode 0 soon after the mode 1 transfer is
1742 * completed, you will find rxcount 0. Okay, so you might think why not
1743 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1744 */
1746 val = musb_readw(epio, MUSB_RXCSR);
1747 val &= ~MUSB_RXCSR_H_REQPKT;
1749 if (dma->desired_mode == 0)
1750 val &= ~MUSB_RXCSR_H_AUTOREQ;
1751 else
1752 val |= MUSB_RXCSR_H_AUTOREQ;
1753 val |= MUSB_RXCSR_DMAENAB;
1755 /* autoclear shouldn't be set in high bandwidth */
1756 if (qh->hb_mult == 1)
1757 val |= MUSB_RXCSR_AUTOCLEAR;
1759 musb_writew(epio, MUSB_RXCSR,
1760 MUSB_RXCSR_H_WZC_BITS | val);
1762 /* REVISIT if when actual_length != 0,
1763 * transfer_buffer_length needs to be
1764 * adjusted first...
1765 */
1766 ret = c->channel_program(
1767 dma, qh->maxpacket,
1768 dma->desired_mode, buf, length);
1770 if (!ret) {
1771 c->channel_release(dma);
1772 hw_ep->rx_channel = NULL;
1773 dma = NULL;
1774 /* REVISIT reset CSR */
1775 }
1776 }
1778 if (!dma) {
1779 /* Unmap the buffer so that CPU can use it */
1780 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
1781 done = musb_host_packet_rx(musb, urb,
1782 epnum, iso_err);
1783 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
1784 }
1785 }
1787 finish:
1788 urb->actual_length += xfer_len;
1789 qh->offset += xfer_len;
1790 if (done) {
1791 if (urb->status == -EINPROGRESS)
1792 urb->status = status;
1793 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
1794 }
1795 }
1797 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1798 * the software schedule associates multiple such nodes with a given
1799 * host side hardware endpoint + direction; scheduling may activate
1800 * that hardware endpoint.
1801 */
1802 static int musb_schedule(
1803 struct musb *musb,
1804 struct musb_qh *qh,
1805 int is_in)
1806 {
1807 int idle;
1808 int best_diff;
1809 int best_end, epnum;
1810 struct musb_hw_ep *hw_ep = NULL;
1811 struct list_head *head = NULL;
1812 u8 toggle;
1813 u8 txtype;
1814 struct urb *urb = next_urb(qh);
1816 /* use fixed hardware for control and bulk */
1817 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
1818 head = &musb->control;
1819 hw_ep = musb->control_ep;
1820 goto success;
1821 }
1823 /* else, periodic transfers get muxed to other endpoints */
1825 /*
1826 * We know this qh hasn't been scheduled, so all we need to do
1827 * is choose which hardware endpoint to put it on ...
1828 *
1829 * REVISIT what we really want here is a regular schedule tree
1830 * like e.g. OHCI uses.
1831 */
1832 best_diff = 4096;
1833 best_end = -1;
1835 for (epnum = 1, hw_ep = musb->endpoints + 1;
1836 epnum < musb->nr_endpoints;
1837 epnum++, hw_ep++) {
1838 int diff;
1840 if (musb_ep_get_qh(hw_ep, is_in) != NULL)
1841 continue;
1843 if (hw_ep == musb->bulk_ep)
1844 continue;
1846 if (is_in)
1847 diff = hw_ep->max_packet_sz_rx;
1848 else
1849 diff = hw_ep->max_packet_sz_tx;
1850 diff -= (qh->maxpacket * qh->hb_mult);
1852 if (diff >= 0 && best_diff > diff) {
1854 /*
1855 * Mentor controller has a bug in that if we schedule
1856 * a BULK Tx transfer on an endpoint that had earlier
1857 * handled ISOC then the BULK transfer has to start on
1858 * a zero toggle. If the BULK transfer starts on a 1
1859 * toggle then this transfer will fail as the mentor
1860 * controller starts the Bulk transfer on a 0 toggle
1861 * irrespective of the programming of the toggle bits
1862 * in the TXCSR register. Check for this condition
1863 * while allocating the EP for a Tx Bulk transfer. If
1864 * so skip this EP.
1865 */
1866 hw_ep = musb->endpoints + epnum;
1867 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
1868 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
1869 >> 4) & 0x3;
1870 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
1871 toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
1872 continue;
1874 best_diff = diff;
1875 best_end = epnum;
1876 }
1877 }
1878 /* use bulk reserved ep1 if no other ep is free */
1879 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
1880 hw_ep = musb->bulk_ep;
1881 if (is_in)
1882 head = &musb->in_bulk;
1883 else
1884 head = &musb->out_bulk;
1886 /* Enable bulk RX NAK timeout scheme when bulk requests are
1887 * multiplexed. This scheme doen't work in high speed to full
1888 * speed scenario as NAK interrupts are not coming from a
1889 * full speed device connected to a high speed device.
1890 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
1891 * 4 (8 frame or 8ms) for FS device.
1892 */
1893 if (is_in && qh->dev)
1894 qh->intv_reg =
1895 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
1896 goto success;
1897 } else if (best_end < 0) {
1898 return -ENOSPC;
1899 }
1901 idle = 1;
1902 qh->mux = 0;
1903 hw_ep = musb->endpoints + best_end;
1904 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
1905 success:
1906 if (head) {
1907 idle = list_empty(head);
1908 list_add_tail(&qh->ring, head);
1909 qh->mux = 1;
1910 }
1911 qh->hw_ep = hw_ep;
1912 qh->hep->hcpriv = qh;
1913 if (idle)
1914 musb_start_urb(musb, is_in, qh);
1915 return 0;
1916 }
1918 static int musb_urb_enqueue(
1919 struct usb_hcd *hcd,
1920 struct urb *urb,
1921 gfp_t mem_flags)
1922 {
1923 unsigned long flags;
1924 struct musb *musb = hcd_to_musb(hcd);
1925 struct usb_host_endpoint *hep = urb->ep;
1926 struct musb_qh *qh;
1927 struct usb_endpoint_descriptor *epd = &hep->desc;
1928 int ret;
1929 unsigned type_reg;
1930 unsigned interval;
1932 /* host role must be active */
1933 if (!is_host_active(musb) || !musb->is_active)
1934 return -ENODEV;
1936 spin_lock_irqsave(&musb->lock, flags);
1937 ret = usb_hcd_link_urb_to_ep(hcd, urb);
1938 qh = ret ? NULL : hep->hcpriv;
1939 if (qh)
1940 urb->hcpriv = qh;
1942 INIT_LIST_HEAD(&urb->giveback_list);
1943 spin_unlock_irqrestore(&musb->lock, flags);
1945 /* DMA mapping was already done, if needed, and this urb is on
1946 * hep->urb_list now ... so we're done, unless hep wasn't yet
1947 * scheduled onto a live qh.
1948 *
1949 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
1950 * disabled, testing for empty qh->ring and avoiding qh setup costs
1951 * except for the first urb queued after a config change.
1952 */
1953 if (qh || ret)
1954 return ret;
1956 /* Allocate and initialize qh, minimizing the work done each time
1957 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
1958 *
1959 * REVISIT consider a dedicated qh kmem_cache, so it's harder
1960 * for bugs in other kernel code to break this driver...
1961 */
1962 qh = kzalloc(sizeof *qh, mem_flags);
1963 if (!qh) {
1964 spin_lock_irqsave(&musb->lock, flags);
1965 usb_hcd_unlink_urb_from_ep(hcd, urb);
1966 spin_unlock_irqrestore(&musb->lock, flags);
1967 return -ENOMEM;
1968 }
1970 qh->hep = hep;
1971 qh->dev = urb->dev;
1972 INIT_LIST_HEAD(&qh->ring);
1973 qh->is_ready = 1;
1975 qh->maxpacket = usb_endpoint_maxp(epd);
1976 qh->type = usb_endpoint_type(epd);
1978 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
1979 * Some musb cores don't support high bandwidth ISO transfers; and
1980 * we don't (yet!) support high bandwidth interrupt transfers.
1981 */
1982 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
1983 if (qh->hb_mult > 1) {
1984 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
1986 if (ok)
1987 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
1988 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
1989 if (!ok) {
1990 ret = -EMSGSIZE;
1991 goto done;
1992 }
1993 qh->maxpacket &= 0x7ff;
1994 }
1996 qh->epnum = usb_endpoint_num(epd);
1998 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
1999 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
2001 /* precompute rxtype/txtype/type0 register */
2002 type_reg = (qh->type << 4) | qh->epnum;
2003 switch (urb->dev->speed) {
2004 case USB_SPEED_LOW:
2005 type_reg |= 0xc0;
2006 break;
2007 case USB_SPEED_FULL:
2008 type_reg |= 0x80;
2009 break;
2010 default:
2011 type_reg |= 0x40;
2012 }
2013 qh->type_reg = type_reg;
2015 /* Precompute RXINTERVAL/TXINTERVAL register */
2016 switch (qh->type) {
2017 case USB_ENDPOINT_XFER_INT:
2018 /*
2019 * Full/low speeds use the linear encoding,
2020 * high speed uses the logarithmic encoding.
2021 */
2022 if (urb->dev->speed <= USB_SPEED_FULL) {
2023 interval = max_t(u8, epd->bInterval, 1);
2024 break;
2025 }
2026 /* FALLTHROUGH */
2027 case USB_ENDPOINT_XFER_ISOC:
2028 /* ISO always uses logarithmic encoding */
2029 interval = min_t(u8, epd->bInterval, 16);
2030 break;
2031 default:
2032 /* REVISIT we actually want to use NAK limits, hinting to the
2033 * transfer scheduling logic to try some other qh, e.g. try
2034 * for 2 msec first:
2035 *
2036 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
2037 *
2038 * The downside of disabling this is that transfer scheduling
2039 * gets VERY unfair for nonperiodic transfers; a misbehaving
2040 * peripheral could make that hurt. That's perfectly normal
2041 * for reads from network or serial adapters ... so we have
2042 * partial NAKlimit support for bulk RX.
2043 *
2044 * The upside of disabling it is simpler transfer scheduling.
2045 */
2046 interval = 0;
2047 }
2048 qh->intv_reg = interval;
2050 /* precompute addressing for external hub/tt ports */
2051 if (musb->is_multipoint) {
2052 struct usb_device *parent = urb->dev->parent;
2054 if (parent != hcd->self.root_hub) {
2055 qh->h_addr_reg = (u8) parent->devnum;
2057 /* set up tt info if needed */
2058 if (urb->dev->tt) {
2059 qh->h_port_reg = (u8) urb->dev->ttport;
2060 if (urb->dev->tt->hub)
2061 qh->h_addr_reg =
2062 (u8) urb->dev->tt->hub->devnum;
2063 if (urb->dev->tt->multi)
2064 qh->h_addr_reg |= 0x80;
2065 }
2066 }
2067 }
2069 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
2070 * until we get real dma queues (with an entry for each urb/buffer),
2071 * we only have work to do in the former case.
2072 */
2073 spin_lock_irqsave(&musb->lock, flags);
2074 if (hep->hcpriv) {
2075 /* some concurrent activity submitted another urb to hep...
2076 * odd, rare, error prone, but legal.
2077 */
2078 kfree(qh);
2079 qh = NULL;
2080 ret = 0;
2081 } else
2082 ret = musb_schedule(musb, qh,
2083 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2085 if (ret == 0) {
2086 urb->hcpriv = qh;
2087 /* FIXME set urb->start_frame for iso/intr, it's tested in
2088 * musb_start_urb(), but otherwise only konicawc cares ...
2089 */
2090 }
2091 spin_unlock_irqrestore(&musb->lock, flags);
2093 done:
2094 if (ret != 0) {
2095 spin_lock_irqsave(&musb->lock, flags);
2096 usb_hcd_unlink_urb_from_ep(hcd, urb);
2097 spin_unlock_irqrestore(&musb->lock, flags);
2098 kfree(qh);
2099 }
2100 return ret;
2101 }
2104 /*
2105 * abort a transfer that's at the head of a hardware queue.
2106 * called with controller locked, irqs blocked
2107 * that hardware queue advances to the next transfer, unless prevented
2108 */
2109 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2110 {
2111 struct musb_hw_ep *ep = qh->hw_ep;
2112 struct musb *musb = ep->musb;
2113 void __iomem *epio = ep->regs;
2114 unsigned hw_end = ep->epnum;
2115 void __iomem *regs = ep->musb->mregs;
2116 int is_in = usb_pipein(urb->pipe);
2117 int status = 0;
2118 u16 csr;
2120 musb_ep_select(ep->musb, regs, hw_end);
2122 if (is_dma_capable()) {
2123 struct dma_channel *dma;
2125 dma = is_in ? ep->rx_channel : ep->tx_channel;
2126 if (dma) {
2127 status = ep->musb->dma_controller->channel_abort(dma);
2128 dev_dbg(musb->controller,
2129 "abort %cX%d DMA for urb %p --> %d\n",
2130 is_in ? 'R' : 'T', ep->epnum,
2131 urb, status);
2132 urb->actual_length += dma->actual_len;
2133 }
2134 }
2136 /* turn off DMA requests, discard state, stop polling ... */
2137 if (is_in) {
2138 /* giveback saves bulk toggle */
2139 csr = musb_h_flush_rxfifo(ep, 0);
2141 /* REVISIT we still get an irq; should likely clear the
2142 * endpoint's irq status here to avoid bogus irqs.
2143 * clearing that status is platform-specific...
2144 */
2145 } else if (ep->epnum) {
2146 musb_h_tx_flush_fifo(ep);
2147 csr = musb_readw(epio, MUSB_TXCSR);
2148 csr &= ~(MUSB_TXCSR_AUTOSET
2149 | MUSB_TXCSR_DMAENAB
2150 | MUSB_TXCSR_H_RXSTALL
2151 | MUSB_TXCSR_H_NAKTIMEOUT
2152 | MUSB_TXCSR_H_ERROR
2153 | MUSB_TXCSR_TXPKTRDY);
2154 musb_writew(epio, MUSB_TXCSR, csr);
2155 /* REVISIT may need to clear FLUSHFIFO ... */
2156 musb_writew(epio, MUSB_TXCSR, csr);
2157 /* flush cpu writebuffer */
2158 csr = musb_readw(epio, MUSB_TXCSR);
2159 } else {
2160 musb_h_ep0_flush_fifo(ep);
2161 }
2162 if (status == 0)
2163 musb_advance_schedule(ep->musb, urb, ep, is_in);
2164 return status;
2165 }
2167 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2168 {
2169 struct musb *musb = hcd_to_musb(hcd);
2170 struct musb_qh *qh;
2171 unsigned long flags;
2172 int is_in = usb_pipein(urb->pipe);
2173 int ret;
2175 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
2176 usb_pipedevice(urb->pipe),
2177 usb_pipeendpoint(urb->pipe),
2178 is_in ? "in" : "out");
2180 spin_lock_irqsave(&musb->lock, flags);
2181 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2182 if (ret)
2183 goto done;
2185 qh = urb->hcpriv;
2186 if (!qh)
2187 goto done;
2189 /*
2190 * Any URB not actively programmed into endpoint hardware can be
2191 * immediately given back; that's any URB not at the head of an
2192 * endpoint queue, unless someday we get real DMA queues. And even
2193 * if it's at the head, it might not be known to the hardware...
2194 *
2195 * Otherwise abort current transfer, pending DMA, etc.; urb->status
2196 * has already been updated. This is a synchronous abort; it'd be
2197 * OK to hold off until after some IRQ, though.
2198 *
2199 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
2200 */
2201 if (!qh->is_ready
2202 || urb->urb_list.prev != &qh->hep->urb_list
2203 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2204 int ready = qh->is_ready;
2206 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
2208 qh->is_ready = 0;
2209 spin_unlock(&musb->lock);
2210 musb_giveback(musb, urb, 0);
2211 spin_lock(&musb->lock);
2212 qh->is_ready = ready;
2214 /* If nothing else (usually musb_giveback) is using it
2215 * and its URB list has emptied, recycle this qh.
2216 */
2217 if (ready && list_empty(&qh->hep->urb_list)) {
2218 qh->hep->hcpriv = NULL;
2219 list_del(&qh->ring);
2220 kfree(qh);
2221 }
2222 } else
2223 ret = musb_cleanup_urb(urb, qh);
2224 done:
2225 spin_unlock_irqrestore(&musb->lock, flags);
2226 return ret;
2227 }
2229 /* disable an endpoint */
2230 static void
2231 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2232 {
2233 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
2234 unsigned long flags;
2235 struct musb *musb = hcd_to_musb(hcd);
2236 struct musb_qh *qh;
2237 struct urb *urb;
2239 spin_lock_irqsave(&musb->lock, flags);
2241 qh = hep->hcpriv;
2242 if (qh == NULL)
2243 goto exit;
2245 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2247 /* Kick the first URB off the hardware, if needed */
2248 qh->is_ready = 0;
2249 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2250 urb = next_urb(qh);
2252 /* make software (then hardware) stop ASAP */
2253 if (!urb->unlinked)
2254 urb->status = -ESHUTDOWN;
2256 /* cleanup */
2257 musb_cleanup_urb(urb, qh);
2259 /* Then nuke all the others ... and advance the
2260 * queue on hw_ep (e.g. bulk ring) when we're done.
2261 */
2262 while (!list_empty(&hep->urb_list)) {
2263 urb = next_urb(qh);
2264 urb->status = -ESHUTDOWN;
2265 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2266 }
2267 } else {
2268 /* Just empty the queue; the hardware is busy with
2269 * other transfers, and since !qh->is_ready nothing
2270 * will activate any of these as it advances.
2271 */
2272 while (!list_empty(&hep->urb_list)) {
2273 urb = next_urb(qh);
2274 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
2275 spin_unlock(&musb->lock);
2276 musb_giveback(musb, urb, -ESHUTDOWN);
2277 spin_lock(&musb->lock);
2278 }
2280 hep->hcpriv = NULL;
2281 list_del(&qh->ring);
2282 kfree(qh);
2283 }
2284 exit:
2285 spin_unlock_irqrestore(&musb->lock, flags);
2286 }
2288 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2289 {
2290 struct musb *musb = hcd_to_musb(hcd);
2292 return musb_readw(musb->mregs, MUSB_FRAME);
2293 }
2295 static int musb_h_start(struct usb_hcd *hcd)
2296 {
2297 struct musb *musb = hcd_to_musb(hcd);
2299 /* NOTE: musb_start() is called when the hub driver turns
2300 * on port power, or when (OTG) peripheral starts.
2301 */
2302 hcd->state = HC_STATE_RUNNING;
2303 musb->port1_status = 0;
2304 return 0;
2305 }
2307 static void musb_h_stop(struct usb_hcd *hcd)
2308 {
2309 musb_stop(hcd_to_musb(hcd));
2310 hcd->state = HC_STATE_HALT;
2311 }
2313 static int musb_bus_suspend(struct usb_hcd *hcd)
2314 {
2315 struct musb *musb = hcd_to_musb(hcd);
2316 u8 devctl;
2318 if (!is_host_active(musb))
2319 return 0;
2321 switch (musb->xceiv->state) {
2322 case OTG_STATE_A_SUSPEND:
2323 return 0;
2324 case OTG_STATE_A_WAIT_VRISE:
2325 /* ID could be grounded even if there's no device
2326 * on the other end of the cable. NOTE that the
2327 * A_WAIT_VRISE timers are messy with MUSB...
2328 */
2329 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2330 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2331 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2332 break;
2333 default:
2334 break;
2335 }
2337 if (musb->is_active) {
2338 dev_dbg(musb->controller, "trying to suspend as %s while active\n",
2339 otg_state_string(musb->xceiv->state));
2340 return -EBUSY;
2341 } else
2342 return 0;
2343 }
2345 static int musb_bus_resume(struct usb_hcd *hcd)
2346 {
2347 /* resuming child port does the work */
2348 return 0;
2349 }
2351 const struct hc_driver musb_hc_driver = {
2352 .description = "musb-hcd",
2353 .product_desc = "MUSB HDRC host driver",
2354 .hcd_priv_size = sizeof(struct musb),
2355 .flags = HCD_USB2 | HCD_MEMORY,
2357 /* not using irq handler or reset hooks from usbcore, since
2358 * those must be shared with peripheral code for OTG configs
2359 */
2361 .start = musb_h_start,
2362 .stop = musb_h_stop,
2364 .get_frame_number = musb_h_get_frame_number,
2366 .urb_enqueue = musb_urb_enqueue,
2367 .urb_dequeue = musb_urb_dequeue,
2368 .endpoint_disable = musb_h_disable,
2370 .hub_status_data = musb_hub_status_data,
2371 .hub_control = musb_hub_control,
2372 .bus_suspend = musb_bus_suspend,
2373 .bus_resume = musb_bus_resume,
2374 /* .start_port_reset = NULL, */
2375 /* .hub_irq_enable = NULL, */
2376 };