058c4ecd3820fcc84693eaa551bc636142af5d3e
1 /*
2 * Texas Instruments TI81XX "usb platform glue layer"
3 *
4 * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * Based on the DaVinci "glue layer" code.
7 * Copyright (C) 2005-2006 by Texas Instruments
8 *
9 * This file is part of the Inventra Controller Driver for Linux.
10 *
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
14 * Foundation.
15 *
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
29 #include <linux/init.h>
30 #include <linux/clk.h>
31 #include <linux/io.h>
32 #include <linux/usb/otg.h>
33 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/module.h>
37 #include "cppi41.h"
38 #include "ti81xx.h"
40 #include "musb_core.h"
41 #include "cppi41_dma.h"
43 struct ti81xx_glue {
44 struct device *dev;
45 struct clk *ick; /* common usbss interface clk */
46 struct clk *fck; /* common usbss functional clk */
47 struct resource *mem_pa; /* usbss memory resource */
48 void *mem_va; /* ioremapped virtual address */
49 struct platform_device *musb[2];/* child musb pdevs */
50 u8 irq; /* usbss irq */
51 };
52 static u64 musb_dmamask = DMA_BIT_MASK(32);
53 static void *usbss_virt_base;
54 static u8 usbss_init_done;
55 struct musb *gmusb[2];
57 u8 usbid_sw_ctrl;
58 #undef USB_TI81XX_DEBUG
60 #ifdef USB_TI81XX_DEBUG
61 #define dprintk(x, ...) printk(x, ## __VA_ARGS__)
62 #else
63 #define dprintk(x, ...)
64 #endif
66 #ifdef CONFIG_USB_TI_CPPI41_DMA
67 static irqreturn_t cppi41dma_Interrupt(int irq, void *hci);
68 static u8 cppi41_init_done;
69 static void *cppi41_dma_base;
70 #define CPPI41_ADDR(offs) ((void *)((u32)cppi41_dma_base + (offs - 0x2000)))
71 #endif
73 extern void omap_ctrl_writel(u32 val, u16 offset);
74 extern u32 omap_ctrl_readl(u16 offset);
76 static inline u32 usbss_read(u32 offset)
77 {
78 if (!usbss_init_done)
79 return 0;
80 return __raw_readl(usbss_virt_base + offset);
81 }
83 static inline void usbss_write(u32 offset, u32 data)
84 {
85 if (!usbss_init_done)
86 return ;
87 __raw_writel(data, usbss_virt_base + offset);
88 }
90 static void usbotg_ss_init(void)
91 {
92 if (!usbss_init_done) {
93 /* reset the usbss for usb0/usb1 */
94 usbss_write(USBSS_SYSCONFIG,
95 usbss_read(USBSS_SYSCONFIG) | USB_SOFT_RESET_MASK);
97 /* clear any USBSS interrupts */
98 usbss_write(USBSS_IRQ_EOI, 0);
99 usbss_write(USBSS_IRQ_STATUS, usbss_read(USBSS_IRQ_STATUS));
100 usbss_init_done = 1;
101 }
102 }
103 static void usbotg_ss_uninit(void)
104 {
105 if (usbss_init_done) {
106 usbss_init_done = 0;
107 usbss_virt_base = 0;
108 }
109 }
110 void set_frame_threshold(struct musb *musb, u8 is_tx, u8 epnum, u8 value, u8 en_intr)
111 {
112 u32 base, reg_val, frame_intr = 0, frame_base = 0;
113 u32 offs = epnum/4*4;
114 u8 indx = (epnum % 4) * 8;
116 if (is_tx)
117 base = musb->id ? USBSS_IRQ_FRAME_THRESHOLD_TX1 :
118 USBSS_IRQ_FRAME_THRESHOLD_TX0;
119 else
120 base = musb->id ? USBSS_IRQ_FRAME_THRESHOLD_RX1 :
121 USBSS_IRQ_FRAME_THRESHOLD_RX0;
123 reg_val = usbss_read(base + offs);
124 reg_val &= ~(0xFF << indx);
125 reg_val |= (value << indx);
126 usbss_write(base + offs, reg_val);
128 if (en_intr) {
129 frame_base = musb->id ? USBSS_IRQ_FRAME_ENABLE_1 :
130 USBSS_IRQ_FRAME_ENABLE_0;
131 frame_intr = musb->id ? usbss_read(USBSS_IRQ_FRAME_ENABLE_0) :
132 usbss_read(USBSS_IRQ_FRAME_ENABLE_1);
133 frame_intr |= is_tx ? (1 << epnum) : (1 << (16 + epnum));
134 usbss_write(frame_base, frame_intr);
135 dev_dbg(musb->controller, "%s: framebase=%x, frame_intr=%x\n",
136 is_tx ? "tx" : "rx", frame_base, frame_intr);
137 }
138 }
140 void set_dma_threshold(struct musb *musb, u8 is_tx, u8 epnum, u8 value)
141 {
142 u32 base, reg_val;
143 u32 offs = epnum/4*4;
144 u8 indx = (epnum % 4) * 8;
146 if (musb->id == 0)
147 base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX0 :
148 USBSS_IRQ_DMA_THRESHOLD_RX0;
149 else
150 base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX1 :
151 USBSS_IRQ_DMA_THRESHOLD_RX1;
153 reg_val = usbss_read(base + offs);
154 reg_val &= ~(0xFF << indx);
155 reg_val |= (value << indx);
156 dev_dbg(musb->controller, "base=%x, offs=%x, indx=%d, reg_val = (%x)%x\n",
157 base, offs, indx, reg_val, usbss_read(base + offs));
158 usbss_write(base + offs, reg_val);
159 }
161 /* ti81xx specific read/write functions */
162 u16 ti81xx_musb_readw(const void __iomem *addr, unsigned offset)
163 {
164 u32 tmp;
165 u16 val;
167 tmp = __raw_readl(addr + (offset & ~3));
169 switch (offset & 0x3) {
170 case 0:
171 val = (tmp & 0xffff);
172 break;
173 case 1:
174 val = (tmp >> 8) & 0xffff;
175 break;
176 case 2:
177 case 3:
178 default:
179 val = (tmp >> 16) & 0xffff;
180 break;
181 }
182 return val;
183 }
185 void ti81xx_musb_writew(void __iomem *addr, unsigned offset, u16 data)
186 {
187 __raw_writew(data, addr + offset);
188 }
190 u8 ti81xx_musb_readb(const void __iomem *addr, unsigned offset)
191 {
192 u32 tmp;
193 u8 val;
195 tmp = __raw_readl(addr + (offset & ~3));
197 switch (offset & 0x3) {
198 case 0:
199 val = tmp & 0xff;
200 break;
201 case 1:
202 val = (tmp >> 8);
203 break;
204 case 2:
205 val = (tmp >> 16);
206 break;
207 case 3:
208 default:
209 val = (tmp >> 24);
210 break;
211 }
212 return val;
213 }
214 void ti81xx_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
215 {
216 __raw_writeb(data, addr + offset);
217 }
219 #ifdef CONFIG_USB_TI_CPPI41_DMA
220 /*
221 * CPPI 4.1 resources used for USB OTG controller module:
222 *
223 tx/rx completion queues for usb0 */
224 static u16 tx_comp_q[] = {93, 94, 95, 96, 97,
225 98, 99, 100, 101, 102,
226 103, 104, 105, 106, 107 };
228 static u16 rx_comp_q[] = {109, 110, 111, 112, 113,
229 114, 115, 116, 117, 118,
230 119, 120, 121, 122, 123 };
232 /* tx/rx completion queues for usb1 */
233 static u16 tx_comp_q1[] = {125, 126, 127, 128, 129,
234 130, 131, 132, 133, 134,
235 135, 136, 137, 138, 139 };
237 static u16 rx_comp_q1[] = {141, 142, 143, 144, 145,
238 146, 147, 148, 149, 150,
239 151, 152, 153, 154, 155 };
241 /* Fair scheduling */
242 u32 dma_sched_table[] = {
243 0x81018000, 0x83038202, 0x85058404, 0x87078606,
244 0x89098808, 0x8b0b8a0a, 0x8d0d8c0c, 0x8f0f8e0e,
245 0x91119010, 0x93139212, 0x95159414, 0x97179616,
246 0x99199818, 0x9b1b9a1a, 0x9d1d9c1c, 0x00009e1e,
247 };
249 /* cppi41 dma tx channel info */
250 static const struct cppi41_tx_ch tx_ch_info[] = {
251 [0] = {
252 .port_num = 1,
253 .num_tx_queue = 2,
254 .tx_queue = { {0, 32} , {0, 33} }
255 },
256 [1] = {
257 .port_num = 2,
258 .num_tx_queue = 2,
259 .tx_queue = { {0, 34} , {0, 35} }
260 },
261 [2] = {
262 .port_num = 3,
263 .num_tx_queue = 2,
264 .tx_queue = { {0, 36} , {0, 37} }
265 },
266 [3] = {
267 .port_num = 4,
268 .num_tx_queue = 2,
269 .tx_queue = { {0, 38} , {0, 39} }
270 },
271 [4] = {
272 .port_num = 5,
273 .num_tx_queue = 2,
274 .tx_queue = { {0, 40} , {0, 41} }
275 },
276 [5] = {
277 .port_num = 6,
278 .num_tx_queue = 2,
279 .tx_queue = { {0, 42} , {0, 43} }
280 },
281 [6] = {
282 .port_num = 7,
283 .num_tx_queue = 2,
284 .tx_queue = { {0, 44} , {0, 45} }
285 },
286 [7] = {
287 .port_num = 8,
288 .num_tx_queue = 2,
289 .tx_queue = { {0, 46} , {0, 47} }
290 },
291 [8] = {
292 .port_num = 9,
293 .num_tx_queue = 2,
294 .tx_queue = { {0, 48} , {0, 49} }
295 },
296 [9] = {
297 .port_num = 10,
298 .num_tx_queue = 2,
299 .tx_queue = { {0, 50} , {0, 51} }
300 },
301 [10] = {
302 .port_num = 11,
303 .num_tx_queue = 2,
304 .tx_queue = { {0, 52} , {0, 53} }
305 },
306 [11] = {
307 .port_num = 12,
308 .num_tx_queue = 2,
309 .tx_queue = { {0, 54} , {0, 55} }
310 },
311 [12] = {
312 .port_num = 13,
313 .num_tx_queue = 2,
314 .tx_queue = { {0, 56} , {0, 57} }
315 },
316 [13] = {
317 .port_num = 14,
318 .num_tx_queue = 2,
319 .tx_queue = { {0, 58} , {0, 59} }
320 },
321 [14] = {
322 .port_num = 15,
323 .num_tx_queue = 2,
324 .tx_queue = { {0, 60} , {0, 61} }
325 },
326 [15] = {
327 .port_num = 1,
328 .num_tx_queue = 2,
329 .tx_queue = { {0, 62} , {0, 63} }
330 },
331 [16] = {
332 .port_num = 2,
333 .num_tx_queue = 2,
334 .tx_queue = { {0, 64} , {0, 65} }
335 },
336 [17] = {
337 .port_num = 3,
338 .num_tx_queue = 2,
339 .tx_queue = { {0, 66} , {0, 67} }
340 },
341 [18] = {
342 .port_num = 4,
343 .num_tx_queue = 2,
344 .tx_queue = { {0, 68} , {0, 69} }
345 },
346 [19] = {
347 .port_num = 5,
348 .num_tx_queue = 2,
349 .tx_queue = { {0, 70} , {0, 71} }
350 },
351 [20] = {
352 .port_num = 6,
353 .num_tx_queue = 2,
354 .tx_queue = { {0, 72} , {0, 73} }
355 },
356 [21] = {
357 .port_num = 7,
358 .num_tx_queue = 2,
359 .tx_queue = { {0, 74} , {0, 75} }
360 },
361 [22] = {
362 .port_num = 8,
363 .num_tx_queue = 2,
364 .tx_queue = { {0, 76} , {0, 77} }
365 },
366 [23] = {
367 .port_num = 9,
368 .num_tx_queue = 2,
369 .tx_queue = { {0, 78} , {0, 79} }
370 },
371 [24] = {
372 .port_num = 10,
373 .num_tx_queue = 2,
374 .tx_queue = { {0, 80} , {0, 81} }
375 },
376 [25] = {
377 .port_num = 11,
378 .num_tx_queue = 2,
379 .tx_queue = { {0, 82} , {0, 83} }
380 },
381 [26] = {
382 .port_num = 12,
383 .num_tx_queue = 2,
384 .tx_queue = { {0, 84} , {0, 85} }
385 },
386 [27] = {
387 .port_num = 13,
388 .num_tx_queue = 2,
389 .tx_queue = { {0, 86} , {0, 87} }
390 },
391 [28] = {
392 .port_num = 14,
393 .num_tx_queue = 2,
394 .tx_queue = { {0, 88} , {0, 89} }
395 },
396 [29] = {
397 .port_num = 15,
398 .num_tx_queue = 2,
399 .tx_queue = { {0, 90} , {0, 91} }
400 }
401 };
403 /* Queues 0 to 66 are pre-assigned, others are spare */
404 static const u32 assigned_queues[] = { 0xffffffff, /* queue 0..31 */
405 0xffffffff, /* queue 32..63 */
406 0xffffffff, /* queue 64..95 */
407 0xffffffff, /* queue 96..127 */
408 0x0fffffff /* queue 128..155 */
409 };
411 int __devinit cppi41_init(u8 id, u8 irq, int num_instances)
412 {
413 struct usb_cppi41_info *cppi_info = &usb_cppi41_info[id];
414 u16 numch, blknum, order;
415 u32 i;
417 /* init cppi info structure */
418 cppi_info->dma_block = 0;
419 for (i = 0 ; i < USB_CPPI41_NUM_CH ; i++)
420 cppi_info->ep_dma_ch[i] = i + (15 * id);
422 cppi_info->q_mgr = 0;
423 cppi_info->num_tx_comp_q = 15;
424 cppi_info->num_rx_comp_q = 15;
425 cppi_info->tx_comp_q = id ? tx_comp_q1 : tx_comp_q;
426 cppi_info->rx_comp_q = id ? rx_comp_q1 : rx_comp_q;
427 cppi_info->bd_intr_ctrl = 1;
429 if (cppi41_init_done)
430 return 0;
432 blknum = cppi_info->dma_block;
434 /* Queue manager information */
435 cppi41_queue_mgr[0].num_queue = 159;
436 cppi41_queue_mgr[0].queue_types = CPPI41_FREE_DESC_BUF_QUEUE |
437 CPPI41_UNASSIGNED_QUEUE;
438 cppi41_queue_mgr[0].base_fdbq_num = 0;
439 cppi41_queue_mgr[0].assigned = assigned_queues;
441 /* init DMA block */
442 cppi41_dma_block[0].num_tx_ch = 30;
443 cppi41_dma_block[0].num_rx_ch = 30;
444 cppi41_dma_block[0].tx_ch_info = tx_ch_info;
446 /* initilize cppi41 dma & Qmgr address */
447 cppi41_dma_base = ioremap(TI81XX_USB_CPPIDMA_BASE,
448 TI81XX_USB_CPPIDMA_LEN);
450 cppi41_queue_mgr[0].q_mgr_rgn_base = CPPI41_ADDR(QMGR_RGN_OFFS);
451 cppi41_queue_mgr[0].desc_mem_rgn_base = CPPI41_ADDR(QMRG_DESCRGN_OFFS);
452 cppi41_queue_mgr[0].q_mgmt_rgn_base = CPPI41_ADDR(QMGR_REG_OFFS);
453 cppi41_queue_mgr[0].q_stat_rgn_base = CPPI41_ADDR(QMGR_STAT_OFFS);
454 cppi41_dma_block[0].global_ctrl_base = CPPI41_ADDR(DMA_GLBCTRL_OFFS);
455 cppi41_dma_block[0].ch_ctrl_stat_base = CPPI41_ADDR(DMA_CHCTRL_OFFS);
456 cppi41_dma_block[0].sched_ctrl_base = CPPI41_ADDR(DMA_SCHED_OFFS);
457 cppi41_dma_block[0].sched_table_base = CPPI41_ADDR(DMA_SCHEDTBL_OFFS);
459 /* Initialize for Linking RAM region 0 alone */
460 cppi41_queue_mgr_init(cppi_info->q_mgr, 0, 0x3fff);
462 numch = USB_CPPI41_NUM_CH * 2 * num_instances;
463 cppi41_dma_block[0].num_max_ch = numch;
465 order = get_count_order(numch);
467 /* TODO: check two teardown desc per channel (5 or 7 ?)*/
468 if (order < 5)
469 order = 5;
471 cppi41_dma_block_init(blknum, cppi_info->q_mgr, order,
472 dma_sched_table, numch);
474 /* attach to the IRQ */
475 if (request_irq(irq, cppi41dma_Interrupt, 0, "cppi41_dma", 0))
476 printk(KERN_INFO "request_irq %d failed!\n", irq);
477 else
478 printk(KERN_INFO "registerd cppi-dma Intr @ IRQ %d\n", irq);
480 cppi41_init_done = 1;
482 printk(KERN_INFO "Cppi41 Init Done Qmgr-base(%p) dma-base(%p)\n",
483 cppi41_queue_mgr[0].q_mgr_rgn_base,
484 cppi41_dma_block[0].global_ctrl_base);
486 /* enable all usbss the interrupts */
487 usbss_write(USBSS_IRQ_EOI, 0);
488 usbss_write(USBSS_IRQ_ENABLE_SET, USBSS_INTR_FLAGS);
489 usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0xFFFeFFFe);
491 printk(KERN_INFO "Cppi41 Init Done\n");
493 return 0;
494 }
496 void cppi41_free(void)
497 {
498 u32 numch, blknum, order;
499 struct usb_cppi41_info *cppi_info = &usb_cppi41_info[0];
501 if (!cppi41_init_done)
502 return ;
504 numch = cppi41_dma_block[0].num_max_ch;
505 order = get_count_order(numch);
506 blknum = cppi_info->dma_block;
508 cppi41_dma_block_uninit(blknum, cppi_info->q_mgr, order,
509 dma_sched_table, numch);
510 cppi41_queue_mgr_uninit(cppi_info->q_mgr);
512 iounmap(cppi41_dma_base);
513 cppi41_dma_base = 0;
514 cppi41_init_done = 0;
515 }
517 int cppi41_disable_sched_rx(void)
518 {
519 cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
520 return 0;
521 }
523 int cppi41_enable_sched_rx(void)
524 {
525 cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
526 return 0;
527 }
528 #endif /* CONFIG_USB_TI_CPPI41_DMA */
530 /*
531 * Because we don't set CTRL.UINT, it's "important" to:
532 * - not read/write INTRUSB/INTRUSBE (except during
533 * initial setup, as a workaround);
534 * - use INTSET/INTCLR instead.
535 */
537 /**
538 * ti81xx_musb_enable - enable interrupts
539 */
540 void ti81xx_musb_enable(struct musb *musb)
541 {
542 void __iomem *reg_base = musb->ctrl_base;
543 u32 epmask, coremask;
545 /* Workaround: setup IRQs through both register sets. */
546 epmask = ((musb->epmask & USB_TX_EP_MASK) << USB_INTR_TX_SHIFT) |
547 ((musb->epmask & USB_RX_EP_MASK) << USB_INTR_RX_SHIFT);
548 coremask = (0x01ff << USB_INTR_USB_SHIFT);
550 coremask &= ~MUSB_INTR_SOF;
552 musb_writel(reg_base, USB_EP_INTR_SET_REG, epmask);
553 musb_writel(reg_base, USB_CORE_INTR_SET_REG, coremask);
554 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
555 if (is_otg_enabled(musb))
556 musb_writel(reg_base, USB_CORE_INTR_SET_REG,
557 USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT);
558 }
560 /**
561 * ti81xx_musb_disable - disable HDRC and flush interrupts
562 */
563 void ti81xx_musb_disable(struct musb *musb)
564 {
565 void __iomem *reg_base = musb->ctrl_base;
567 musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, USB_INTR_USB_MASK);
568 musb_writel(reg_base, USB_EP_INTR_CLEAR_REG,
569 USB_TX_INTR_MASK | USB_RX_INTR_MASK);
570 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
571 musb_writel(reg_base, USB_IRQ_EOI, 0);
572 }
574 #define POLL_SECONDS 2
576 static void otg_timer(unsigned long _musb)
577 {
578 struct musb *musb = (void *)_musb;
579 void __iomem *mregs = musb->mregs;
580 u8 devctl;
581 unsigned long flags;
583 /* We poll because DaVinci's won't expose several OTG-critical
584 * status change events (from the transceiver) otherwise.
585 */
586 devctl = musb_readb(mregs, MUSB_DEVCTL);
587 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
588 otg_state_string(musb->xceiv->state));
590 spin_lock_irqsave(&musb->lock, flags);
591 switch (musb->xceiv->state) {
592 case OTG_STATE_A_WAIT_BCON:
593 devctl &= ~MUSB_DEVCTL_SESSION;
594 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
596 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
597 if (devctl & MUSB_DEVCTL_BDEVICE) {
598 musb->xceiv->state = OTG_STATE_B_IDLE;
599 MUSB_DEV_MODE(musb);
600 } else {
601 musb->xceiv->state = OTG_STATE_A_IDLE;
602 MUSB_HST_MODE(musb);
603 }
604 break;
605 case OTG_STATE_A_WAIT_VFALL:
606 /*
607 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
608 * RTL seems to mis-handle session "start" otherwise (or in
609 * our case "recover"), in routine "VBUS was valid by the time
610 * VBUSERR got reported during enumeration" cases.
611 */
612 if (devctl & MUSB_DEVCTL_VBUS) {
613 mod_timer(&musb->otg_workaround,
614 jiffies + POLL_SECONDS * HZ);
615 break;
616 }
617 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
618 musb_writel(musb->ctrl_base, USB_CORE_INTR_SET_REG,
619 MUSB_INTR_VBUSERROR << USB_INTR_USB_SHIFT);
620 break;
621 case OTG_STATE_B_IDLE:
622 if (!is_peripheral_enabled(musb))
623 break;
625 /*
626 * There's no ID-changed IRQ, so we have no good way to tell
627 * when to switch to the A-Default state machine (by setting
628 * the DEVCTL.SESSION flag).
629 *
630 * Workaround: whenever we're in B_IDLE, try setting the
631 * session flag every few seconds. If it works, ID was
632 * grounded and we're now in the A-Default state machine.
633 *
634 * NOTE: setting the session flag is _supposed_ to trigger
635 * SRP but clearly it doesn't.
636 */
637 devctl = musb_readb(mregs, MUSB_DEVCTL);
638 if (devctl & MUSB_DEVCTL_BDEVICE)
639 mod_timer(&musb->otg_workaround,
640 jiffies + POLL_SECONDS * HZ);
641 else
642 musb->xceiv->state = OTG_STATE_A_IDLE;
643 break;
644 default:
645 break;
646 }
647 spin_unlock_irqrestore(&musb->lock, flags);
648 }
650 void ti81xx_musb_try_idle(struct musb *musb, unsigned long timeout)
651 {
652 if (!is_otg_enabled(musb))
653 return;
655 if (timeout == 0)
656 timeout = jiffies + msecs_to_jiffies(3);
658 /* Never idle if active, or when VBUS timeout is not set as host */
659 if (musb->is_active || (musb->a_wait_bcon == 0 &&
660 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
661 dev_dbg(musb->controller, "%s active, deleting timer\n",
662 otg_state_string(musb->xceiv->state));
663 del_timer(&musb->otg_workaround);
664 musb->last_timer = jiffies;
665 return;
666 }
668 if (time_after(musb->last_timer, timeout) &&
669 timer_pending(&musb->otg_workaround)) {
670 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
671 return;
672 }
673 musb->last_timer = timeout;
675 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
676 otg_state_string(musb->xceiv->state),
677 jiffies_to_msecs(timeout - jiffies));
678 mod_timer(&musb->otg_workaround, timeout);
679 }
681 #ifdef CONFIG_USB_TI_CPPI41_DMA
682 static irqreturn_t cppi41dma_Interrupt(int irq, void *hci)
683 {
684 struct musb *musb = hci;
685 u32 intr_status;
686 irqreturn_t ret = IRQ_NONE;
687 u32 q_cmpl_status_0, q_cmpl_status_1, q_cmpl_status_2;
688 u32 usb0_tx_intr, usb0_rx_intr;
689 u32 usb1_tx_intr, usb1_rx_intr;
690 void *q_mgr_base = cppi41_queue_mgr[0].q_mgr_rgn_base;
691 unsigned long flags;
693 musb = hci;
694 /*
695 * CPPI 4.1 interrupts share the same IRQ and the EOI register but
696 * don't get reflected in the interrupt source/mask registers.
697 */
698 /*
699 * Check for the interrupts from Tx/Rx completion queues; they
700 * are level-triggered and will stay asserted until the queues
701 * are emptied. We're using the queue pending register 0 as a
702 * substitute for the interrupt status register and reading it
703 * directly for speed.
704 */
705 intr_status = usbss_read(USBSS_IRQ_STATUS);
707 if (intr_status)
708 usbss_write(USBSS_IRQ_STATUS, intr_status);
709 else
710 printk(KERN_DEBUG "spurious usbss intr\n");
712 q_cmpl_status_0 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG2);
713 q_cmpl_status_1 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG3);
714 q_cmpl_status_2 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG4);
716 /* USB0 tx/rx completion */
717 /* usb0 tx completion interrupt for ep1..15 */
718 usb0_tx_intr = (q_cmpl_status_0 >> 29) |
719 ((q_cmpl_status_1 & 0xFFF) << 3);
720 usb0_rx_intr = ((q_cmpl_status_1 & 0x07FFe000) >> 13);
722 usb1_tx_intr = (q_cmpl_status_1 >> 29) |
723 ((q_cmpl_status_2 & 0xFFF) << 3);
724 usb1_rx_intr = ((q_cmpl_status_2 & 0x0fffe000) >> 13);
726 /* get proper musb handle based usb0/usb1 ctrl-id */
728 dev_dbg(musb->controller, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", usb0_tx_intr,
729 usb0_rx_intr);
730 if (gmusb[0] && (usb0_tx_intr || usb0_rx_intr)) {
731 spin_lock_irqsave(&gmusb[0]->lock, flags);
732 cppi41_completion(gmusb[0], usb0_rx_intr,
733 usb0_tx_intr);
734 spin_unlock_irqrestore(&gmusb[0]->lock, flags);
735 ret = IRQ_HANDLED;
736 }
738 dev_dbg(musb->controller, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", usb1_tx_intr,
739 usb1_rx_intr);
740 if (gmusb[1] && (usb1_rx_intr || usb1_tx_intr)) {
741 spin_lock_irqsave(&gmusb[1]->lock, flags);
742 cppi41_completion(gmusb[1], usb1_rx_intr,
743 usb1_tx_intr);
744 spin_unlock_irqrestore(&gmusb[1]->lock, flags);
745 ret = IRQ_HANDLED;
746 }
747 usbss_write(USBSS_IRQ_EOI, 0);
749 return ret;
750 }
751 #endif
753 int musb_simulate_babble(struct musb *musb)
754 {
755 void __iomem *reg_base = musb->ctrl_base;
756 void __iomem *mbase = musb->mregs;
757 u8 reg;
759 /* during babble condition musb controller
760 * remove the session
761 */
762 reg = musb_readb(mbase, MUSB_DEVCTL);
763 reg &= ~MUSB_DEVCTL_SESSION;
764 musb_writeb(mbase, MUSB_DEVCTL, reg);
765 mdelay(100);
767 /* generate s/w babble interrupt */
768 musb_writel(reg_base, USB_IRQ_STATUS_RAW_1,
769 MUSB_INTR_BABBLE);
770 return 0;
771 }
772 EXPORT_SYMBOL(musb_simulate_babble);
774 void musb_babble_workaround(struct musb *musb)
775 {
776 void __iomem *reg_base = musb->ctrl_base;
777 struct device *dev = musb->controller;
778 struct musb_hdrc_platform_data *plat = dev->platform_data;
779 struct omap_musb_board_data *data = plat->board_data;
781 /* Reset the controller */
782 musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
783 udelay(100);
785 /* Shutdown the on-chip PHY and its PLL. */
786 if (data->set_phy_power)
787 data->set_phy_power(0);
788 udelay(100);
790 musb_platform_set_mode(musb, MUSB_HOST);
791 udelay(100);
793 /* enable the usbphy */
794 if (data->set_phy_power)
795 data->set_phy_power(1);
796 mdelay(100);
798 /* save the usbotgss register contents */
799 musb_platform_enable(musb);
801 musb_start(musb);
802 }
804 static void evm_deferred_musb_restart(struct work_struct *work)
805 {
806 struct musb *musb =
807 container_of(work, struct musb, work);
809 ERR("deferred musb restart musbid(%d)\n", musb->id);
810 musb_babble_workaround(musb);
811 }
813 static irqreturn_t ti81xx_interrupt(int irq, void *hci)
814 {
815 struct musb *musb = hci;
816 void __iomem *reg_base = musb->ctrl_base;
817 unsigned long flags;
818 irqreturn_t ret = IRQ_NONE;
819 u32 pend1 = 0, pend2 = 0;
820 u32 epintr, usbintr;
821 u8 is_babble = 0;
823 spin_lock_irqsave(&musb->lock, flags);
825 /* Acknowledge and handle non-CPPI interrupts */
826 /* Get endpoint interrupts */
827 epintr = musb_readl(reg_base, USB_EP_INTR_STATUS_REG);
828 musb->int_rx = (epintr & USB_RX_INTR_MASK) >> USB_INTR_RX_SHIFT;
829 musb->int_tx = (epintr & USB_TX_INTR_MASK) >> USB_INTR_TX_SHIFT;
830 if (epintr)
831 musb_writel(reg_base, USB_EP_INTR_STATUS_REG, epintr);
833 /* Get usb core interrupts */
834 usbintr = musb_readl(reg_base, USB_CORE_INTR_STATUS_REG);
835 if (!usbintr && !epintr) {
836 dev_dbg(musb->controller, "sprious interrupt\n");
837 goto eoi;
838 }
840 if (usbintr)
841 musb_writel(reg_base, USB_CORE_INTR_STATUS_REG, usbintr);
842 musb->int_usb = (usbintr & USB_INTR_USB_MASK) >> USB_INTR_USB_SHIFT;
844 dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", usbintr, epintr);
845 /*
846 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
847 * AM3517's missing ID change IRQ. We need an ID change IRQ to
848 * switch appropriately between halves of the OTG state machine.
849 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
850 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
851 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
852 */
853 if ((usbintr & MUSB_INTR_BABBLE) && is_otg_enabled(musb)
854 && (musb->xceiv->state == OTG_STATE_A_HOST))
855 is_babble = 1;
856 else if ((usbintr & MUSB_INTR_BABBLE) && !is_otg_enabled(musb)
857 && is_host_enabled(musb))
858 is_babble = 1;
860 if (is_babble) {
861 if (musb->enable_babble_work)
862 musb->int_usb |= MUSB_INTR_DISCONNECT;
864 ERR("CAUTION: musb%d: Babble Interrupt Occured\n", musb->id);
865 ERR("Please issue long reset to make usb functional !!\n");
866 }
868 if (usbintr & (USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT)) {
869 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
870 void __iomem *mregs = musb->mregs;
871 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
872 int err;
874 err = is_host_enabled(musb) && (musb->int_usb &
875 MUSB_INTR_VBUSERROR);
876 if (err) {
877 /*
878 * The Mentor core doesn't debounce VBUS as needed
879 * to cope with device connect current spikes. This
880 * means it's not uncommon for bus-powered devices
881 * to get VBUS errors during enumeration.
882 *
883 * This is a workaround, but newer RTL from Mentor
884 * seems to allow a better one: "re"-starting sessions
885 * without waiting for VBUS to stop registering in
886 * devctl.
887 */
888 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
889 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
890 mod_timer(&musb->otg_workaround,
891 jiffies + POLL_SECONDS * HZ);
892 WARNING("VBUS error workaround (delay coming)\n");
893 } else if (is_host_enabled(musb) && drvvbus) {
894 musb->is_active = 1;
895 MUSB_HST_MODE(musb);
896 musb->xceiv->default_a = 1;
897 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
898 del_timer(&musb->otg_workaround);
899 } else {
900 musb->is_active = 0;
901 MUSB_DEV_MODE(musb);
902 musb->xceiv->default_a = 0;
903 musb->xceiv->state = OTG_STATE_B_IDLE;
904 }
906 /* NOTE: this must complete power-on within 100 ms. */
907 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
908 drvvbus ? "on" : "off",
909 otg_state_string(musb->xceiv->state),
910 err ? " ERROR" : "",
911 devctl);
912 ret = IRQ_HANDLED;
913 }
915 if (musb->int_tx || musb->int_rx || musb->int_usb)
916 ret |= musb_interrupt(musb);
918 eoi:
919 /* EOI needs to be written for the IRQ to be re-asserted. */
920 if (ret == IRQ_HANDLED || epintr || usbintr) {
921 /* write EOI */
922 musb_writel(reg_base, USB_IRQ_EOI, 1);
923 }
925 /* Poll for ID change */
926 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
927 mod_timer(&musb->otg_workaround, jiffies + POLL_SECONDS * HZ);
929 spin_unlock_irqrestore(&musb->lock, flags);
931 if (ret != IRQ_HANDLED) {
932 if (epintr || usbintr)
933 /*
934 * We sometimes get unhandled IRQs in the peripheral
935 * mode from EP0 and SOF...
936 */
937 dev_dbg(musb->controller, "Unhandled USB IRQ %08x-%08x\n",
938 epintr, usbintr);
939 else if (printk_ratelimit())
940 /*
941 * We've seen series of spurious interrupts in the
942 * peripheral mode after USB reset and then after some
943 * time a real interrupt storm starting...
944 */
945 dev_dbg(musb->controller, "Spurious IRQ, CPPI 4.1 status %08x, %08x\n",
946 pend1, pend2);
947 }
949 if (is_babble) {
950 if (!musb->enable_babble_work) {
951 musb_writeb(musb->mregs, MUSB_DEVCTL,
952 musb_readb(musb->mregs, MUSB_DEVCTL) |
953 MUSB_DEVCTL_SESSION);
954 } else {
955 ERR("Babble: devtcl(%x)Restarting musb....\n",
956 musb_readb(musb->mregs, MUSB_DEVCTL));
957 schedule_work(&musb->work);
958 }
959 }
960 return ret;
961 }
962 int ti81xx_musb_set_mode(struct musb *musb, u8 musb_mode)
963 {
964 void __iomem *reg_base = musb->ctrl_base;
965 u32 regval;
967 /* TODO: implement this using CONF0 */
968 if (musb_mode == MUSB_HOST) {
969 regval = musb_readl(reg_base, USB_MODE_REG);
971 regval &= ~USBMODE_USBID_HIGH;
972 if (usbid_sw_ctrl && cpu_is_ti816x())
973 regval |= USBMODE_USBID_MUXSEL;
975 musb_writel(reg_base, USB_MODE_REG, regval);
976 musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
977 dev_dbg(musb->controller, "host: value of mode reg=%x regval(%x)\n",
978 musb_readl(reg_base, USB_MODE_REG), regval);
979 } else if (musb_mode == MUSB_PERIPHERAL) {
980 /* TODO commmented writing 8 to USB_MODE_REG device
981 mode is not working */
982 regval = musb_readl(reg_base, USB_MODE_REG);
984 regval |= USBMODE_USBID_HIGH;
985 if (usbid_sw_ctrl && cpu_is_ti816x())
986 regval |= USBMODE_USBID_MUXSEL;
988 musb_writel(reg_base, USB_MODE_REG, regval);
989 dev_dbg(musb->controller, "device: value of mode reg=%x regval(%x)\n",
990 musb_readl(reg_base, USB_MODE_REG), regval);
991 } else if (musb_mode == MUSB_OTG) {
992 musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
993 } else
994 return -EIO;
996 return 0;
997 }
999 int ti81xx_musb_init(struct musb *musb)
1000 {
1001 void __iomem *reg_base = musb->ctrl_base;
1002 struct device *dev = musb->controller;
1003 struct musb_hdrc_platform_data *plat = dev->platform_data;
1004 struct omap_musb_board_data *data = plat->board_data;
1005 u32 rev, status = 0;
1006 u8 mode;
1008 if (musb->id < 2)
1009 gmusb[musb->id] = musb;
1011 usb_nop_xceiv_register(musb->id);
1013 musb->xceiv = otg_get_transceiver(musb->id);
1014 if (!musb->xceiv)
1015 return -ENODEV;
1017 status = pm_runtime_get_sync(dev);
1018 if (status < 0) {
1019 dev_err(dev, "pm_runtime_get_sync FAILED");
1020 goto err1;
1021 }
1023 /* mentor is at offset of 0x400 in am3517/ti81xx */
1024 musb->mregs += USB_MENTOR_CORE_OFFSET;
1027 /* Returns zero if e.g. not clocked */
1028 rev = musb_readl(reg_base, USB_REVISION_REG);
1029 if (!rev)
1030 return -ENODEV;
1032 if (is_host_enabled(musb))
1033 setup_timer(&musb->otg_workaround, otg_timer,
1034 (unsigned long) musb);
1036 /* Reset the controller */
1037 musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
1039 /* wait till reset bit clears */
1040 while ((musb_readl(reg_base, USB_CTRL_REG) & 0x1))
1041 cpu_relax();
1043 /* Start the on-chip PHY and its PLL. */
1044 if (data->set_phy_power)
1045 data->set_phy_power(1);
1047 musb->a_wait_bcon = A_WAIT_BCON_TIMEOUT;
1048 musb->isr = ti81xx_interrupt;
1050 if (cpu_is_ti816x())
1051 usbid_sw_ctrl = 1;
1053 if (is_otg_enabled(musb)) {
1054 /* if usb-id contolled through software for ti816x then
1055 * configure the usb0 in peripheral mode and usb1 in
1056 * host mode
1057 */
1058 if (usbid_sw_ctrl && cpu_is_ti816x())
1059 mode = musb->id ? MUSB_HOST : MUSB_PERIPHERAL;
1060 else
1061 mode = MUSB_OTG;
1062 } else
1063 /* set musb controller to host mode */
1064 mode = is_host_enabled(musb) ? MUSB_HOST : MUSB_PERIPHERAL;
1066 /* set musb controller to host mode */
1067 musb_platform_set_mode(musb, mode);
1069 /* enable babble workaround */
1070 INIT_WORK(&musb->work, evm_deferred_musb_restart);
1071 musb->enable_babble_work = 0;
1073 musb_writel(reg_base, USB_IRQ_EOI, 0);
1075 return 0;
1076 err1:
1077 pm_runtime_disable(dev);
1078 return status;
1079 }
1081 /* TI81xx supports only 32bit read operation */
1082 void ti81xx_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
1083 {
1084 void __iomem *fifo = hw_ep->fifo;
1085 u32 val;
1086 int i;
1088 /* Read for 32bit-aligned destination address */
1089 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
1090 readsl(fifo, dst, len >> 2);
1091 dst += len & ~0x03;
1092 len &= 0x03;
1093 }
1094 /*
1095 * Now read the remaining 1 to 3 byte or complete length if
1096 * unaligned address.
1097 */
1098 if (len > 4) {
1099 for (i = 0; i < (len >> 2); i++) {
1100 *(u32 *) dst = musb_readl(fifo, 0);
1101 dst += 4;
1102 }
1103 len &= 0x03;
1104 }
1105 if (len > 0) {
1106 val = musb_readl(fifo, 0);
1107 memcpy(dst, &val, len);
1108 }
1109 }
1111 int ti81xx_musb_exit(struct musb *musb)
1112 {
1113 struct device *dev = musb->controller;
1114 struct musb_hdrc_platform_data *plat = dev->platform_data;
1115 struct omap_musb_board_data *data = plat->board_data;
1117 if (is_host_enabled(musb))
1118 del_timer_sync(&musb->otg_workaround);
1120 /* Shutdown the on-chip PHY and its PLL. */
1121 if (data->set_phy_power)
1122 data->set_phy_power(0);
1124 otg_put_transceiver(musb->xceiv);
1125 usb_nop_xceiv_unregister(musb->id);
1127 return 0;
1128 }
1130 static struct musb_platform_ops ti81xx_ops = {
1131 .fifo_mode = 4,
1132 .flags = MUSB_GLUE_EP_ADDR_FLAT_MAPPING | MUSB_GLUE_DMA_CPPI41,
1133 .init = ti81xx_musb_init,
1134 .exit = ti81xx_musb_exit,
1136 .enable = ti81xx_musb_enable,
1137 .disable = ti81xx_musb_disable,
1139 .try_idle = ti81xx_musb_try_idle,
1140 .set_mode = ti81xx_musb_set_mode,
1142 .read_fifo = ti81xx_musb_read_fifo,
1143 .write_fifo = musb_write_fifo,
1145 .dma_controller_create = cppi41_dma_controller_create,
1146 .dma_controller_destroy = cppi41_dma_controller_destroy,
1147 .simulate_babble_intr = musb_simulate_babble,
1148 };
1150 static void __devexit ti81xx_delete_musb_pdev(struct ti81xx_glue *glue, u8 id)
1151 {
1152 platform_device_del(glue->musb[id]);
1153 platform_device_put(glue->musb[id]);
1154 }
1156 static int __devinit ti81xx_create_musb_pdev(struct ti81xx_glue *glue, u8 id)
1157 {
1158 struct device *dev = glue->dev;
1159 struct platform_device *pdev = to_platform_device(dev);
1160 struct musb_hdrc_platform_data *pdata = dev->platform_data;
1161 struct platform_device *musb;
1162 struct resource *res;
1163 struct resource resources[2];
1164 char res_name[10];
1165 int ret = 0;
1167 /* get memory resource */
1168 sprintf(res_name, "musb%d", id);
1169 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name);
1170 if (!res) {
1171 dev_err(dev, "%s get mem resource failed\n", res_name);
1172 ret = -ENODEV;
1173 goto err0;
1174 }
1175 res->parent = NULL;
1176 resources[0] = *res;
1178 /* get irq resource */
1179 sprintf(res_name, "musb%d-irq", id);
1180 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res_name);
1181 if (!res) {
1182 dev_err(dev, "%s get irq resource failed\n", res_name);
1183 ret = -ENODEV;
1184 goto err0;
1185 }
1186 res->parent = NULL;
1187 resources[1] = *res;
1189 /* allocate the child platform device */
1190 musb = platform_device_alloc("musb-hdrc", id);
1191 if (!musb) {
1192 dev_err(dev, "failed to allocate musb device\n");
1193 goto err0;
1194 }
1196 musb->id = id;
1197 musb->dev.parent = dev;
1198 musb->dev.dma_mask = &musb_dmamask;
1199 musb->dev.coherent_dma_mask = musb_dmamask;
1201 glue->musb[id] = musb;
1203 pdata->platform_ops = &ti81xx_ops;
1205 ret = platform_device_add_resources(musb, resources, 2);
1206 if (ret) {
1207 dev_err(dev, "failed to add resources\n");
1208 goto err1;
1209 }
1211 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
1212 if (ret) {
1213 dev_err(dev, "failed to add platform_data\n");
1214 goto err1;
1215 }
1217 ret = platform_device_add(musb);
1218 if (ret) {
1219 dev_err(dev, "failed to register musb device\n");
1220 goto err1;
1221 }
1223 return 0;
1225 err1:
1226 platform_device_put(musb);
1227 err0:
1228 return ret;
1229 }
1231 static int __init ti81xx_probe(struct platform_device *pdev)
1232 {
1233 struct ti81xx_glue *glue;
1234 struct device *dev = &pdev->dev;
1235 struct musb_hdrc_platform_data *plat = dev->platform_data;
1236 struct omap_musb_board_data *data = plat->board_data;
1237 int ret = 0, i;
1238 struct resource *res;
1240 /* allocate glue */
1241 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1242 if (!glue) {
1243 dev_err(&pdev->dev, "unable to allocate glue memory\n");
1244 ret = -ENOMEM;
1245 goto err0;
1246 }
1248 /* interface clock needs to be enabled for usbss register programming */
1249 glue->ick = clk_get(&pdev->dev, "usbotg_ick");
1250 if (IS_ERR(glue->ick)) {
1251 dev_err(&pdev->dev, "unable to get usbss interface clock\n");
1252 ret = PTR_ERR(glue->ick);
1253 goto err1;
1254 }
1256 /* functional clock needs to be enabled for usbss register programming */
1257 glue->fck = clk_get(&pdev->dev, "usbotg_fck");
1258 if (IS_ERR(glue->fck)) {
1259 dev_err(&pdev->dev, "unable to get usbss functional clock\n");
1260 ret = PTR_ERR(glue->fck);
1261 goto err2;
1262 }
1264 /* get memory resource */
1265 glue->mem_pa = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1266 if (!glue->mem_pa) {
1267 dev_err(&pdev->dev, "failed to get usbss mem resourse\n");
1268 ret = -ENODEV;
1269 goto err3;
1270 }
1272 /* get memory resource */
1273 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "usbss-irq");
1274 if (!res) {
1275 dev_err(&pdev->dev, "failed to get usbss irq resourse\n");
1276 ret = -ENODEV;
1277 goto err3;
1278 }
1279 glue->irq = res->start;
1281 /* enable interface clock */
1282 ret = clk_enable(glue->ick);
1283 if (ret) {
1284 dev_err(&pdev->dev, "failed to enable usbss interface clock\n");
1285 goto err3;
1286 }
1288 /* enable functional clock */
1289 ret = clk_enable(glue->fck);
1290 if (ret) {
1291 dev_err(&pdev->dev, "failed to enable usbss functional clock\n");
1292 goto err4;
1293 }
1295 /* iomap for usbss mem space */
1296 glue->mem_va =
1297 ioremap(glue->mem_pa->start, resource_size(glue->mem_pa));
1298 if (!glue->mem_va) {
1299 dev_err(&pdev->dev, "usbss ioremap failed\n");
1300 ret = -ENOMEM;
1301 goto err5;
1302 }
1303 usbss_virt_base = glue->mem_va;
1305 glue->dev = &pdev->dev;
1306 platform_set_drvdata(pdev, glue);
1308 /* usb subsystem init */
1309 usbotg_ss_init();
1311 /* clear any USBSS interrupts */
1312 __raw_writel(0, glue->mem_va + USBSS_IRQ_EOI);
1313 __raw_writel(__raw_readl(glue->mem_va + USBSS_IRQ_STATUS),
1314 glue->mem_va + USBSS_IRQ_STATUS);
1316 /* create the child platform device for mulitple instances of musb */
1317 for (i = 0; i <= data->instances; ++i) {
1318 #ifdef CONFIG_USB_TI_CPPI41_DMA
1319 /* initialize the cppi41dma init */
1320 cppi41_init(i, glue->irq, data->instances+1);
1321 #endif
1322 ret = ti81xx_create_musb_pdev(glue, i);
1323 if (ret != 0)
1324 goto err6;
1325 }
1327 return 0;
1329 err6:
1330 iounmap(glue->mem_va);
1331 err5:
1332 clk_disable(glue->fck);
1333 err4:
1334 clk_disable(glue->ick);
1335 err3:
1336 clk_put(glue->fck);
1337 err2:
1338 clk_put(glue->ick);
1339 err1:
1340 kfree(glue);
1341 err0:
1342 return ret;
1343 }
1345 static int __exit ti81xx_remove(struct platform_device *pdev)
1346 {
1347 struct ti81xx_glue *glue = platform_get_drvdata(pdev);
1348 struct device *dev = &pdev->dev;
1349 struct musb_hdrc_platform_data *plat = dev->platform_data;
1350 struct omap_musb_board_data *data = plat->board_data;
1351 int i;
1353 /* delete the child platform device for mulitple instances of musb */
1354 for (i = 0; i <= data->instances; ++i)
1355 ti81xx_delete_musb_pdev(glue, i);
1357 #ifdef CONFIG_USB_TI_CPPI41_DMA
1358 cppi41_free();
1359 #endif
1360 /* iounmap */
1361 iounmap(glue->mem_va);
1362 usbotg_ss_uninit();
1364 /* disable common usbss functional clock */
1365 clk_disable(glue->fck);
1366 clk_put(glue->fck);
1367 /* disable common usbss interface clock */
1368 clk_disable(glue->ick);
1369 clk_put(glue->ick);
1370 kfree(glue);
1372 return 0;
1373 }
1375 #ifdef CONFIG_PM
1376 static int ti81xx_suspend(struct device *dev)
1377 {
1378 struct ti81xx_glue *glue = dev_get_drvdata(dev);
1379 struct musb_hdrc_platform_data *plat = dev->platform_data;
1380 struct omap_musb_board_data *data = plat->board_data;
1381 int i;
1383 /* Shutdown the on-chip PHY and its PLL. */
1384 for (i = 0; i <= data->instances; ++i) {
1385 if (data->set_phy_power)
1386 data->set_phy_power(i);
1387 }
1389 /* disable the common usbss functional clock */
1390 clk_disable(glue->fck);
1391 /* disable the common usbss interface clock */
1392 clk_disable(glue->ick);
1393 return 0;
1394 }
1396 static int ti81xx_resume(struct device *dev)
1397 {
1398 struct ti81xx_glue *glue = dev_get_drvdata(dev);
1399 struct musb_hdrc_platform_data *plat = dev->platform_data;
1400 struct omap_musb_board_data *data = plat->board_data;
1401 int ret, i;
1403 /* Start the on-chip PHY and its PLL. */
1404 for (i = 0; i <= data->instances; ++i) {
1405 if (data->set_phy_power)
1406 data->set_phy_power(i);
1407 }
1409 /* enable the common usbss interface clock */
1410 ret = clk_enable(glue->ick);
1411 if (ret) {
1412 dev_err(dev, "failed to enable iclock\n");
1413 return ret;
1414 }
1415 /* enable the common usbss functional clock */
1416 ret = clk_enable(glue->fck);
1417 if (ret) {
1418 dev_err(dev, "failed to enable fclock\n");
1419 return ret;
1420 }
1421 return 0;
1422 }
1424 static const struct dev_pm_ops ti81xx_pm_ops = {
1425 .suspend = ti81xx_suspend,
1426 .resume = ti81xx_resume,
1427 };
1429 #define DEV_PM_OPS (&ti81xx_pm_ops)
1430 #else
1431 #define DEV_PM_OPS NULL
1432 #endif
1434 static struct platform_driver ti81xx_musb_driver = {
1435 .remove = __exit_p(ti81xx_remove),
1436 .driver = {
1437 .name = "musb-ti81xx",
1438 .pm = DEV_PM_OPS,
1439 },
1440 };
1442 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1443 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
1444 MODULE_LICENSE("GPL v2");
1446 static int __init ti81xx_glue_init(void)
1447 {
1448 return platform_driver_probe(&ti81xx_musb_driver, ti81xx_probe);
1449 }
1450 subsys_initcall(ti81xx_glue_init);
1452 static void __exit ti81xx_glue_exit(void)
1453 {
1454 #ifdef CONFIG_USB_TI_CPPI41_DMA
1455 /* free the usbss irq */
1456 free_irq(TI81XX_IRQ_USBSS, 0);
1457 #endif
1459 /* disable the interrupts */
1460 usbss_write(USBSS_IRQ_EOI, 0);
1461 usbss_write(USBSS_IRQ_ENABLE_SET, 0);
1462 usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0);
1464 /* unregister platform driver */
1465 platform_driver_unregister(&ti81xx_musb_driver);
1466 }
1467 module_exit(ti81xx_glue_exit);
1469 #ifdef CONFIG_PM
1470 void musb_platform_save_context(struct musb *musb,
1471 struct musb_context_registers *musb_context)
1472 {
1473 /* Save CPPI41 DMA related registers */
1474 }
1476 void musb_platform_restore_context(struct musb *musb,
1477 struct musb_context_registers *musb_context)
1478 {
1479 /* Restore CPPI41 DMA related registers */
1480 }
1481 #endif