1 /*
2 * Texas Instruments TI81XX "usb platform glue layer"
3 *
4 * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * Based on the DaVinci "glue layer" code.
7 * Copyright (C) 2005-2006 by Texas Instruments
8 *
9 * This file is part of the Inventra Controller Driver for Linux.
10 *
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
14 * Foundation.
15 *
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
29 #include <linux/init.h>
30 #include <linux/clk.h>
31 #include <linux/io.h>
32 #include <linux/usb/otg.h>
33 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/module.h>
37 #include "cppi41.h"
38 #include "ti81xx.h"
40 #include "musb_core.h"
41 #include "cppi41_dma.h"
43 struct ti81xx_glue {
44 struct device *dev;
45 struct clk *ick; /* common usbss interface clk */
46 struct clk *fck; /* common usbss functional clk */
47 struct resource *mem_pa; /* usbss memory resource */
48 void *mem_va; /* ioremapped virtual address */
49 struct platform_device *musb[2];/* child musb pdevs */
50 u8 irq; /* usbss irq */
51 };
52 static u64 musb_dmamask = DMA_BIT_MASK(32);
53 static void *usbss_virt_base;
54 static u8 usbss_init_done;
55 struct musb *gmusb[2];
57 u8 usbid_sw_ctrl;
58 #undef USB_TI81XX_DEBUG
60 #ifdef USB_TI81XX_DEBUG
61 #define dprintk(x, ...) printk(x, ## __VA_ARGS__)
62 #else
63 #define dprintk(x, ...)
64 #endif
66 #ifdef CONFIG_USB_TI_CPPI41_DMA
67 static irqreturn_t cppi41dma_Interrupt(int irq, void *hci);
68 static u8 cppi41_init_done;
69 static void *cppi41_dma_base;
70 #define CPPI41_ADDR(offs) ((void *)((u32)cppi41_dma_base + (offs - 0x2000)))
71 #endif
73 extern void omap_ctrl_writel(u32 val, u16 offset);
74 extern u32 omap_ctrl_readl(u16 offset);
76 static inline u32 usbss_read(u32 offset)
77 {
78 if (!usbss_init_done)
79 return 0;
80 return __raw_readl(usbss_virt_base + offset);
81 }
83 static inline void usbss_write(u32 offset, u32 data)
84 {
85 if (!usbss_init_done)
86 return ;
87 __raw_writel(data, usbss_virt_base + offset);
88 }
90 static void usbotg_ss_init(void)
91 {
92 if (!usbss_init_done) {
93 /* reset the usbss for usb0/usb1 */
94 usbss_write(USBSS_SYSCONFIG,
95 usbss_read(USBSS_SYSCONFIG) | USB_SOFT_RESET_MASK);
97 /* clear any USBSS interrupts */
98 usbss_write(USBSS_IRQ_EOI, 0);
99 usbss_write(USBSS_IRQ_STATUS, usbss_read(USBSS_IRQ_STATUS));
100 usbss_init_done = 1;
101 }
102 }
103 static void usbotg_ss_uninit(void)
104 {
105 if (usbss_init_done) {
106 usbss_init_done = 0;
107 usbss_virt_base = 0;
108 }
109 }
110 void set_frame_threshold(struct musb *musb, u8 is_tx, u8 epnum, u8 value, u8 en_intr)
111 {
112 u32 base, reg_val, frame_intr = 0, frame_base = 0;
113 u32 offs = epnum/4*4;
114 u8 indx = (epnum % 4) * 8;
116 if (is_tx)
117 base = musb->id ? USBSS_IRQ_FRAME_THRESHOLD_TX1 :
118 USBSS_IRQ_FRAME_THRESHOLD_TX0;
119 else
120 base = musb->id ? USBSS_IRQ_FRAME_THRESHOLD_RX1 :
121 USBSS_IRQ_FRAME_THRESHOLD_RX0;
123 reg_val = usbss_read(base + offs);
124 reg_val &= ~(0xFF << indx);
125 reg_val |= (value << indx);
126 usbss_write(base + offs, reg_val);
128 if (en_intr) {
129 frame_base = musb->id ? USBSS_IRQ_FRAME_ENABLE_1 :
130 USBSS_IRQ_FRAME_ENABLE_0;
131 frame_intr = musb->id ? usbss_read(USBSS_IRQ_FRAME_ENABLE_0) :
132 usbss_read(USBSS_IRQ_FRAME_ENABLE_1);
133 frame_intr |= is_tx ? (1 << epnum) : (1 << (16 + epnum));
134 usbss_write(frame_base, frame_intr);
135 dev_dbg(musb->controller, "%s: framebase=%x, frame_intr=%x\n",
136 is_tx ? "tx" : "rx", frame_base, frame_intr);
137 }
138 }
140 void set_dma_threshold(struct musb *musb, u8 is_tx, u8 epnum, u8 value)
141 {
142 u32 base, reg_val;
143 u32 offs = epnum/4*4;
144 u8 indx = (epnum % 4) * 8;
146 if (musb->id == 0)
147 base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX0 :
148 USBSS_IRQ_DMA_THRESHOLD_RX0;
149 else
150 base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX1 :
151 USBSS_IRQ_DMA_THRESHOLD_RX1;
153 reg_val = usbss_read(base + offs);
154 reg_val &= ~(0xFF << indx);
155 reg_val |= (value << indx);
156 dev_dbg(musb->controller, "base=%x, offs=%x, indx=%d, reg_val = (%x)%x\n",
157 base, offs, indx, reg_val, usbss_read(base + offs));
158 usbss_write(base + offs, reg_val);
159 }
161 /* ti81xx specific read/write functions */
162 u16 ti81xx_musb_readw(const void __iomem *addr, unsigned offset)
163 {
164 u32 tmp;
165 u16 val;
167 tmp = __raw_readl(addr + (offset & ~3));
169 switch (offset & 0x3) {
170 case 0:
171 val = (tmp & 0xffff);
172 break;
173 case 1:
174 val = (tmp >> 8) & 0xffff;
175 break;
176 case 2:
177 case 3:
178 default:
179 val = (tmp >> 16) & 0xffff;
180 break;
181 }
182 return val;
183 }
185 void ti81xx_musb_writew(void __iomem *addr, unsigned offset, u16 data)
186 {
187 __raw_writew(data, addr + offset);
188 }
190 u8 ti81xx_musb_readb(const void __iomem *addr, unsigned offset)
191 {
192 u32 tmp;
193 u8 val;
195 tmp = __raw_readl(addr + (offset & ~3));
197 switch (offset & 0x3) {
198 case 0:
199 val = tmp & 0xff;
200 break;
201 case 1:
202 val = (tmp >> 8);
203 break;
204 case 2:
205 val = (tmp >> 16);
206 break;
207 case 3:
208 default:
209 val = (tmp >> 24);
210 break;
211 }
212 return val;
213 }
214 void ti81xx_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
215 {
216 __raw_writeb(data, addr + offset);
217 }
219 #ifdef CONFIG_USB_TI_CPPI41_DMA
220 /*
221 * CPPI 4.1 resources used for USB OTG controller module:
222 *
223 tx/rx completion queues for usb0 */
224 static u16 tx_comp_q[] = {93, 94, 95, 96, 97,
225 98, 99, 100, 101, 102,
226 103, 104, 105, 106, 107 };
228 static u16 rx_comp_q[] = {109, 110, 111, 112, 113,
229 114, 115, 116, 117, 118,
230 119, 120, 121, 122, 123 };
232 /* tx/rx completion queues for usb1 */
233 static u16 tx_comp_q1[] = {125, 126, 127, 128, 129,
234 130, 131, 132, 133, 134,
235 135, 136, 137, 138, 139 };
237 static u16 rx_comp_q1[] = {141, 142, 143, 144, 145,
238 146, 147, 148, 149, 150,
239 151, 152, 153, 154, 155 };
241 /* Fair scheduling */
242 u32 dma_sched_table[] = {
243 0x81018000, 0x83038202, 0x85058404, 0x87078606,
244 0x89098808, 0x8b0b8a0a, 0x8d0d8c0c, 0x8f0f8e0e,
245 0x91119010, 0x93139212, 0x95159414, 0x97179616,
246 0x99199818, 0x9b1b9a1a, 0x9d1d9c1c, 0x00009e1e,
247 };
249 /* cppi41 dma tx channel info */
250 static const struct cppi41_tx_ch tx_ch_info[] = {
251 [0] = {
252 .port_num = 1,
253 .num_tx_queue = 2,
254 .tx_queue = { {0, 32} , {0, 33} }
255 },
256 [1] = {
257 .port_num = 2,
258 .num_tx_queue = 2,
259 .tx_queue = { {0, 34} , {0, 35} }
260 },
261 [2] = {
262 .port_num = 3,
263 .num_tx_queue = 2,
264 .tx_queue = { {0, 36} , {0, 37} }
265 },
266 [3] = {
267 .port_num = 4,
268 .num_tx_queue = 2,
269 .tx_queue = { {0, 38} , {0, 39} }
270 },
271 [4] = {
272 .port_num = 5,
273 .num_tx_queue = 2,
274 .tx_queue = { {0, 40} , {0, 41} }
275 },
276 [5] = {
277 .port_num = 6,
278 .num_tx_queue = 2,
279 .tx_queue = { {0, 42} , {0, 43} }
280 },
281 [6] = {
282 .port_num = 7,
283 .num_tx_queue = 2,
284 .tx_queue = { {0, 44} , {0, 45} }
285 },
286 [7] = {
287 .port_num = 8,
288 .num_tx_queue = 2,
289 .tx_queue = { {0, 46} , {0, 47} }
290 },
291 [8] = {
292 .port_num = 9,
293 .num_tx_queue = 2,
294 .tx_queue = { {0, 48} , {0, 49} }
295 },
296 [9] = {
297 .port_num = 10,
298 .num_tx_queue = 2,
299 .tx_queue = { {0, 50} , {0, 51} }
300 },
301 [10] = {
302 .port_num = 11,
303 .num_tx_queue = 2,
304 .tx_queue = { {0, 52} , {0, 53} }
305 },
306 [11] = {
307 .port_num = 12,
308 .num_tx_queue = 2,
309 .tx_queue = { {0, 54} , {0, 55} }
310 },
311 [12] = {
312 .port_num = 13,
313 .num_tx_queue = 2,
314 .tx_queue = { {0, 56} , {0, 57} }
315 },
316 [13] = {
317 .port_num = 14,
318 .num_tx_queue = 2,
319 .tx_queue = { {0, 58} , {0, 59} }
320 },
321 [14] = {
322 .port_num = 15,
323 .num_tx_queue = 2,
324 .tx_queue = { {0, 60} , {0, 61} }
325 },
326 [15] = {
327 .port_num = 1,
328 .num_tx_queue = 2,
329 .tx_queue = { {0, 62} , {0, 63} }
330 },
331 [16] = {
332 .port_num = 2,
333 .num_tx_queue = 2,
334 .tx_queue = { {0, 64} , {0, 65} }
335 },
336 [17] = {
337 .port_num = 3,
338 .num_tx_queue = 2,
339 .tx_queue = { {0, 66} , {0, 67} }
340 },
341 [18] = {
342 .port_num = 4,
343 .num_tx_queue = 2,
344 .tx_queue = { {0, 68} , {0, 69} }
345 },
346 [19] = {
347 .port_num = 5,
348 .num_tx_queue = 2,
349 .tx_queue = { {0, 70} , {0, 71} }
350 },
351 [20] = {
352 .port_num = 6,
353 .num_tx_queue = 2,
354 .tx_queue = { {0, 72} , {0, 73} }
355 },
356 [21] = {
357 .port_num = 7,
358 .num_tx_queue = 2,
359 .tx_queue = { {0, 74} , {0, 75} }
360 },
361 [22] = {
362 .port_num = 8,
363 .num_tx_queue = 2,
364 .tx_queue = { {0, 76} , {0, 77} }
365 },
366 [23] = {
367 .port_num = 9,
368 .num_tx_queue = 2,
369 .tx_queue = { {0, 78} , {0, 79} }
370 },
371 [24] = {
372 .port_num = 10,
373 .num_tx_queue = 2,
374 .tx_queue = { {0, 80} , {0, 81} }
375 },
376 [25] = {
377 .port_num = 11,
378 .num_tx_queue = 2,
379 .tx_queue = { {0, 82} , {0, 83} }
380 },
381 [26] = {
382 .port_num = 12,
383 .num_tx_queue = 2,
384 .tx_queue = { {0, 84} , {0, 85} }
385 },
386 [27] = {
387 .port_num = 13,
388 .num_tx_queue = 2,
389 .tx_queue = { {0, 86} , {0, 87} }
390 },
391 [28] = {
392 .port_num = 14,
393 .num_tx_queue = 2,
394 .tx_queue = { {0, 88} , {0, 89} }
395 },
396 [29] = {
397 .port_num = 15,
398 .num_tx_queue = 2,
399 .tx_queue = { {0, 90} , {0, 91} }
400 }
401 };
403 /* Queues 0 to 66 are pre-assigned, others are spare */
404 static const u32 assigned_queues[] = { 0xffffffff, /* queue 0..31 */
405 0xffffffff, /* queue 32..63 */
406 0xffffffff, /* queue 64..95 */
407 0xffffffff, /* queue 96..127 */
408 0x0fffffff /* queue 128..155 */
409 };
411 int __devinit cppi41_init(u8 id, u8 irq, int num_instances)
412 {
413 struct usb_cppi41_info *cppi_info = &usb_cppi41_info[id];
414 u16 numch, blknum, order;
415 u32 i;
417 /* init cppi info structure */
418 cppi_info->dma_block = 0;
419 for (i = 0 ; i < USB_CPPI41_NUM_CH ; i++)
420 cppi_info->ep_dma_ch[i] = i + (15 * id);
422 cppi_info->q_mgr = 0;
423 cppi_info->num_tx_comp_q = 15;
424 cppi_info->num_rx_comp_q = 15;
425 cppi_info->tx_comp_q = id ? tx_comp_q1 : tx_comp_q;
426 cppi_info->rx_comp_q = id ? rx_comp_q1 : rx_comp_q;
427 cppi_info->bd_intr_ctrl = 1;
429 if (cppi41_init_done)
430 return 0;
432 blknum = cppi_info->dma_block;
434 /* Queue manager information */
435 cppi41_queue_mgr[0].num_queue = 159;
436 cppi41_queue_mgr[0].queue_types = CPPI41_FREE_DESC_BUF_QUEUE |
437 CPPI41_UNASSIGNED_QUEUE;
438 cppi41_queue_mgr[0].base_fdbq_num = 0;
439 cppi41_queue_mgr[0].assigned = assigned_queues;
441 /* init DMA block */
442 cppi41_dma_block[0].num_tx_ch = 30;
443 cppi41_dma_block[0].num_rx_ch = 30;
444 cppi41_dma_block[0].tx_ch_info = tx_ch_info;
446 /* initilize cppi41 dma & Qmgr address */
447 cppi41_dma_base = ioremap(TI81XX_USB_CPPIDMA_BASE,
448 TI81XX_USB_CPPIDMA_LEN);
450 cppi41_queue_mgr[0].q_mgr_rgn_base = CPPI41_ADDR(QMGR_RGN_OFFS);
451 cppi41_queue_mgr[0].desc_mem_rgn_base = CPPI41_ADDR(QMRG_DESCRGN_OFFS);
452 cppi41_queue_mgr[0].q_mgmt_rgn_base = CPPI41_ADDR(QMGR_REG_OFFS);
453 cppi41_queue_mgr[0].q_stat_rgn_base = CPPI41_ADDR(QMGR_STAT_OFFS);
454 cppi41_dma_block[0].global_ctrl_base = CPPI41_ADDR(DMA_GLBCTRL_OFFS);
455 cppi41_dma_block[0].ch_ctrl_stat_base = CPPI41_ADDR(DMA_CHCTRL_OFFS);
456 cppi41_dma_block[0].sched_ctrl_base = CPPI41_ADDR(DMA_SCHED_OFFS);
457 cppi41_dma_block[0].sched_table_base = CPPI41_ADDR(DMA_SCHEDTBL_OFFS);
459 /* Initialize for Linking RAM region 0 alone */
460 cppi41_queue_mgr_init(cppi_info->q_mgr, 0, 0x3fff);
462 numch = USB_CPPI41_NUM_CH * 2 * num_instances;
463 cppi41_dma_block[0].num_max_ch = numch;
465 order = get_count_order(numch);
467 /* TODO: check two teardown desc per channel (5 or 7 ?)*/
468 if (order < 5)
469 order = 5;
471 cppi41_dma_block_init(blknum, cppi_info->q_mgr, order,
472 dma_sched_table, numch);
474 /* attach to the IRQ */
475 if (request_irq(irq, cppi41dma_Interrupt, 0, "cppi41_dma", 0))
476 printk(KERN_INFO "request_irq %d failed!\n", irq);
477 else
478 printk(KERN_INFO "registerd cppi-dma Intr @ IRQ %d\n", irq);
480 cppi41_init_done = 1;
482 printk(KERN_INFO "Cppi41 Init Done Qmgr-base(%p) dma-base(%p)\n",
483 cppi41_queue_mgr[0].q_mgr_rgn_base,
484 cppi41_dma_block[0].global_ctrl_base);
486 /* enable all usbss the interrupts */
487 usbss_write(USBSS_IRQ_EOI, 0);
488 usbss_write(USBSS_IRQ_ENABLE_SET, USBSS_INTR_FLAGS);
489 usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0xFFFeFFFe);
491 printk(KERN_INFO "Cppi41 Init Done\n");
493 return 0;
494 }
496 void cppi41_free(void)
497 {
498 u32 numch, blknum, order;
499 struct usb_cppi41_info *cppi_info = &usb_cppi41_info[0];
501 if (!cppi41_init_done)
502 return ;
504 numch = cppi41_dma_block[0].num_max_ch;
505 order = get_count_order(numch);
506 blknum = cppi_info->dma_block;
508 cppi41_dma_block_uninit(blknum, cppi_info->q_mgr, order,
509 dma_sched_table, numch);
510 cppi41_queue_mgr_uninit(cppi_info->q_mgr);
512 iounmap(cppi41_dma_base);
513 cppi41_dma_base = 0;
514 cppi41_init_done = 0;
515 }
517 int cppi41_disable_sched_rx(void)
518 {
519 cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
520 return 0;
521 }
523 int cppi41_enable_sched_rx(void)
524 {
525 cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
526 return 0;
527 }
528 #endif /* CONFIG_USB_TI_CPPI41_DMA */
530 /*
531 * Because we don't set CTRL.UINT, it's "important" to:
532 * - not read/write INTRUSB/INTRUSBE (except during
533 * initial setup, as a workaround);
534 * - use INTSET/INTCLR instead.
535 */
537 /**
538 * ti81xx_musb_enable - enable interrupts
539 */
540 void ti81xx_musb_enable(struct musb *musb)
541 {
542 void __iomem *reg_base = musb->ctrl_base;
543 u32 epmask, coremask;
545 /* Workaround: setup IRQs through both register sets. */
546 epmask = ((musb->epmask & USB_TX_EP_MASK) << USB_INTR_TX_SHIFT) |
547 ((musb->epmask & USB_RX_EP_MASK) << USB_INTR_RX_SHIFT);
548 coremask = (0x01ff << USB_INTR_USB_SHIFT);
550 coremask &= ~MUSB_INTR_SOF;
552 musb_writel(reg_base, USB_EP_INTR_SET_REG, epmask);
553 musb_writel(reg_base, USB_CORE_INTR_SET_REG, coremask);
554 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
555 if (is_otg_enabled(musb))
556 musb_writel(reg_base, USB_CORE_INTR_SET_REG,
557 USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT);
558 }
560 /**
561 * ti81xx_musb_disable - disable HDRC and flush interrupts
562 */
563 void ti81xx_musb_disable(struct musb *musb)
564 {
565 void __iomem *reg_base = musb->ctrl_base;
567 musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, USB_INTR_USB_MASK);
568 musb_writel(reg_base, USB_EP_INTR_CLEAR_REG,
569 USB_TX_INTR_MASK | USB_RX_INTR_MASK);
570 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
571 musb_writel(reg_base, USB_IRQ_EOI, 0);
572 }
574 #define POLL_SECONDS 2
576 static void otg_timer(unsigned long _musb)
577 {
578 struct musb *musb = (void *)_musb;
579 void __iomem *mregs = musb->mregs;
580 u8 devctl;
581 unsigned long flags;
583 /* We poll because DaVinci's won't expose several OTG-critical
584 * status change events (from the transceiver) otherwise.
585 */
586 devctl = musb_readb(mregs, MUSB_DEVCTL);
587 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
588 otg_state_string(musb->xceiv->state));
590 spin_lock_irqsave(&musb->lock, flags);
591 switch (musb->xceiv->state) {
592 case OTG_STATE_A_WAIT_BCON:
593 devctl &= ~MUSB_DEVCTL_SESSION;
594 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
596 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
597 if (devctl & MUSB_DEVCTL_HM) {
598 musb->xceiv->state = OTG_STATE_A_IDLE;
599 MUSB_HST_MODE(musb);
600 } else {
601 musb->xceiv->state = OTG_STATE_B_IDLE;
602 MUSB_DEV_MODE(musb);
603 mod_timer(&musb->otg_workaround,
604 jiffies + POLL_SECONDS * HZ);
605 }
606 break;
607 case OTG_STATE_A_WAIT_VFALL:
608 /*
609 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
610 * RTL seems to mis-handle session "start" otherwise (or in
611 * our case "recover"), in routine "VBUS was valid by the time
612 * VBUSERR got reported during enumeration" cases.
613 */
614 if (devctl & MUSB_DEVCTL_VBUS) {
615 mod_timer(&musb->otg_workaround,
616 jiffies + POLL_SECONDS * HZ);
617 break;
618 }
619 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
620 musb_writel(musb->ctrl_base, USB_CORE_INTR_SET_REG,
621 MUSB_INTR_VBUSERROR << USB_INTR_USB_SHIFT);
622 break;
623 case OTG_STATE_B_IDLE:
624 if (!is_peripheral_enabled(musb))
625 break;
627 /*
628 * There's no ID-changed IRQ, so we have no good way to tell
629 * when to switch to the A-Default state machine (by setting
630 * the DEVCTL.SESSION flag).
631 *
632 * Workaround: whenever we're in B_IDLE, try setting the
633 * session flag every few seconds. If it works, ID was
634 * grounded and we're now in the A-Default state machine.
635 *
636 * NOTE: setting the session flag is _supposed_ to trigger
637 * SRP but clearly it doesn't.
638 */
639 devctl = musb_readb(mregs, MUSB_DEVCTL);
640 if (devctl & MUSB_DEVCTL_HM) {
641 musb->xceiv->state = OTG_STATE_A_IDLE;
642 } else {
643 mod_timer(&musb->otg_workaround,
644 jiffies + POLL_SECONDS * HZ);
645 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl |
646 MUSB_DEVCTL_SESSION);
647 }
648 break;
649 default:
650 break;
651 }
652 spin_unlock_irqrestore(&musb->lock, flags);
653 }
655 void ti81xx_musb_try_idle(struct musb *musb, unsigned long timeout)
656 {
657 if (!is_otg_enabled(musb))
658 return;
660 if (timeout == 0)
661 timeout = jiffies + msecs_to_jiffies(3);
663 /* Never idle if active, or when VBUS timeout is not set as host */
664 if (musb->is_active || (musb->a_wait_bcon == 0 &&
665 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
666 dev_dbg(musb->controller, "%s active, deleting timer\n",
667 otg_state_string(musb->xceiv->state));
668 del_timer(&musb->otg_workaround);
669 musb->last_timer = jiffies;
670 return;
671 }
673 if (time_after(musb->last_timer, timeout) &&
674 timer_pending(&musb->otg_workaround)) {
675 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
676 return;
677 }
678 musb->last_timer = timeout;
680 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
681 otg_state_string(musb->xceiv->state),
682 jiffies_to_msecs(timeout - jiffies));
683 mod_timer(&musb->otg_workaround, timeout);
684 }
686 #ifdef CONFIG_USB_TI_CPPI41_DMA
687 static irqreturn_t cppi41dma_Interrupt(int irq, void *hci)
688 {
689 struct musb *musb = hci;
690 u32 intr_status;
691 irqreturn_t ret = IRQ_NONE;
692 u32 q_cmpl_status_0, q_cmpl_status_1, q_cmpl_status_2;
693 u32 usb0_tx_intr, usb0_rx_intr;
694 u32 usb1_tx_intr, usb1_rx_intr;
695 void *q_mgr_base = cppi41_queue_mgr[0].q_mgr_rgn_base;
696 unsigned long flags;
698 musb = hci;
699 /*
700 * CPPI 4.1 interrupts share the same IRQ and the EOI register but
701 * don't get reflected in the interrupt source/mask registers.
702 */
703 /*
704 * Check for the interrupts from Tx/Rx completion queues; they
705 * are level-triggered and will stay asserted until the queues
706 * are emptied. We're using the queue pending register 0 as a
707 * substitute for the interrupt status register and reading it
708 * directly for speed.
709 */
710 intr_status = usbss_read(USBSS_IRQ_STATUS);
712 if (intr_status)
713 usbss_write(USBSS_IRQ_STATUS, intr_status);
714 else
715 printk(KERN_DEBUG "spurious usbss intr\n");
717 q_cmpl_status_0 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG2);
718 q_cmpl_status_1 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG3);
719 q_cmpl_status_2 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG4);
721 /* USB0 tx/rx completion */
722 /* usb0 tx completion interrupt for ep1..15 */
723 usb0_tx_intr = (q_cmpl_status_0 >> 29) |
724 ((q_cmpl_status_1 & 0xFFF) << 3);
725 usb0_rx_intr = ((q_cmpl_status_1 & 0x07FFe000) >> 13);
727 usb1_tx_intr = (q_cmpl_status_1 >> 29) |
728 ((q_cmpl_status_2 & 0xFFF) << 3);
729 usb1_rx_intr = ((q_cmpl_status_2 & 0x0fffe000) >> 13);
731 /* get proper musb handle based usb0/usb1 ctrl-id */
733 dev_dbg(musb->controller, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", usb0_tx_intr,
734 usb0_rx_intr);
735 if (gmusb[0] && (usb0_tx_intr || usb0_rx_intr)) {
736 spin_lock_irqsave(&gmusb[0]->lock, flags);
737 cppi41_completion(gmusb[0], usb0_rx_intr,
738 usb0_tx_intr);
739 spin_unlock_irqrestore(&gmusb[0]->lock, flags);
740 ret = IRQ_HANDLED;
741 }
743 dev_dbg(musb->controller, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", usb1_tx_intr,
744 usb1_rx_intr);
745 if (gmusb[1] && (usb1_rx_intr || usb1_tx_intr)) {
746 spin_lock_irqsave(&gmusb[1]->lock, flags);
747 cppi41_completion(gmusb[1], usb1_rx_intr,
748 usb1_tx_intr);
749 spin_unlock_irqrestore(&gmusb[1]->lock, flags);
750 ret = IRQ_HANDLED;
751 }
752 usbss_write(USBSS_IRQ_EOI, 0);
754 return ret;
755 }
756 #endif
758 int musb_simulate_babble(struct musb *musb)
759 {
760 void __iomem *reg_base = musb->ctrl_base;
761 void __iomem *mbase = musb->mregs;
762 u8 reg;
764 /* during babble condition musb controller
765 * remove the session
766 */
767 reg = musb_readb(mbase, MUSB_DEVCTL);
768 reg &= ~MUSB_DEVCTL_SESSION;
769 musb_writeb(mbase, MUSB_DEVCTL, reg);
770 mdelay(100);
772 /* generate s/w babble interrupt */
773 musb_writel(reg_base, USB_IRQ_STATUS_RAW_1,
774 MUSB_INTR_BABBLE);
775 return 0;
776 }
777 EXPORT_SYMBOL(musb_simulate_babble);
779 void musb_babble_workaround(struct musb *musb)
780 {
781 void __iomem *reg_base = musb->ctrl_base;
782 struct device *dev = musb->controller;
783 struct musb_hdrc_platform_data *plat = dev->platform_data;
784 struct omap_musb_board_data *data = plat->board_data;
786 /* Reset the controller */
787 musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
788 udelay(100);
790 /* Shutdown the on-chip PHY and its PLL. */
791 if (data->set_phy_power)
792 data->set_phy_power(musb->id, 0);
793 udelay(100);
795 musb_platform_set_mode(musb, MUSB_HOST);
796 udelay(100);
798 /* enable the usbphy */
799 if (data->set_phy_power)
800 data->set_phy_power(musb->id, 1);
801 mdelay(100);
803 /* save the usbotgss register contents */
804 musb_platform_enable(musb);
806 musb_start(musb);
807 }
809 static void evm_deferred_musb_restart(struct work_struct *work)
810 {
811 struct musb *musb =
812 container_of(work, struct musb, work);
814 ERR("deferred musb restart musbid(%d)\n", musb->id);
815 musb_babble_workaround(musb);
816 }
818 static irqreturn_t ti81xx_interrupt(int irq, void *hci)
819 {
820 struct musb *musb = hci;
821 void __iomem *reg_base = musb->ctrl_base;
822 unsigned long flags;
823 irqreturn_t ret = IRQ_NONE;
824 u32 pend1 = 0, pend2 = 0;
825 u32 epintr, usbintr;
826 u8 is_babble = 0;
828 spin_lock_irqsave(&musb->lock, flags);
830 /* Acknowledge and handle non-CPPI interrupts */
831 /* Get endpoint interrupts */
832 epintr = musb_readl(reg_base, USB_EP_INTR_STATUS_REG);
833 musb->int_rx = (epintr & USB_RX_INTR_MASK) >> USB_INTR_RX_SHIFT;
834 musb->int_tx = (epintr & USB_TX_INTR_MASK) >> USB_INTR_TX_SHIFT;
835 if (epintr)
836 musb_writel(reg_base, USB_EP_INTR_STATUS_REG, epintr);
838 /* Get usb core interrupts */
839 usbintr = musb_readl(reg_base, USB_CORE_INTR_STATUS_REG);
840 if (!usbintr && !epintr) {
841 dev_dbg(musb->controller, "sprious interrupt\n");
842 goto eoi;
843 }
845 if (usbintr)
846 musb_writel(reg_base, USB_CORE_INTR_STATUS_REG, usbintr);
847 musb->int_usb = (usbintr & USB_INTR_USB_MASK) >> USB_INTR_USB_SHIFT;
849 dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n", usbintr, epintr);
850 /*
851 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
852 * AM3517's missing ID change IRQ. We need an ID change IRQ to
853 * switch appropriately between halves of the OTG state machine.
854 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
855 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
856 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
857 */
858 if ((usbintr & MUSB_INTR_BABBLE) && is_otg_enabled(musb)
859 && (musb->xceiv->state == OTG_STATE_A_HOST))
860 is_babble = 1;
861 else if ((usbintr & MUSB_INTR_BABBLE) && !is_otg_enabled(musb)
862 && is_host_enabled(musb))
863 is_babble = 1;
865 if (is_babble) {
866 if (musb->enable_babble_work)
867 musb->int_usb |= MUSB_INTR_DISCONNECT;
869 ERR("CAUTION: musb%d: Babble Interrupt Occured\n", musb->id);
870 ERR("Please issue long reset to make usb functional !!\n");
871 }
873 if (usbintr & (USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT)) {
874 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
875 void __iomem *mregs = musb->mregs;
876 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
877 int err;
879 err = is_host_enabled(musb) && (musb->int_usb &
880 MUSB_INTR_VBUSERROR);
881 if (err) {
882 /*
883 * The Mentor core doesn't debounce VBUS as needed
884 * to cope with device connect current spikes. This
885 * means it's not uncommon for bus-powered devices
886 * to get VBUS errors during enumeration.
887 *
888 * This is a workaround, but newer RTL from Mentor
889 * seems to allow a better one: "re"-starting sessions
890 * without waiting for VBUS to stop registering in
891 * devctl.
892 */
893 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
894 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
895 mod_timer(&musb->otg_workaround,
896 jiffies + POLL_SECONDS * HZ);
897 WARNING("VBUS error workaround (delay coming)\n");
898 } else if (is_host_enabled(musb) && drvvbus) {
899 musb->is_active = 1;
900 MUSB_HST_MODE(musb);
901 musb->xceiv->default_a = 1;
902 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
903 del_timer(&musb->otg_workaround);
904 } else {
905 musb->is_active = 0;
906 MUSB_DEV_MODE(musb);
907 musb->xceiv->default_a = 0;
908 musb->xceiv->state = OTG_STATE_B_IDLE;
909 }
911 /* NOTE: this must complete power-on within 100 ms. */
912 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
913 drvvbus ? "on" : "off",
914 otg_state_string(musb->xceiv->state),
915 err ? " ERROR" : "",
916 devctl);
917 ret = IRQ_HANDLED;
918 }
920 if (musb->int_tx || musb->int_rx || musb->int_usb)
921 ret |= musb_interrupt(musb);
923 eoi:
924 /* EOI needs to be written for the IRQ to be re-asserted. */
925 if (ret == IRQ_HANDLED || epintr || usbintr) {
926 /* write EOI */
927 musb_writel(reg_base, USB_IRQ_EOI, 1);
928 }
930 /* Poll for ID change */
931 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
932 mod_timer(&musb->otg_workaround, jiffies + POLL_SECONDS * HZ);
934 spin_unlock_irqrestore(&musb->lock, flags);
936 if (ret != IRQ_HANDLED) {
937 if (epintr || usbintr)
938 /*
939 * We sometimes get unhandled IRQs in the peripheral
940 * mode from EP0 and SOF...
941 */
942 dev_dbg(musb->controller, "Unhandled USB IRQ %08x-%08x\n",
943 epintr, usbintr);
944 else if (printk_ratelimit())
945 /*
946 * We've seen series of spurious interrupts in the
947 * peripheral mode after USB reset and then after some
948 * time a real interrupt storm starting...
949 */
950 dev_dbg(musb->controller, "Spurious IRQ, CPPI 4.1 status %08x, %08x\n",
951 pend1, pend2);
952 }
954 if (is_babble) {
955 if (!musb->enable_babble_work) {
956 musb_writeb(musb->mregs, MUSB_DEVCTL,
957 musb_readb(musb->mregs, MUSB_DEVCTL) |
958 MUSB_DEVCTL_SESSION);
959 } else {
960 ERR("Babble: devtcl(%x)Restarting musb....\n",
961 musb_readb(musb->mregs, MUSB_DEVCTL));
962 schedule_work(&musb->work);
963 }
964 }
965 return ret;
966 }
967 int ti81xx_musb_set_mode(struct musb *musb, u8 musb_mode)
968 {
969 void __iomem *reg_base = musb->ctrl_base;
970 u32 regval;
972 /* TODO: implement this using CONF0 */
973 if (musb_mode == MUSB_HOST) {
974 regval = musb_readl(reg_base, USB_MODE_REG);
976 regval &= ~USBMODE_USBID_HIGH;
977 if (usbid_sw_ctrl && cpu_is_ti816x())
978 regval |= USBMODE_USBID_MUXSEL;
980 musb_writel(reg_base, USB_MODE_REG, regval);
981 musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
982 dev_dbg(musb->controller, "host: value of mode reg=%x regval(%x)\n",
983 musb_readl(reg_base, USB_MODE_REG), regval);
984 } else if (musb_mode == MUSB_PERIPHERAL) {
985 /* TODO commmented writing 8 to USB_MODE_REG device
986 mode is not working */
987 regval = musb_readl(reg_base, USB_MODE_REG);
989 regval |= USBMODE_USBID_HIGH;
990 if (usbid_sw_ctrl && cpu_is_ti816x())
991 regval |= USBMODE_USBID_MUXSEL;
993 musb_writel(reg_base, USB_MODE_REG, regval);
994 dev_dbg(musb->controller, "device: value of mode reg=%x regval(%x)\n",
995 musb_readl(reg_base, USB_MODE_REG), regval);
996 } else if (musb_mode == MUSB_OTG) {
997 musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
998 } else
999 return -EIO;
1001 return 0;
1002 }
1004 int ti81xx_musb_init(struct musb *musb)
1005 {
1006 void __iomem *reg_base = musb->ctrl_base;
1007 struct device *dev = musb->controller;
1008 struct musb_hdrc_platform_data *plat = dev->platform_data;
1009 struct omap_musb_board_data *data = plat->board_data;
1010 u32 rev, status = 0;
1011 u8 mode;
1013 if (musb->id < 2)
1014 gmusb[musb->id] = musb;
1016 usb_nop_xceiv_register(musb->id);
1018 musb->xceiv = otg_get_transceiver(musb->id);
1019 if (!musb->xceiv)
1020 return -ENODEV;
1022 status = pm_runtime_get_sync(dev);
1023 if (status < 0) {
1024 dev_err(dev, "pm_runtime_get_sync FAILED");
1025 goto err1;
1026 }
1028 /* mentor is at offset of 0x400 in am3517/ti81xx */
1029 musb->mregs += USB_MENTOR_CORE_OFFSET;
1032 /* Returns zero if e.g. not clocked */
1033 rev = musb_readl(reg_base, USB_REVISION_REG);
1034 if (!rev)
1035 return -ENODEV;
1037 if (is_host_enabled(musb))
1038 setup_timer(&musb->otg_workaround, otg_timer,
1039 (unsigned long) musb);
1041 /* Reset the controller */
1042 musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
1044 /* wait till reset bit clears */
1045 while ((musb_readl(reg_base, USB_CTRL_REG) & 0x1))
1046 cpu_relax();
1048 /* Start the on-chip PHY and its PLL. */
1049 if (data->set_phy_power)
1050 data->set_phy_power(musb->id, 1);
1052 musb->a_wait_bcon = A_WAIT_BCON_TIMEOUT;
1053 musb->isr = ti81xx_interrupt;
1055 if (cpu_is_ti816x())
1056 usbid_sw_ctrl = 1;
1058 if (is_otg_enabled(musb)) {
1059 /* if usb-id contolled through software for ti816x then
1060 * configure the usb0 in peripheral mode and usb1 in
1061 * host mode
1062 */
1063 if (usbid_sw_ctrl && cpu_is_ti816x())
1064 mode = musb->id ? MUSB_HOST : MUSB_PERIPHERAL;
1065 else
1066 mode = MUSB_OTG;
1067 } else
1068 /* set musb controller to host mode */
1069 mode = is_host_enabled(musb) ? MUSB_HOST : MUSB_PERIPHERAL;
1071 /* set musb controller to host mode */
1072 musb_platform_set_mode(musb, mode);
1074 /* enable babble workaround */
1075 INIT_WORK(&musb->work, evm_deferred_musb_restart);
1076 musb->enable_babble_work = 0;
1078 musb_writel(reg_base, USB_IRQ_EOI, 0);
1080 return 0;
1081 err1:
1082 pm_runtime_disable(dev);
1083 return status;
1084 }
1086 /* TI81xx supports only 32bit read operation */
1087 void ti81xx_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
1088 {
1089 void __iomem *fifo = hw_ep->fifo;
1090 u32 val;
1091 int i;
1093 /* Read for 32bit-aligned destination address */
1094 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
1095 readsl(fifo, dst, len >> 2);
1096 dst += len & ~0x03;
1097 len &= 0x03;
1098 }
1099 /*
1100 * Now read the remaining 1 to 3 byte or complete length if
1101 * unaligned address.
1102 */
1103 if (len > 4) {
1104 for (i = 0; i < (len >> 2); i++) {
1105 *(u32 *) dst = musb_readl(fifo, 0);
1106 dst += 4;
1107 }
1108 len &= 0x03;
1109 }
1110 if (len > 0) {
1111 val = musb_readl(fifo, 0);
1112 memcpy(dst, &val, len);
1113 }
1114 }
1116 int ti81xx_musb_exit(struct musb *musb)
1117 {
1118 struct device *dev = musb->controller;
1119 struct musb_hdrc_platform_data *plat = dev->platform_data;
1120 struct omap_musb_board_data *data = plat->board_data;
1122 if (is_host_enabled(musb))
1123 del_timer_sync(&musb->otg_workaround);
1125 /* Shutdown the on-chip PHY and its PLL. */
1126 if (data->set_phy_power)
1127 data->set_phy_power(musb->id, 0);
1129 otg_put_transceiver(musb->xceiv);
1130 usb_nop_xceiv_unregister(musb->id);
1132 return 0;
1133 }
1135 static struct musb_platform_ops ti81xx_ops = {
1136 .fifo_mode = 4,
1137 .flags = MUSB_GLUE_EP_ADDR_FLAT_MAPPING | MUSB_GLUE_DMA_CPPI41,
1138 .init = ti81xx_musb_init,
1139 .exit = ti81xx_musb_exit,
1141 .enable = ti81xx_musb_enable,
1142 .disable = ti81xx_musb_disable,
1144 .try_idle = ti81xx_musb_try_idle,
1145 .set_mode = ti81xx_musb_set_mode,
1147 .read_fifo = ti81xx_musb_read_fifo,
1148 .write_fifo = musb_write_fifo,
1150 .dma_controller_create = cppi41_dma_controller_create,
1151 .dma_controller_destroy = cppi41_dma_controller_destroy,
1152 .simulate_babble_intr = musb_simulate_babble,
1153 };
1155 static void __devexit ti81xx_delete_musb_pdev(struct ti81xx_glue *glue, u8 id)
1156 {
1157 platform_device_del(glue->musb[id]);
1158 platform_device_put(glue->musb[id]);
1159 }
1161 static int __devinit ti81xx_create_musb_pdev(struct ti81xx_glue *glue, u8 id)
1162 {
1163 struct device *dev = glue->dev;
1164 struct platform_device *pdev = to_platform_device(dev);
1165 struct musb_hdrc_platform_data *pdata = dev->platform_data;
1166 struct omap_musb_board_data *bdata = pdata->board_data;
1167 struct platform_device *musb;
1168 struct resource *res;
1169 struct resource resources[2];
1170 char res_name[10];
1171 int ret = 0;
1173 /* get memory resource */
1174 sprintf(res_name, "musb%d", id);
1175 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name);
1176 if (!res) {
1177 dev_err(dev, "%s get mem resource failed\n", res_name);
1178 ret = -ENODEV;
1179 goto err0;
1180 }
1181 res->parent = NULL;
1182 resources[0] = *res;
1184 /* get irq resource */
1185 sprintf(res_name, "musb%d-irq", id);
1186 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res_name);
1187 if (!res) {
1188 dev_err(dev, "%s get irq resource failed\n", res_name);
1189 ret = -ENODEV;
1190 goto err0;
1191 }
1192 res->parent = NULL;
1193 resources[1] = *res;
1195 /* allocate the child platform device */
1196 musb = platform_device_alloc("musb-hdrc", id);
1197 if (!musb) {
1198 dev_err(dev, "failed to allocate musb device\n");
1199 goto err0;
1200 }
1202 musb->id = id;
1203 musb->dev.parent = dev;
1204 musb->dev.dma_mask = &musb_dmamask;
1205 musb->dev.coherent_dma_mask = musb_dmamask;
1207 glue->musb[id] = musb;
1209 pdata->platform_ops = &ti81xx_ops;
1211 ret = platform_device_add_resources(musb, resources, 2);
1212 if (ret) {
1213 dev_err(dev, "failed to add resources\n");
1214 goto err1;
1215 }
1217 if (id == 0)
1218 pdata->mode = bdata->mode & USB0PORT_MODEMASK;
1219 else
1220 pdata->mode = (bdata->mode & USB1PORT_MODEMASK)
1221 >> USB1PORT_MODESHIFT;
1223 dev_info(dev, "musb%d, board_mode=0x%x, plat_mode=0x%x\n",
1224 id, bdata->mode, pdata->mode);
1226 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
1227 if (ret) {
1228 dev_err(dev, "failed to add platform_data\n");
1229 goto err1;
1230 }
1232 ret = platform_device_add(musb);
1233 if (ret) {
1234 dev_err(dev, "failed to register musb device\n");
1235 goto err1;
1236 }
1238 return 0;
1240 err1:
1241 platform_device_put(musb);
1242 err0:
1243 return ret;
1244 }
1246 static int __init ti81xx_probe(struct platform_device *pdev)
1247 {
1248 struct ti81xx_glue *glue;
1249 struct device *dev = &pdev->dev;
1250 struct musb_hdrc_platform_data *plat = dev->platform_data;
1251 struct omap_musb_board_data *data = plat->board_data;
1252 int ret = 0, i;
1253 struct resource *res;
1255 /* allocate glue */
1256 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1257 if (!glue) {
1258 dev_err(&pdev->dev, "unable to allocate glue memory\n");
1259 ret = -ENOMEM;
1260 goto err0;
1261 }
1263 /* interface clock needs to be enabled for usbss register programming */
1264 glue->ick = clk_get(&pdev->dev, "usbotg_ick");
1265 if (IS_ERR(glue->ick)) {
1266 dev_err(&pdev->dev, "unable to get usbss interface clock\n");
1267 ret = PTR_ERR(glue->ick);
1268 goto err1;
1269 }
1271 /* functional clock needs to be enabled for usbss register programming */
1272 glue->fck = clk_get(&pdev->dev, "usbotg_fck");
1273 if (IS_ERR(glue->fck)) {
1274 dev_err(&pdev->dev, "unable to get usbss functional clock\n");
1275 ret = PTR_ERR(glue->fck);
1276 goto err2;
1277 }
1279 /* get memory resource */
1280 glue->mem_pa = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1281 if (!glue->mem_pa) {
1282 dev_err(&pdev->dev, "failed to get usbss mem resourse\n");
1283 ret = -ENODEV;
1284 goto err3;
1285 }
1287 /* get memory resource */
1288 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "usbss-irq");
1289 if (!res) {
1290 dev_err(&pdev->dev, "failed to get usbss irq resourse\n");
1291 ret = -ENODEV;
1292 goto err3;
1293 }
1294 glue->irq = res->start;
1296 /* enable interface clock */
1297 ret = clk_enable(glue->ick);
1298 if (ret) {
1299 dev_err(&pdev->dev, "failed to enable usbss interface clock\n");
1300 goto err3;
1301 }
1303 /* enable functional clock */
1304 ret = clk_enable(glue->fck);
1305 if (ret) {
1306 dev_err(&pdev->dev, "failed to enable usbss functional clock\n");
1307 goto err4;
1308 }
1310 /* iomap for usbss mem space */
1311 glue->mem_va =
1312 ioremap(glue->mem_pa->start, resource_size(glue->mem_pa));
1313 if (!glue->mem_va) {
1314 dev_err(&pdev->dev, "usbss ioremap failed\n");
1315 ret = -ENOMEM;
1316 goto err5;
1317 }
1318 usbss_virt_base = glue->mem_va;
1320 glue->dev = &pdev->dev;
1321 platform_set_drvdata(pdev, glue);
1323 /* usb subsystem init */
1324 usbotg_ss_init();
1326 /* clear any USBSS interrupts */
1327 __raw_writel(0, glue->mem_va + USBSS_IRQ_EOI);
1328 __raw_writel(__raw_readl(glue->mem_va + USBSS_IRQ_STATUS),
1329 glue->mem_va + USBSS_IRQ_STATUS);
1331 /* create the child platform device for mulitple instances of musb */
1332 for (i = 0; i <= data->instances; ++i) {
1333 #ifdef CONFIG_USB_TI_CPPI41_DMA
1334 /* initialize the cppi41dma init */
1335 cppi41_init(i, glue->irq, data->instances+1);
1336 #endif
1337 ret = ti81xx_create_musb_pdev(glue, i);
1338 if (ret != 0)
1339 goto err6;
1340 }
1342 return 0;
1344 err6:
1345 iounmap(glue->mem_va);
1346 err5:
1347 clk_disable(glue->fck);
1348 err4:
1349 clk_disable(glue->ick);
1350 err3:
1351 clk_put(glue->fck);
1352 err2:
1353 clk_put(glue->ick);
1354 err1:
1355 kfree(glue);
1356 err0:
1357 return ret;
1358 }
1360 static int __exit ti81xx_remove(struct platform_device *pdev)
1361 {
1362 struct ti81xx_glue *glue = platform_get_drvdata(pdev);
1363 struct device *dev = &pdev->dev;
1364 struct musb_hdrc_platform_data *plat = dev->platform_data;
1365 struct omap_musb_board_data *data = plat->board_data;
1366 int i;
1368 /* delete the child platform device for mulitple instances of musb */
1369 for (i = 0; i <= data->instances; ++i)
1370 ti81xx_delete_musb_pdev(glue, i);
1372 #ifdef CONFIG_USB_TI_CPPI41_DMA
1373 cppi41_free();
1374 #endif
1375 /* iounmap */
1376 iounmap(glue->mem_va);
1377 usbotg_ss_uninit();
1379 /* disable common usbss functional clock */
1380 clk_disable(glue->fck);
1381 clk_put(glue->fck);
1382 /* disable common usbss interface clock */
1383 clk_disable(glue->ick);
1384 clk_put(glue->ick);
1385 kfree(glue);
1387 return 0;
1388 }
1390 #ifdef CONFIG_PM
1391 static int ti81xx_suspend(struct device *dev)
1392 {
1393 struct ti81xx_glue *glue = dev_get_drvdata(dev);
1394 struct musb_hdrc_platform_data *plat = dev->platform_data;
1395 struct omap_musb_board_data *data = plat->board_data;
1396 int i;
1398 /* Shutdown the on-chip PHY and its PLL. */
1399 for (i = 0; i <= data->instances; ++i) {
1400 if (data->set_phy_power)
1401 data->set_phy_power(i, 0);
1402 }
1404 /* disable the common usbss functional clock */
1405 clk_disable(glue->fck);
1406 /* disable the common usbss interface clock */
1407 clk_disable(glue->ick);
1408 return 0;
1409 }
1411 static int ti81xx_resume(struct device *dev)
1412 {
1413 struct ti81xx_glue *glue = dev_get_drvdata(dev);
1414 struct musb_hdrc_platform_data *plat = dev->platform_data;
1415 struct omap_musb_board_data *data = plat->board_data;
1416 int ret, i;
1418 /* Start the on-chip PHY and its PLL. */
1419 for (i = 0; i <= data->instances; ++i) {
1420 if (data->set_phy_power)
1421 data->set_phy_power(i, 1);
1422 }
1424 /* enable the common usbss interface clock */
1425 ret = clk_enable(glue->ick);
1426 if (ret) {
1427 dev_err(dev, "failed to enable iclock\n");
1428 return ret;
1429 }
1430 /* enable the common usbss functional clock */
1431 ret = clk_enable(glue->fck);
1432 if (ret) {
1433 dev_err(dev, "failed to enable fclock\n");
1434 return ret;
1435 }
1436 return 0;
1437 }
1439 static const struct dev_pm_ops ti81xx_pm_ops = {
1440 .suspend = ti81xx_suspend,
1441 .resume = ti81xx_resume,
1442 };
1444 #define DEV_PM_OPS (&ti81xx_pm_ops)
1445 #else
1446 #define DEV_PM_OPS NULL
1447 #endif
1449 static struct platform_driver ti81xx_musb_driver = {
1450 .remove = __exit_p(ti81xx_remove),
1451 .driver = {
1452 .name = "musb-ti81xx",
1453 .pm = DEV_PM_OPS,
1454 },
1455 };
1457 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1458 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
1459 MODULE_LICENSE("GPL v2");
1461 static int __init ti81xx_glue_init(void)
1462 {
1463 return platform_driver_probe(&ti81xx_musb_driver, ti81xx_probe);
1464 }
1465 subsys_initcall(ti81xx_glue_init);
1467 static void __exit ti81xx_glue_exit(void)
1468 {
1469 #ifdef CONFIG_USB_TI_CPPI41_DMA
1470 /* free the usbss irq */
1471 free_irq(TI81XX_IRQ_USBSS, 0);
1472 #endif
1474 /* disable the interrupts */
1475 usbss_write(USBSS_IRQ_EOI, 0);
1476 usbss_write(USBSS_IRQ_ENABLE_SET, 0);
1477 usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0);
1479 /* unregister platform driver */
1480 platform_driver_unregister(&ti81xx_musb_driver);
1481 }
1482 module_exit(ti81xx_glue_exit);
1484 #ifdef CONFIG_PM
1485 void musb_platform_save_context(struct musb *musb,
1486 struct musb_context_registers *musb_context)
1487 {
1488 /* Save CPPI41 DMA related registers */
1489 }
1491 void musb_platform_restore_context(struct musb *musb,
1492 struct musb_context_registers *musb_context)
1493 {
1494 /* Restore CPPI41 DMA related registers */
1495 }
1496 #endif