1 /*
2 * Texas Instruments TI81XX "glue layer"
3 *
4 * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * Based on the DaVinci "glue layer" code.
7 * Copyright (C) 2005-2006 by Texas Instruments
8 *
9 * This file is part of the Inventra Controller Driver for Linux.
10 *
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
14 * Foundation.
15 *
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
29 #include <linux/init.h>
30 #include <linux/clk.h>
31 #include <linux/io.h>
32 #include <linux/usb/otg.h>
33 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/module.h>
37 #include "cppi41.h"
38 #include "ti81xx.h"
40 #include "musb_core.h"
41 #include "cppi41_dma.h"
43 struct ti81xx_glue {
44 struct device *dev;
45 struct platform_device *musb;
46 struct clk *phy_clk;
47 struct clk *clk;
48 };
49 static u64 musb_dmamask = DMA_BIT_MASK(32);
50 static void *usbss_virt_base;
51 static u8 usbss_init_done;
52 struct musb *gmusb[2];
54 #undef USB_TI81XX_DEBUG
56 #ifdef USB_TI81XX_DEBUG
57 #define dprintk(x, ...) printk(x, ## __VA_ARGS__)
58 #else
59 #define dprintk(x, ...)
60 #endif
62 #ifdef CONFIG_USB_TI_CPPI41_DMA
63 static irqreturn_t cppi41dma_Interrupt(int irq, void *hci);
64 static u8 cppi41_init_done;
65 static void *cppi41_dma_base;
66 #define CPPI41_ADDR(offs) ((void *)((u32)cppi41_dma_base + (offs - 0x2000)))
67 #endif
69 extern void omap_ctrl_writel(u32 val, u16 offset);
70 extern u32 omap_ctrl_readl(u16 offset);
72 static inline u32 usbss_read(u32 offset)
73 {
74 return __raw_readl(usbss_virt_base + offset);
75 }
77 static inline void usbss_write(u32 offset, u32 data)
78 {
79 __raw_writel(data, usbss_virt_base + offset);
80 }
82 static void __init usbotg_ss_init(struct musb *musb)
83 {
84 if (!usbss_init_done) {
85 usbss_virt_base = ioremap(TI81XX_USBSS_BASE,
86 TI81XX_USBSS_LEN);
87 usbss_init_done = 1;
88 /* clear any USBSS interrupts */
89 usbss_write(USBSS_IRQ_EOI, 0);
90 usbss_write(USBSS_IRQ_STATUS, usbss_read(USBSS_IRQ_STATUS));
91 }
92 }
94 void set_frame_threshold(u8 musb_id, u8 is_tx, u8 epnum, u8 value, u8 en_intr)
95 {
96 u32 base, reg_val, frame_intr = 0, frame_base = 0;
97 u32 offs = epnum/4*4;
98 u8 indx = (epnum % 4) * 8;
100 if (is_tx)
101 base = musb_id ? USBSS_IRQ_FRAME_THRESHOLD_TX1 :
102 USBSS_IRQ_FRAME_THRESHOLD_TX0;
103 else
104 base = musb_id ? USBSS_IRQ_FRAME_THRESHOLD_RX1 :
105 USBSS_IRQ_FRAME_THRESHOLD_RX0;
107 reg_val = usbss_read(base + offs);
108 reg_val &= ~(0xFF << indx);
109 reg_val |= (value << indx);
110 usbss_write(base + offs, reg_val);
112 if (en_intr) {
113 frame_base = musb_id ? USBSS_IRQ_FRAME_ENABLE_1 :
114 USBSS_IRQ_FRAME_ENABLE_0;
115 frame_intr = musb_id ? usbss_read(USBSS_IRQ_FRAME_ENABLE_0) :
116 usbss_read(USBSS_IRQ_FRAME_ENABLE_1);
117 frame_intr |= is_tx ? (1 << epnum) : (1 << (16 + epnum));
118 usbss_write(frame_base, frame_intr);
119 DBG(4, "%s: framebase=%x, frame_intr=%x\n", is_tx ? "tx" : "rx",
120 frame_base, frame_intr);
121 }
122 }
124 void set_dma_threshold(u8 musb_id, u8 is_tx, u8 epnum, u8 value)
125 {
126 u32 base, reg_val;
127 u32 offs = epnum/4*4;
128 u8 indx = (epnum % 4) * 8;
130 if (musb_id == 0)
131 base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX0 :
132 USBSS_IRQ_DMA_THRESHOLD_RX0;
133 else
134 base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX1 :
135 USBSS_IRQ_DMA_THRESHOLD_RX1;
137 reg_val = usbss_read(base + offs);
138 reg_val &= ~(0xFF << indx);
139 reg_val |= (value << indx);
140 DBG(4, "base=%x, offs=%x, indx=%d, reg_val = (%x)%x\n",
141 base, offs, indx, reg_val, usbss_read(base + offs));
142 usbss_write(base + offs, reg_val);
143 }
145 /* ti81xx specific read/write functions */
146 u16 ti81xx_musb_readw(const void __iomem *addr, unsigned offset)
147 {
148 u32 tmp;
149 u16 val;
151 tmp = __raw_readl(addr + (offset & ~3));
153 switch (offset & 0x3) {
154 case 0:
155 val = (tmp & 0xffff);
156 break;
157 case 1:
158 val = (tmp >> 8) & 0xffff;
159 break;
160 case 2:
161 case 3:
162 default:
163 val = (tmp >> 16) & 0xffff;
164 break;
165 }
166 return val;
167 }
169 void ti81xx_musb_writew(void __iomem *addr, unsigned offset, u16 data)
170 {
171 __raw_writew(data, addr + offset);
172 }
174 u8 ti81xx_musb_readb(const void __iomem *addr, unsigned offset)
175 {
176 u32 tmp;
177 u8 val;
179 tmp = __raw_readl(addr + (offset & ~3));
181 switch (offset & 0x3) {
182 case 0:
183 val = tmp & 0xff;
184 break;
185 case 1:
186 val = (tmp >> 8);
187 break;
188 case 2:
189 val = (tmp >> 16);
190 break;
191 case 3:
192 default:
193 val = (tmp >> 24);
194 break;
195 }
196 return val;
197 }
198 void ti81xx_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
199 {
200 __raw_writeb(data, addr + offset);
201 }
203 #ifdef CONFIG_USB_TI_CPPI41_DMA
204 /*
205 * CPPI 4.1 resources used for USB OTG controller module:
206 *
207 tx/rx completion queues for usb0 */
208 static u16 tx_comp_q[] = {93, 94, 95, 96, 97,
209 98, 99, 100, 101, 102,
210 103, 104, 105, 106, 107 };
212 static u16 rx_comp_q[] = {109, 110, 111, 112, 113,
213 114, 115, 116, 117, 118,
214 119, 120, 121, 122, 123 };
216 /* tx/rx completion queues for usb1 */
217 static u16 tx_comp_q1[] = {125, 126, 127, 128, 129,
218 130, 131, 132, 133, 134,
219 135, 136, 137, 138, 139 };
221 static u16 rx_comp_q1[] = {141, 142, 143, 144, 145,
222 146, 147, 148, 149, 150,
223 151, 152, 153, 154, 155 };
225 /* Fair scheduling */
226 u32 dma_sched_table[] = {
227 0x81018000, 0x83038202, 0x85058404, 0x87078606,
228 0x89098808, 0x8b0b8a0a, 0x8d0d8c0c, 0x8f0f8e0e,
229 0x91119010, 0x93139212, 0x95159414, 0x97179616,
230 0x99199818, 0x9b1b9a1a, 0x9d1d9c1c, 0x00009e1e,
231 };
233 /* cppi41 dma tx channel info */
234 static const struct cppi41_tx_ch tx_ch_info[] = {
235 [0] = {
236 .port_num = 1,
237 .num_tx_queue = 2,
238 .tx_queue = { {0, 32} , {0, 33} }
239 },
240 [1] = {
241 .port_num = 2,
242 .num_tx_queue = 2,
243 .tx_queue = { {0, 34} , {0, 35} }
244 },
245 [2] = {
246 .port_num = 3,
247 .num_tx_queue = 2,
248 .tx_queue = { {0, 36} , {0, 37} }
249 },
250 [3] = {
251 .port_num = 4,
252 .num_tx_queue = 2,
253 .tx_queue = { {0, 38} , {0, 39} }
254 },
255 [4] = {
256 .port_num = 5,
257 .num_tx_queue = 2,
258 .tx_queue = { {0, 40} , {0, 41} }
259 },
260 [5] = {
261 .port_num = 6,
262 .num_tx_queue = 2,
263 .tx_queue = { {0, 42} , {0, 43} }
264 },
265 [6] = {
266 .port_num = 7,
267 .num_tx_queue = 2,
268 .tx_queue = { {0, 44} , {0, 45} }
269 },
270 [7] = {
271 .port_num = 8,
272 .num_tx_queue = 2,
273 .tx_queue = { {0, 46} , {0, 47} }
274 },
275 [8] = {
276 .port_num = 9,
277 .num_tx_queue = 2,
278 .tx_queue = { {0, 48} , {0, 49} }
279 },
280 [9] = {
281 .port_num = 10,
282 .num_tx_queue = 2,
283 .tx_queue = { {0, 50} , {0, 51} }
284 },
285 [10] = {
286 .port_num = 11,
287 .num_tx_queue = 2,
288 .tx_queue = { {0, 52} , {0, 53} }
289 },
290 [11] = {
291 .port_num = 12,
292 .num_tx_queue = 2,
293 .tx_queue = { {0, 54} , {0, 55} }
294 },
295 [12] = {
296 .port_num = 13,
297 .num_tx_queue = 2,
298 .tx_queue = { {0, 56} , {0, 57} }
299 },
300 [13] = {
301 .port_num = 14,
302 .num_tx_queue = 2,
303 .tx_queue = { {0, 58} , {0, 59} }
304 },
305 [14] = {
306 .port_num = 15,
307 .num_tx_queue = 2,
308 .tx_queue = { {0, 60} , {0, 61} }
309 },
310 [15] = {
311 .port_num = 1,
312 .num_tx_queue = 2,
313 .tx_queue = { {0, 62} , {0, 63} }
314 },
315 [16] = {
316 .port_num = 2,
317 .num_tx_queue = 2,
318 .tx_queue = { {0, 64} , {0, 65} }
319 },
320 [17] = {
321 .port_num = 3,
322 .num_tx_queue = 2,
323 .tx_queue = { {0, 66} , {0, 67} }
324 },
325 [18] = {
326 .port_num = 4,
327 .num_tx_queue = 2,
328 .tx_queue = { {0, 68} , {0, 69} }
329 },
330 [19] = {
331 .port_num = 5,
332 .num_tx_queue = 2,
333 .tx_queue = { {0, 70} , {0, 71} }
334 },
335 [20] = {
336 .port_num = 6,
337 .num_tx_queue = 2,
338 .tx_queue = { {0, 72} , {0, 73} }
339 },
340 [21] = {
341 .port_num = 7,
342 .num_tx_queue = 2,
343 .tx_queue = { {0, 74} , {0, 75} }
344 },
345 [22] = {
346 .port_num = 8,
347 .num_tx_queue = 2,
348 .tx_queue = { {0, 76} , {0, 77} }
349 },
350 [23] = {
351 .port_num = 9,
352 .num_tx_queue = 2,
353 .tx_queue = { {0, 78} , {0, 79} }
354 },
355 [24] = {
356 .port_num = 10,
357 .num_tx_queue = 2,
358 .tx_queue = { {0, 80} , {0, 81} }
359 },
360 [25] = {
361 .port_num = 11,
362 .num_tx_queue = 2,
363 .tx_queue = { {0, 82} , {0, 83} }
364 },
365 [26] = {
366 .port_num = 12,
367 .num_tx_queue = 2,
368 .tx_queue = { {0, 84} , {0, 85} }
369 },
370 [27] = {
371 .port_num = 13,
372 .num_tx_queue = 2,
373 .tx_queue = { {0, 86} , {0, 87} }
374 },
375 [28] = {
376 .port_num = 14,
377 .num_tx_queue = 2,
378 .tx_queue = { {0, 88} , {0, 89} }
379 },
380 [29] = {
381 .port_num = 15,
382 .num_tx_queue = 2,
383 .tx_queue = { {0, 90} , {0, 91} }
384 }
385 };
387 /* Queues 0 to 66 are pre-assigned, others are spare */
388 static const u32 assigned_queues[] = { 0xffffffff, /* queue 0..31 */
389 0xffffffff, /* queue 32..63 */
390 0xffffffff, /* queue 64..95 */
391 0xffffffff, /* queue 96..127 */
392 0x0fffffff /* queue 128..155 */
393 };
395 int __devinit cppi41_init(struct musb *musb)
396 {
397 struct usb_cppi41_info *cppi_info = &usb_cppi41_info[musb->id];
398 u16 numch, blknum, order;
399 u32 i, nIrq = TI81XX_IRQ_USBSS;
401 /* init cppi info structure */
402 cppi_info->dma_block = 0;
403 for (i = 0 ; i < USB_CPPI41_NUM_CH ; i++)
404 cppi_info->ep_dma_ch[i] = i + (15 * musb->id);
406 cppi_info->q_mgr = 0;
407 cppi_info->num_tx_comp_q = 15;
408 cppi_info->num_rx_comp_q = 15;
409 cppi_info->tx_comp_q = musb->id ? tx_comp_q1 : tx_comp_q;
410 cppi_info->rx_comp_q = musb->id ? rx_comp_q1 : rx_comp_q;
411 cppi_info->bd_intr_ctrl = 1;
413 if (cppi41_init_done)
414 return 0;
416 blknum = cppi_info->dma_block;
418 /* Queue manager information */
419 cppi41_queue_mgr[0].num_queue = 159;
420 cppi41_queue_mgr[0].queue_types = CPPI41_FREE_DESC_BUF_QUEUE |
421 CPPI41_UNASSIGNED_QUEUE;
422 cppi41_queue_mgr[0].base_fdbq_num = 0;
423 cppi41_queue_mgr[0].assigned = assigned_queues;
425 /* init DMA block */
426 cppi41_dma_block[0].num_tx_ch = 30;
427 cppi41_dma_block[0].num_rx_ch = 30;
428 cppi41_dma_block[0].tx_ch_info = tx_ch_info;
430 /* initilize cppi41 dma & Qmgr address */
431 cppi41_dma_base = ioremap(TI81XX_USB_CPPIDMA_BASE,
432 TI81XX_USB_CPPIDMA_LEN);
434 cppi41_queue_mgr[0].q_mgr_rgn_base = CPPI41_ADDR(QMGR_RGN_OFFS);
435 cppi41_queue_mgr[0].desc_mem_rgn_base = CPPI41_ADDR(QMRG_DESCRGN_OFFS);
436 cppi41_queue_mgr[0].q_mgmt_rgn_base = CPPI41_ADDR(QMGR_REG_OFFS);
437 cppi41_queue_mgr[0].q_stat_rgn_base = CPPI41_ADDR(QMGR_STAT_OFFS);
438 cppi41_dma_block[0].global_ctrl_base = CPPI41_ADDR(DMA_GLBCTRL_OFFS);
439 cppi41_dma_block[0].ch_ctrl_stat_base = CPPI41_ADDR(DMA_CHCTRL_OFFS);
440 cppi41_dma_block[0].sched_ctrl_base = CPPI41_ADDR(DMA_SCHED_OFFS);
441 cppi41_dma_block[0].sched_table_base = CPPI41_ADDR(DMA_SCHEDTBL_OFFS);
443 /* Initialize for Linking RAM region 0 alone */
444 cppi41_queue_mgr_init(cppi_info->q_mgr, 0, 0x3fff);
446 numch = USB_CPPI41_NUM_CH * 2 * 2;
447 order = get_count_order(numch);
449 /* TODO: check two teardown desc per channel (5 or 7 ?)*/
450 if (order < 5)
451 order = 5;
453 cppi41_dma_block_init(blknum, cppi_info->q_mgr, order,
454 dma_sched_table, numch);
456 /* attach to the IRQ */
457 if (request_irq(nIrq, cppi41dma_Interrupt, 0, "cppi41_dma", musb))
458 printk(KERN_INFO "request_irq %d failed!\n", nIrq);
459 else
460 printk(KERN_INFO "registerd cppi-dma Intr @ IRQ %d\n", nIrq);
462 cppi41_init_done = 1;
464 /* enable all the interrupts */
465 usbss_write(USBSS_IRQ_EOI, 0);
466 usbss_write(USBSS_IRQ_ENABLE_SET, USBSS_INTR_FLAGS);
467 usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0xFFFeFFFe);
469 DBG(4, "Cppi41 Init Done Qmgr-base(%p) dma-base(%p)\n",
470 cppi41_queue_mgr[0].q_mgr_rgn_base,
471 cppi41_dma_block[0].global_ctrl_base);
473 printk(KERN_INFO "Cppi41 Init Done\n");
475 return 0;
476 }
478 void cppi41_free(void)
479 {
480 if (!cppi41_init_done)
481 return ;
483 /* REVISIT: iounmap causing issue in rmmod */
484 /* iounmap(cppi41_dma_base); */
485 cppi41_dma_base = 0;
486 cppi41_init_done = 0;
487 }
489 int cppi41_disable_sched_rx(void)
490 {
491 cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
492 return 0;
493 }
495 int cppi41_enable_sched_rx(void)
496 {
497 cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
498 return 0;
499 }
500 #endif /* CONFIG_USB_TI_CPPI41_DMA */
502 /*
503 * Because we don't set CTRL.UINT, it's "important" to:
504 * - not read/write INTRUSB/INTRUSBE (except during
505 * initial setup, as a workaround);
506 * - use INTSET/INTCLR instead.
507 */
509 /**
510 * ti81xx_musb_enable - enable interrupts
511 */
512 void ti81xx_musb_enable(struct musb *musb)
513 {
514 void __iomem *reg_base = musb->ctrl_base;
515 u32 epmask, coremask;
517 /* Workaround: setup IRQs through both register sets. */
518 epmask = ((musb->epmask & USB_TX_EP_MASK) << USB_INTR_TX_SHIFT) |
519 ((musb->epmask & USB_RX_EP_MASK) << USB_INTR_RX_SHIFT);
520 coremask = (0x01ff << USB_INTR_USB_SHIFT);
522 coremask &= ~MUSB_INTR_SOF;
524 musb_writel(reg_base, USB_EP_INTR_SET_REG, epmask);
525 musb_writel(reg_base, USB_CORE_INTR_SET_REG, coremask);
526 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
527 if (is_otg_enabled(musb))
528 musb_writel(reg_base, USB_CORE_INTR_SET_REG,
529 USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT);
530 }
532 /**
533 * ti81xx_musb_disable - disable HDRC and flush interrupts
534 */
535 void ti81xx_musb_disable(struct musb *musb)
536 {
537 void __iomem *reg_base = musb->ctrl_base;
539 musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, USB_INTR_USB_MASK);
540 musb_writel(reg_base, USB_EP_INTR_CLEAR_REG,
541 USB_TX_INTR_MASK | USB_RX_INTR_MASK);
542 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
543 musb_writel(reg_base, USB_IRQ_EOI, 0);
544 }
546 #define POLL_SECONDS 2
548 static struct timer_list otg_workaround;
550 static void otg_timer(unsigned long _musb)
551 {
552 struct musb *musb = (void *)_musb;
553 void __iomem *mregs = musb->mregs;
554 u8 devctl;
555 unsigned long flags;
557 /* We poll because DaVinci's won't expose several OTG-critical
558 * status change events (from the transceiver) otherwise.
559 */
560 devctl = musb_readb(mregs, MUSB_DEVCTL);
561 DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
563 spin_lock_irqsave(&musb->lock, flags);
564 switch (musb->xceiv->state) {
565 case OTG_STATE_A_WAIT_BCON:
566 devctl &= ~MUSB_DEVCTL_SESSION;
567 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
569 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
570 if (devctl & MUSB_DEVCTL_BDEVICE) {
571 musb->xceiv->state = OTG_STATE_B_IDLE;
572 MUSB_DEV_MODE(musb);
573 } else {
574 musb->xceiv->state = OTG_STATE_A_IDLE;
575 MUSB_HST_MODE(musb);
576 }
577 break;
578 case OTG_STATE_A_WAIT_VFALL:
579 /*
580 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
581 * RTL seems to mis-handle session "start" otherwise (or in
582 * our case "recover"), in routine "VBUS was valid by the time
583 * VBUSERR got reported during enumeration" cases.
584 */
585 if (devctl & MUSB_DEVCTL_VBUS) {
586 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
587 break;
588 }
589 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
590 musb_writel(musb->ctrl_base, USB_CORE_INTR_SET_REG,
591 MUSB_INTR_VBUSERROR << USB_INTR_USB_SHIFT);
592 break;
593 case OTG_STATE_B_IDLE:
594 if (!is_peripheral_enabled(musb))
595 break;
597 /*
598 * There's no ID-changed IRQ, so we have no good way to tell
599 * when to switch to the A-Default state machine (by setting
600 * the DEVCTL.SESSION flag).
601 *
602 * Workaround: whenever we're in B_IDLE, try setting the
603 * session flag every few seconds. If it works, ID was
604 * grounded and we're now in the A-Default state machine.
605 *
606 * NOTE: setting the session flag is _supposed_ to trigger
607 * SRP but clearly it doesn't.
608 */
609 devctl = musb_readb(mregs, MUSB_DEVCTL);
610 if (devctl & MUSB_DEVCTL_BDEVICE)
611 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
612 else
613 musb->xceiv->state = OTG_STATE_A_IDLE;
614 break;
615 default:
616 break;
617 }
618 spin_unlock_irqrestore(&musb->lock, flags);
619 }
621 void ti81xx_musb_try_idle(struct musb *musb, unsigned long timeout)
622 {
623 static unsigned long last_timer;
625 if (!is_otg_enabled(musb))
626 return;
628 if (timeout == 0)
629 timeout = jiffies + msecs_to_jiffies(3);
631 /* Never idle if active, or when VBUS timeout is not set as host */
632 if (musb->is_active || (musb->a_wait_bcon == 0 &&
633 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
634 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
635 del_timer(&otg_workaround);
636 last_timer = jiffies;
637 return;
638 }
640 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
641 DBG(4, "Longer idle timer already pending, ignoring...\n");
642 return;
643 }
644 last_timer = timeout;
646 DBG(4, "%s inactive, starting idle timer for %u ms\n",
647 otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
648 mod_timer(&otg_workaround, timeout);
649 }
651 #ifdef CONFIG_USB_TI_CPPI41_DMA
652 static irqreturn_t cppi41dma_Interrupt(int irq, void *hci)
653 {
654 struct musb *musb = hci;
655 u32 intr_status;
656 irqreturn_t ret = IRQ_NONE;
657 u32 q_cmpl_status_0, q_cmpl_status_1, q_cmpl_status_2;
658 u32 usb0_tx_intr, usb0_rx_intr;
659 u32 usb1_tx_intr, usb1_rx_intr;
660 void *q_mgr_base = cppi41_queue_mgr[0].q_mgr_rgn_base;
661 unsigned long flags;
663 musb = hci;
664 /*
665 * CPPI 4.1 interrupts share the same IRQ and the EOI register but
666 * don't get reflected in the interrupt source/mask registers.
667 */
668 /*
669 * Check for the interrupts from Tx/Rx completion queues; they
670 * are level-triggered and will stay asserted until the queues
671 * are emptied. We're using the queue pending register 0 as a
672 * substitute for the interrupt status register and reading it
673 * directly for speed.
674 */
675 intr_status = usbss_read(USBSS_IRQ_STATUS);
677 if (intr_status)
678 usbss_write(USBSS_IRQ_STATUS, intr_status);
679 else
680 printk(KERN_DEBUG "spurious usbss intr\n");
681 q_cmpl_status_0 = musb_readl(q_mgr_base, 0x98);
682 q_cmpl_status_1 = musb_readl(q_mgr_base, 0x9c);
683 q_cmpl_status_2 = musb_readl(q_mgr_base, 0xa0);
685 /* USB0 tx/rx completion */
686 /* usb0 tx completion interrupt for ep1..15 */
687 usb0_tx_intr = (q_cmpl_status_0 >> 29) |
688 ((q_cmpl_status_1 & 0xFFF) << 3);
689 usb0_rx_intr = ((q_cmpl_status_1 & 0x07FFe000) >> 13);
691 usb1_tx_intr = (q_cmpl_status_1 >> 29) |
692 ((q_cmpl_status_2 & 0xFFF) << 3);
693 usb1_rx_intr = ((q_cmpl_status_2 & 0x0fffe000) >> 13);
695 /* get proper musb handle based usb0/usb1 ctrl-id */
697 DBG(4, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", usb0_tx_intr,
698 usb0_rx_intr);
699 if (usb0_tx_intr || usb0_rx_intr) {
700 spin_lock_irqsave(&gmusb[0]->lock, flags);
701 cppi41_completion(gmusb[0], usb0_rx_intr,
702 usb0_tx_intr);
703 spin_unlock_irqrestore(&gmusb[0]->lock, flags);
704 ret = IRQ_HANDLED;
705 }
707 DBG(4, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", usb1_tx_intr,
708 usb1_rx_intr);
709 if (usb1_rx_intr || usb1_tx_intr) {
710 spin_lock_irqsave(&gmusb[1]->lock, flags);
711 cppi41_completion(gmusb[1], usb1_rx_intr,
712 usb1_tx_intr);
713 spin_unlock_irqrestore(&gmusb[1]->lock, flags);
714 ret = IRQ_HANDLED;
715 }
716 usbss_write(USBSS_IRQ_EOI, 0);
718 return ret;
719 }
720 #endif
722 int musb_simulate_babble(struct musb *musb)
723 {
724 void __iomem *reg_base = musb->ctrl_base;
725 void __iomem *mbase = musb->mregs;
726 u8 reg;
728 /* during babble condition musb controller
729 * remove the session
730 */
731 reg = musb_readb(mbase, MUSB_DEVCTL);
732 reg &= ~MUSB_DEVCTL_SESSION;
733 musb_writeb(mbase, MUSB_DEVCTL, reg);
734 mdelay(100);
736 /* generate s/w babble interrupt */
737 musb_writel(reg_base, USB_IRQ_STATUS_RAW_1,
738 MUSB_INTR_BABBLE);
739 return 0;
740 }
741 EXPORT_SYMBOL(musb_simulate_babble);
743 void musb_babble_workaround(struct musb *musb)
744 {
745 void __iomem *reg_base = musb->ctrl_base;
746 struct device *dev = musb->controller;
747 struct musb_hdrc_platform_data *plat = dev->platform_data;
748 struct omap_musb_board_data *data = plat->board_data;
750 /* Reset the controller */
751 musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
752 udelay(100);
754 /* Shutdown the on-chip PHY and its PLL. */
755 if (data->set_phy_power)
756 data->set_phy_power(0);
757 udelay(100);
759 musb_platform_set_mode(musb, MUSB_HOST);
760 udelay(100);
762 /* enable the usbphy */
763 if (data->set_phy_power)
764 data->set_phy_power(1);
765 mdelay(100);
767 /* save the usbotgss register contents */
768 musb_platform_enable(musb);
770 musb_start(musb);
771 }
773 static void evm_deferred_musb_restart(struct work_struct *work)
774 {
775 struct musb *musb =
776 container_of(work, struct musb, work);
778 ERR("deferred musb restart musbid(%d)\n", musb->id);
779 musb_babble_workaround(musb);
780 }
782 static irqreturn_t ti81xx_interrupt(int irq, void *hci)
783 {
784 struct musb *musb = hci;
785 void __iomem *reg_base = musb->ctrl_base;
786 unsigned long flags;
787 irqreturn_t ret = IRQ_NONE;
788 u32 pend1 = 0, pend2 = 0;
789 u32 epintr, usbintr;
790 u8 is_babble = 0;
792 spin_lock_irqsave(&musb->lock, flags);
794 /* Acknowledge and handle non-CPPI interrupts */
795 /* Get endpoint interrupts */
796 epintr = musb_readl(reg_base, USB_EP_INTR_STATUS_REG);
797 musb->int_rx = (epintr & USB_RX_INTR_MASK) >> USB_INTR_RX_SHIFT;
798 musb->int_tx = (epintr & USB_TX_INTR_MASK) >> USB_INTR_TX_SHIFT;
799 if (epintr)
800 musb_writel(reg_base, USB_EP_INTR_STATUS_REG, epintr);
802 /* Get usb core interrupts */
803 usbintr = musb_readl(reg_base, USB_CORE_INTR_STATUS_REG);
804 if (!usbintr && !epintr) {
805 DBG(4, "sprious interrupt\n");
806 goto eoi;
807 }
809 if (usbintr)
810 musb_writel(reg_base, USB_CORE_INTR_STATUS_REG, usbintr);
811 musb->int_usb = (usbintr & USB_INTR_USB_MASK) >> USB_INTR_USB_SHIFT;
813 DBG(4, "usbintr (%x) epintr(%x)\n", usbintr, epintr);
814 /*
815 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
816 * AM3517's missing ID change IRQ. We need an ID change IRQ to
817 * switch appropriately between halves of the OTG state machine.
818 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
819 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
820 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
821 */
822 if ((usbintr & MUSB_INTR_BABBLE) && is_host_enabled(musb)) {
823 ERR("CAUTION: musb%d: Babble Interrupt Occured\n", musb->id);
824 ERR("Please issue long reset to make usb functional !!\n");
825 }
827 is_babble = is_host_capable() && (musb->int_usb & MUSB_INTR_BABBLE);
828 if (is_babble)
829 musb->int_usb |= MUSB_INTR_DISCONNECT;
831 if (usbintr & (USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT)) {
832 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
833 void __iomem *mregs = musb->mregs;
834 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
835 int err;
837 err = is_host_enabled(musb) && (musb->int_usb &
838 MUSB_INTR_VBUSERROR);
839 if (err) {
840 /*
841 * The Mentor core doesn't debounce VBUS as needed
842 * to cope with device connect current spikes. This
843 * means it's not uncommon for bus-powered devices
844 * to get VBUS errors during enumeration.
845 *
846 * This is a workaround, but newer RTL from Mentor
847 * seems to allow a better one: "re"-starting sessions
848 * without waiting for VBUS to stop registering in
849 * devctl.
850 */
851 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
852 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
853 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
854 WARNING("VBUS error workaround (delay coming)\n");
855 } else if (is_host_enabled(musb) && drvvbus) {
856 musb->is_active = 1;
857 MUSB_HST_MODE(musb);
858 musb->xceiv->default_a = 1;
859 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
860 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
861 del_timer(&otg_workaround);
862 } else {
863 musb->is_active = 0;
864 MUSB_DEV_MODE(musb);
865 musb->xceiv->default_a = 0;
866 musb->xceiv->state = OTG_STATE_B_IDLE;
867 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
868 }
870 /* NOTE: this must complete power-on within 100 ms. */
871 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
872 drvvbus ? "on" : "off",
873 otg_state_string(musb),
874 err ? " ERROR" : "",
875 devctl);
876 ret = IRQ_HANDLED;
877 }
879 if (musb->int_tx || musb->int_rx || musb->int_usb)
880 ret |= musb_interrupt(musb);
882 eoi:
883 /* EOI needs to be written for the IRQ to be re-asserted. */
884 if (ret == IRQ_HANDLED || epintr || usbintr) {
885 /* write EOI */
886 musb_writel(reg_base, USB_IRQ_EOI, 1);
887 }
889 /* Poll for ID change */
890 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
891 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
893 spin_unlock_irqrestore(&musb->lock, flags);
895 if (ret != IRQ_HANDLED) {
896 if (epintr || usbintr)
897 /*
898 * We sometimes get unhandled IRQs in the peripheral
899 * mode from EP0 and SOF...
900 */
901 DBG(2, "Unhandled USB IRQ %08x-%08x\n",
902 epintr, usbintr);
903 else if (printk_ratelimit())
904 /*
905 * We've seen series of spurious interrupts in the
906 * peripheral mode after USB reset and then after some
907 * time a real interrupt storm starting...
908 */
909 DBG(2, "Spurious IRQ, CPPI 4.1 status %08x, %08x\n",
910 pend1, pend2);
911 }
913 if (is_babble) {
914 if (!musb->enable_babble_work) {
915 musb_writeb(musb->mregs, MUSB_DEVCTL,
916 musb_readb(musb->mregs, MUSB_DEVCTL) |
917 MUSB_DEVCTL_SESSION);
918 } else {
919 ERR("Babble: devtcl(%x)Restarting musb....\n",
920 musb_readb(musb->mregs, MUSB_DEVCTL));
921 schedule_work(&musb->work);
922 }
923 }
924 return ret;
925 }
926 int ti81xx_musb_set_mode(struct musb *musb, u8 musb_mode)
927 {
928 void __iomem *reg_base = musb->ctrl_base;
930 /* TODO: implement this using CONF0 */
931 if (musb_mode == MUSB_HOST) {
932 musb_writel(reg_base, USB_MODE_REG, 0);
933 musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
934 DBG(4, "host: %s: value of mode reg=%x\n\n", __func__,
935 musb_readl(reg_base, USB_MODE_REG));
936 } else
937 if (musb_mode == MUSB_PERIPHERAL) {
938 /* TODO commmented writing 8 to USB_MODE_REG device
939 mode is not working */
940 musb_writel(reg_base, USB_MODE_REG, 0x100);
941 DBG(4, "device: %s: value of mode reg=%x\n\n", __func__,
942 musb_readl(reg_base, USB_MODE_REG));
943 } else
944 return -EIO;
945 return 0;
946 }
948 int ti81xx_musb_init(struct musb *musb)
949 {
950 void __iomem *reg_base = musb->ctrl_base;
951 struct device *dev = musb->controller;
952 struct musb_hdrc_platform_data *plat = dev->platform_data;
953 struct omap_musb_board_data *data = plat->board_data;
954 u32 rev, status = 0;
955 u8 mode;
957 if (musb->id < 2)
958 gmusb[musb->id] = musb;
960 usb_nop_xceiv_register(musb->id);
962 musb->xceiv = otg_get_transceiver(musb->id);
963 if (!musb->xceiv)
964 return -ENODEV;
966 status = pm_runtime_get_sync(dev);
967 if (status < 0) {
968 dev_err(dev, "pm_runtime_get_sync FAILED");
969 goto err1;
970 }
972 /* mentor is at offset of 0x400 in am3517/ti81xx */
973 musb->mregs += USB_MENTOR_CORE_OFFSET;
975 /* usb subsystem init */
976 usbotg_ss_init(musb);
978 /* Returns zero if e.g. not clocked */
979 rev = musb_readl(reg_base, USB_REVISION_REG);
980 if (!rev)
981 return -ENODEV;
983 if (is_host_enabled(musb))
984 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
986 /* Reset the controller */
987 musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
989 /* wait till reset bit clears */
990 while ((musb_readl(reg_base, USB_CTRL_REG) & 0x1))
991 cpu_relax();
993 /* Start the on-chip PHY and its PLL. */
994 if (data->set_phy_power)
995 data->set_phy_power(1);
997 msleep(5);
999 #ifdef CONFIG_USB_TI_CPPI41_DMA
1000 cppi41_init(musb);
1001 #endif
1003 musb->a_wait_bcon = A_WAIT_BCON_TIMEOUT;
1004 musb->isr = ti81xx_interrupt;
1006 #ifdef CONFIG_USB_MUSB_OTG
1007 if (musb->id == 1)
1008 mode = MUSB_HOST;
1009 else
1010 mode = MUSB_PERIPHERAL;
1011 #else
1012 /* set musb controller to host mode */
1013 if (is_host_enabled(musb))
1014 mode = MUSB_HOST;
1015 else
1016 mode = MUSB_PERIPHERAL;
1017 #endif
1019 /* set musb controller to host mode */
1020 musb_platform_set_mode(musb, mode);
1022 INIT_WORK(&musb->work, evm_deferred_musb_restart);
1023 musb->enable_babble_work = 0;
1025 musb_writel(reg_base, USB_IRQ_EOI, 0);
1026 usbss_write(USBSS_IRQ_EOI, 0);
1028 return 0;
1029 err1:
1030 pm_runtime_disable(dev);
1031 return status;
1032 }
1034 /* TI81xx supports only 32bit read operation */
1035 void ti81xx_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
1036 {
1037 void __iomem *fifo = hw_ep->fifo;
1038 u32 val;
1039 int i;
1041 /* Read for 32bit-aligned destination address */
1042 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
1043 readsl(fifo, dst, len >> 2);
1044 dst += len & ~0x03;
1045 len &= 0x03;
1046 }
1047 /*
1048 * Now read the remaining 1 to 3 byte or complete length if
1049 * unaligned address.
1050 */
1051 if (len > 4) {
1052 for (i = 0; i < (len >> 2); i++) {
1053 *(u32 *) dst = musb_readl(fifo, 0);
1054 dst += 4;
1055 }
1056 len &= 0x03;
1057 }
1058 if (len > 0) {
1059 val = musb_readl(fifo, 0);
1060 memcpy(dst, &val, len);
1061 }
1062 }
1064 int ti81xx_musb_exit(struct musb *musb)
1065 {
1066 struct device *dev = musb->controller;
1067 struct musb_hdrc_platform_data *plat = dev->platform_data;
1068 struct omap_musb_board_data *data = plat->board_data;
1070 if (is_host_enabled(musb))
1071 del_timer_sync(&otg_workaround);
1073 /* Shutdown the on-chip PHY and its PLL. */
1074 if (data->set_phy_power)
1075 data->set_phy_power(0);
1077 otg_put_transceiver(musb->xceiv);
1078 usb_nop_xceiv_unregister(musb->id);
1080 return 0;
1081 }
1083 static struct musb_platform_ops ti81xx_ops = {
1084 .fifo_mode = 4,
1085 .flags = MUSB_GLUE_EP_ADDR_FLAT_MAPPING | MUSB_GLUE_DMA_CPPI41,
1086 .init = ti81xx_musb_init,
1087 .exit = ti81xx_musb_exit,
1089 .enable = ti81xx_musb_enable,
1090 .disable = ti81xx_musb_disable,
1092 .try_idle = ti81xx_musb_try_idle,
1093 .set_mode = ti81xx_musb_set_mode,
1095 .read_fifo = ti81xx_musb_read_fifo,
1096 .write_fifo = musb_write_fifo,
1098 .dma_controller_create = cppi41_dma_controller_create,
1099 .dma_controller_destroy = cppi41_dma_controller_destroy,
1100 .simulate_babble_intr = musb_simulate_babble,
1101 };
1103 static int __init ti81xx_probe(struct platform_device *pdev)
1104 {
1105 struct ti81xx_glue *glue;
1106 struct platform_device *musb;
1107 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
1108 int ret;
1109 struct clk *otg_fck = NULL;
1111 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1112 if (!glue) {
1113 dev_err(&pdev->dev, "unable to allocate memory\n");
1114 return -ENOMEM;
1115 }
1117 dev_set_name(&pdev->dev, "musb-ti81xx");
1118 if (cpu_is_ti816x())
1119 glue->clk = clk_get(&pdev->dev, "usbotg_ick");
1120 else
1121 glue->clk = clk_get(&pdev->dev, "usb_ick");
1123 if (IS_ERR(glue->clk)) {
1124 dev_err(&pdev->dev, "unable to get clock\n");
1125 ret = PTR_ERR(glue->clk);
1126 goto err0;
1127 }
1129 musb = platform_device_alloc("musb-hdrc", pdev->id);
1130 if (!musb) {
1131 dev_err(&pdev->dev, "failed to allocate musb device\n");
1132 ret = -ENOMEM;
1133 goto err1;
1134 }
1136 musb->dev.parent = &pdev->dev;
1137 musb->dev.dma_mask = &musb_dmamask;
1138 musb->dev.coherent_dma_mask = musb_dmamask;
1140 glue->dev = &pdev->dev;
1141 glue->musb = musb;
1143 pdata->platform_ops = &ti81xx_ops;
1145 platform_set_drvdata(pdev, glue);
1146 ret = platform_device_add_resources(musb, pdev->resource,
1147 pdev->num_resources);
1148 if (ret) {
1149 dev_err(&pdev->dev, "failed to add resources\n");
1150 goto err3;
1151 }
1153 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
1154 if (ret) {
1155 dev_err(&pdev->dev, "failed to add platform_data\n");
1156 goto err2;
1157 }
1159 ret = clk_enable(glue->clk);
1160 if (ret) {
1161 dev_err(&pdev->dev, "failed to enable clock\n");
1162 goto err2;
1163 }
1165 /* Enable musb phy clock */
1166 if (cpu_is_ti816x())
1167 otg_fck = clk_get(NULL, "usbotg_ick");
1168 else if (cpu_is_ti814x() && musb->id == 0)
1169 otg_fck = clk_get(NULL, "usb_phy0_rclk_ick");
1170 else if (cpu_is_ti814x() && musb->id == 1)
1171 otg_fck = clk_get(NULL, "usb_phy1_rclk_ick");
1173 clk_enable(otg_fck);
1174 DBG(2, "usbotg_phy_ck=%lud\n", clk_get_rate(otg_fck));
1176 platform_set_drvdata(pdev, glue);
1177 glue->dev = &pdev->dev;
1178 glue->phy_clk = otg_fck;
1180 ret = platform_device_add(musb);
1181 if (ret) {
1182 dev_err(&pdev->dev, "failed to register musb device\n");
1183 goto err3;
1184 }
1186 return 0;
1188 err3:
1189 clk_disable(glue->clk);
1191 err2:
1192 platform_device_put(musb);
1194 err1:
1195 clk_put(glue->clk);
1197 err0:
1198 kfree(glue);
1200 return ret;
1201 }
1203 static int __exit ti81xx_remove(struct platform_device *pdev)
1204 {
1205 struct ti81xx_glue *glue = platform_get_drvdata(pdev);
1207 platform_device_del(glue->musb);
1208 platform_device_put(glue->musb);
1209 clk_disable(glue->clk);
1210 clk_disable(glue->phy_clk);
1211 clk_put(glue->clk);
1212 clk_put(glue->phy_clk);
1213 kfree(glue);
1215 return 0;
1216 }
1218 #ifdef CONFIG_PM
1219 static int ti81xx_suspend(struct device *dev)
1220 {
1221 struct ti81xx_glue *glue = dev_get_drvdata(dev);
1222 struct musb_hdrc_platform_data *plat = dev->platform_data;
1223 struct omap_musb_board_data *data = plat->board_data;
1224 int i;
1226 /* Shutdown the on-chip PHY and its PLL. */
1227 for (i = 0; i <= data->instances; ++i) {
1228 if (data->set_phy_power)
1229 data->set_phy_power(i);
1230 }
1232 /* disable the common usbss interface clock */
1233 clk_disable(glue->ick);
1234 return 0;
1235 }
1237 static int ti81xx_resume(struct device *dev)
1238 {
1239 struct ti81xx_glue *glue = dev_get_drvdata(dev);
1240 struct musb_hdrc_platform_data *plat = dev->platform_data;
1241 struct omap_musb_board_data *data = plat->board_data;
1242 int ret, i;
1244 /* Start the on-chip PHY and its PLL. */
1245 for (i = 0; i <= data->instances; ++i) {
1246 if (data->set_phy_power)
1247 data->set_phy_power(i);
1248 }
1250 /* enable the common usbss interface clock */
1251 ret = clk_enable(glue->ick);
1252 if (ret) {
1253 dev_err(dev, "failed to enable iclock\n");
1254 return ret;
1255 }
1256 /* enable the common usbss functional clock */
1257 ret = clk_enable(glue->fck);
1258 if (ret) {
1259 dev_err(dev, "failed to enable fclock\n");
1260 return ret;
1261 }
1262 return 0;
1263 }
1265 static const struct dev_pm_ops ti81xx_pm_ops = {
1266 .suspend = ti81xx_suspend,
1267 .resume = ti81xx_resume,
1268 };
1270 #define DEV_PM_OPS (&ti81xx_pm_ops)
1271 #else
1272 #define DEV_PM_OPS NULL
1273 #endif
1275 static struct platform_driver ti81xx_musb_driver = {
1276 .remove = __exit_p(ti81xx_remove),
1277 .driver = {
1278 .name = "musb-ti81xx",
1279 .pm = DEV_PM_OPS,
1280 },
1281 };
1283 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1284 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
1285 MODULE_LICENSE("GPL v2");
1287 static int __init ti81xx_glue_init(void)
1288 {
1289 return platform_driver_probe(&ti81xx_musb_driver, ti81xx_probe);
1290 }
1291 subsys_initcall(ti81xx_glue_init);
1293 static void __exit ti81xx_glue_exit(void)
1294 {
1295 #ifdef CONFIG_USB_TI_CPPI41_DMA
1296 cppi41_exit();
1297 cppi41_free();
1298 #endif
1299 platform_driver_unregister(&ti81xx_musb_driver);
1300 }
1301 module_exit(ti81xx_glue_exit);
1303 #ifdef CONFIG_PM
1304 void musb_platform_save_context(struct musb *musb,
1305 struct musb_context_registers *musb_context)
1306 {
1307 /* Save CPPI41 DMA related registers */
1308 }
1310 void musb_platform_restore_context(struct musb *musb,
1311 struct musb_context_registers *musb_context)
1312 {
1313 /* Restore CPPI41 DMA related registers */
1314 }
1315 #endif