1 /*
2 * Texas Instruments TI81XX "usb platform glue layer"
3 *
4 * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * Based on the DaVinci "glue layer" code.
7 * Copyright (C) 2005-2006 by Texas Instruments
8 *
9 * This file is part of the Inventra Controller Driver for Linux.
10 *
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
14 * Foundation.
15 *
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
29 #include <linux/init.h>
30 #include <linux/clk.h>
31 #include <linux/io.h>
32 #include <linux/usb/otg.h>
33 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/module.h>
37 #include "cppi41.h"
38 #include "ti81xx.h"
40 #include "musb_core.h"
41 #include "cppi41_dma.h"
43 struct ti81xx_glue {
44 struct device *dev;
45 struct clk *ick; /* common usbss interface clk */
46 struct clk *fck; /* common usbss functional clk */
47 struct resource *mem_pa; /* usbss memory resource */
48 void *mem_va; /* ioremapped virtual address */
49 struct platform_device *musb[2];/* child musb pdevs */
50 u8 irq; /* usbss irq */
51 };
52 static u64 musb_dmamask = DMA_BIT_MASK(32);
53 static void *usbss_virt_base;
54 static u8 usbss_init_done;
55 struct musb *gmusb[2];
57 u8 usbid_sw_ctrl;
58 #undef USB_TI81XX_DEBUG
60 #ifdef USB_TI81XX_DEBUG
61 #define dprintk(x, ...) printk(x, ## __VA_ARGS__)
62 #else
63 #define dprintk(x, ...)
64 #endif
66 #ifdef CONFIG_USB_TI_CPPI41_DMA
67 static irqreturn_t cppi41dma_Interrupt(int irq, void *hci);
68 static u8 cppi41_init_done;
69 static void *cppi41_dma_base;
70 #define CPPI41_ADDR(offs) ((void *)((u32)cppi41_dma_base + (offs - 0x2000)))
71 #endif
73 extern void omap_ctrl_writel(u32 val, u16 offset);
74 extern u32 omap_ctrl_readl(u16 offset);
76 static inline u32 usbss_read(u32 offset)
77 {
78 if (!usbss_init_done)
79 return 0;
80 return __raw_readl(usbss_virt_base + offset);
81 }
83 static inline void usbss_write(u32 offset, u32 data)
84 {
85 if (!usbss_init_done)
86 return ;
87 __raw_writel(data, usbss_virt_base + offset);
88 }
90 static void usbotg_ss_init(void)
91 {
92 if (!usbss_init_done) {
93 /* reset the usbss for usb0/usb1 */
94 usbss_write(USBSS_SYSCONFIG,
95 usbss_read(USBSS_SYSCONFIG) | USB_SOFT_RESET_MASK);
97 /* clear any USBSS interrupts */
98 usbss_write(USBSS_IRQ_EOI, 0);
99 usbss_write(USBSS_IRQ_STATUS, usbss_read(USBSS_IRQ_STATUS));
100 usbss_init_done = 1;
101 }
102 }
103 static void usbotg_ss_uninit(void)
104 {
105 if (usbss_init_done) {
106 usbss_init_done = 0;
107 usbss_virt_base = 0;
108 }
109 }
110 void set_frame_threshold(u8 musb_id, u8 is_tx, u8 epnum, u8 value, u8 en_intr)
111 {
112 u32 base, reg_val, frame_intr = 0, frame_base = 0;
113 u32 offs = epnum/4*4;
114 u8 indx = (epnum % 4) * 8;
116 if (is_tx)
117 base = musb_id ? USBSS_IRQ_FRAME_THRESHOLD_TX1 :
118 USBSS_IRQ_FRAME_THRESHOLD_TX0;
119 else
120 base = musb_id ? USBSS_IRQ_FRAME_THRESHOLD_RX1 :
121 USBSS_IRQ_FRAME_THRESHOLD_RX0;
123 reg_val = usbss_read(base + offs);
124 reg_val &= ~(0xFF << indx);
125 reg_val |= (value << indx);
126 usbss_write(base + offs, reg_val);
128 if (en_intr) {
129 frame_base = musb_id ? USBSS_IRQ_FRAME_ENABLE_1 :
130 USBSS_IRQ_FRAME_ENABLE_0;
131 frame_intr = musb_id ? usbss_read(USBSS_IRQ_FRAME_ENABLE_0) :
132 usbss_read(USBSS_IRQ_FRAME_ENABLE_1);
133 frame_intr |= is_tx ? (1 << epnum) : (1 << (16 + epnum));
134 usbss_write(frame_base, frame_intr);
135 DBG(4, "%s: framebase=%x, frame_intr=%x\n", is_tx ? "tx" : "rx",
136 frame_base, frame_intr);
137 }
138 }
140 void set_dma_threshold(u8 musb_id, u8 is_tx, u8 epnum, u8 value)
141 {
142 u32 base, reg_val;
143 u32 offs = epnum/4*4;
144 u8 indx = (epnum % 4) * 8;
146 if (musb_id == 0)
147 base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX0 :
148 USBSS_IRQ_DMA_THRESHOLD_RX0;
149 else
150 base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX1 :
151 USBSS_IRQ_DMA_THRESHOLD_RX1;
153 reg_val = usbss_read(base + offs);
154 reg_val &= ~(0xFF << indx);
155 reg_val |= (value << indx);
156 DBG(4, "base=%x, offs=%x, indx=%d, reg_val = (%x)%x\n",
157 base, offs, indx, reg_val, usbss_read(base + offs));
158 usbss_write(base + offs, reg_val);
159 }
161 /* ti81xx specific read/write functions */
162 u16 ti81xx_musb_readw(const void __iomem *addr, unsigned offset)
163 {
164 u32 tmp;
165 u16 val;
167 tmp = __raw_readl(addr + (offset & ~3));
169 switch (offset & 0x3) {
170 case 0:
171 val = (tmp & 0xffff);
172 break;
173 case 1:
174 val = (tmp >> 8) & 0xffff;
175 break;
176 case 2:
177 case 3:
178 default:
179 val = (tmp >> 16) & 0xffff;
180 break;
181 }
182 return val;
183 }
185 void ti81xx_musb_writew(void __iomem *addr, unsigned offset, u16 data)
186 {
187 __raw_writew(data, addr + offset);
188 }
190 u8 ti81xx_musb_readb(const void __iomem *addr, unsigned offset)
191 {
192 u32 tmp;
193 u8 val;
195 tmp = __raw_readl(addr + (offset & ~3));
197 switch (offset & 0x3) {
198 case 0:
199 val = tmp & 0xff;
200 break;
201 case 1:
202 val = (tmp >> 8);
203 break;
204 case 2:
205 val = (tmp >> 16);
206 break;
207 case 3:
208 default:
209 val = (tmp >> 24);
210 break;
211 }
212 return val;
213 }
214 void ti81xx_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
215 {
216 __raw_writeb(data, addr + offset);
217 }
219 #ifdef CONFIG_USB_TI_CPPI41_DMA
220 /*
221 * CPPI 4.1 resources used for USB OTG controller module:
222 *
223 tx/rx completion queues for usb0 */
224 static u16 tx_comp_q[] = {93, 94, 95, 96, 97,
225 98, 99, 100, 101, 102,
226 103, 104, 105, 106, 107 };
228 static u16 rx_comp_q[] = {109, 110, 111, 112, 113,
229 114, 115, 116, 117, 118,
230 119, 120, 121, 122, 123 };
232 /* tx/rx completion queues for usb1 */
233 static u16 tx_comp_q1[] = {125, 126, 127, 128, 129,
234 130, 131, 132, 133, 134,
235 135, 136, 137, 138, 139 };
237 static u16 rx_comp_q1[] = {141, 142, 143, 144, 145,
238 146, 147, 148, 149, 150,
239 151, 152, 153, 154, 155 };
241 /* Fair scheduling */
242 u32 dma_sched_table[] = {
243 0x81018000, 0x83038202, 0x85058404, 0x87078606,
244 0x89098808, 0x8b0b8a0a, 0x8d0d8c0c, 0x8f0f8e0e,
245 0x91119010, 0x93139212, 0x95159414, 0x97179616,
246 0x99199818, 0x9b1b9a1a, 0x9d1d9c1c, 0x00009e1e,
247 };
249 /* cppi41 dma tx channel info */
250 static const struct cppi41_tx_ch tx_ch_info[] = {
251 [0] = {
252 .port_num = 1,
253 .num_tx_queue = 2,
254 .tx_queue = { {0, 32} , {0, 33} }
255 },
256 [1] = {
257 .port_num = 2,
258 .num_tx_queue = 2,
259 .tx_queue = { {0, 34} , {0, 35} }
260 },
261 [2] = {
262 .port_num = 3,
263 .num_tx_queue = 2,
264 .tx_queue = { {0, 36} , {0, 37} }
265 },
266 [3] = {
267 .port_num = 4,
268 .num_tx_queue = 2,
269 .tx_queue = { {0, 38} , {0, 39} }
270 },
271 [4] = {
272 .port_num = 5,
273 .num_tx_queue = 2,
274 .tx_queue = { {0, 40} , {0, 41} }
275 },
276 [5] = {
277 .port_num = 6,
278 .num_tx_queue = 2,
279 .tx_queue = { {0, 42} , {0, 43} }
280 },
281 [6] = {
282 .port_num = 7,
283 .num_tx_queue = 2,
284 .tx_queue = { {0, 44} , {0, 45} }
285 },
286 [7] = {
287 .port_num = 8,
288 .num_tx_queue = 2,
289 .tx_queue = { {0, 46} , {0, 47} }
290 },
291 [8] = {
292 .port_num = 9,
293 .num_tx_queue = 2,
294 .tx_queue = { {0, 48} , {0, 49} }
295 },
296 [9] = {
297 .port_num = 10,
298 .num_tx_queue = 2,
299 .tx_queue = { {0, 50} , {0, 51} }
300 },
301 [10] = {
302 .port_num = 11,
303 .num_tx_queue = 2,
304 .tx_queue = { {0, 52} , {0, 53} }
305 },
306 [11] = {
307 .port_num = 12,
308 .num_tx_queue = 2,
309 .tx_queue = { {0, 54} , {0, 55} }
310 },
311 [12] = {
312 .port_num = 13,
313 .num_tx_queue = 2,
314 .tx_queue = { {0, 56} , {0, 57} }
315 },
316 [13] = {
317 .port_num = 14,
318 .num_tx_queue = 2,
319 .tx_queue = { {0, 58} , {0, 59} }
320 },
321 [14] = {
322 .port_num = 15,
323 .num_tx_queue = 2,
324 .tx_queue = { {0, 60} , {0, 61} }
325 },
326 [15] = {
327 .port_num = 1,
328 .num_tx_queue = 2,
329 .tx_queue = { {0, 62} , {0, 63} }
330 },
331 [16] = {
332 .port_num = 2,
333 .num_tx_queue = 2,
334 .tx_queue = { {0, 64} , {0, 65} }
335 },
336 [17] = {
337 .port_num = 3,
338 .num_tx_queue = 2,
339 .tx_queue = { {0, 66} , {0, 67} }
340 },
341 [18] = {
342 .port_num = 4,
343 .num_tx_queue = 2,
344 .tx_queue = { {0, 68} , {0, 69} }
345 },
346 [19] = {
347 .port_num = 5,
348 .num_tx_queue = 2,
349 .tx_queue = { {0, 70} , {0, 71} }
350 },
351 [20] = {
352 .port_num = 6,
353 .num_tx_queue = 2,
354 .tx_queue = { {0, 72} , {0, 73} }
355 },
356 [21] = {
357 .port_num = 7,
358 .num_tx_queue = 2,
359 .tx_queue = { {0, 74} , {0, 75} }
360 },
361 [22] = {
362 .port_num = 8,
363 .num_tx_queue = 2,
364 .tx_queue = { {0, 76} , {0, 77} }
365 },
366 [23] = {
367 .port_num = 9,
368 .num_tx_queue = 2,
369 .tx_queue = { {0, 78} , {0, 79} }
370 },
371 [24] = {
372 .port_num = 10,
373 .num_tx_queue = 2,
374 .tx_queue = { {0, 80} , {0, 81} }
375 },
376 [25] = {
377 .port_num = 11,
378 .num_tx_queue = 2,
379 .tx_queue = { {0, 82} , {0, 83} }
380 },
381 [26] = {
382 .port_num = 12,
383 .num_tx_queue = 2,
384 .tx_queue = { {0, 84} , {0, 85} }
385 },
386 [27] = {
387 .port_num = 13,
388 .num_tx_queue = 2,
389 .tx_queue = { {0, 86} , {0, 87} }
390 },
391 [28] = {
392 .port_num = 14,
393 .num_tx_queue = 2,
394 .tx_queue = { {0, 88} , {0, 89} }
395 },
396 [29] = {
397 .port_num = 15,
398 .num_tx_queue = 2,
399 .tx_queue = { {0, 90} , {0, 91} }
400 }
401 };
403 /* Queues 0 to 66 are pre-assigned, others are spare */
404 static const u32 assigned_queues[] = { 0xffffffff, /* queue 0..31 */
405 0xffffffff, /* queue 32..63 */
406 0xffffffff, /* queue 64..95 */
407 0xffffffff, /* queue 96..127 */
408 0x0fffffff /* queue 128..155 */
409 };
411 int __devinit cppi41_init(u8 id, u8 irq)
412 {
413 struct usb_cppi41_info *cppi_info = &usb_cppi41_info[id];
414 u16 numch, blknum, order;
415 u32 i;
417 /* init cppi info structure */
418 cppi_info->dma_block = 0;
419 for (i = 0 ; i < USB_CPPI41_NUM_CH ; i++)
420 cppi_info->ep_dma_ch[i] = i + (15 * id);
422 cppi_info->q_mgr = 0;
423 cppi_info->num_tx_comp_q = 15;
424 cppi_info->num_rx_comp_q = 15;
425 cppi_info->tx_comp_q = id ? tx_comp_q1 : tx_comp_q;
426 cppi_info->rx_comp_q = id ? rx_comp_q1 : rx_comp_q;
427 cppi_info->bd_intr_ctrl = 1;
429 if (cppi41_init_done)
430 return 0;
432 blknum = cppi_info->dma_block;
434 /* Queue manager information */
435 cppi41_queue_mgr[0].num_queue = 159;
436 cppi41_queue_mgr[0].queue_types = CPPI41_FREE_DESC_BUF_QUEUE |
437 CPPI41_UNASSIGNED_QUEUE;
438 cppi41_queue_mgr[0].base_fdbq_num = 0;
439 cppi41_queue_mgr[0].assigned = assigned_queues;
441 /* init DMA block */
442 cppi41_dma_block[0].num_tx_ch = 30;
443 cppi41_dma_block[0].num_rx_ch = 30;
444 cppi41_dma_block[0].tx_ch_info = tx_ch_info;
446 /* initilize cppi41 dma & Qmgr address */
447 cppi41_dma_base = ioremap(TI81XX_USB_CPPIDMA_BASE,
448 TI81XX_USB_CPPIDMA_LEN);
450 cppi41_queue_mgr[0].q_mgr_rgn_base = CPPI41_ADDR(QMGR_RGN_OFFS);
451 cppi41_queue_mgr[0].desc_mem_rgn_base = CPPI41_ADDR(QMRG_DESCRGN_OFFS);
452 cppi41_queue_mgr[0].q_mgmt_rgn_base = CPPI41_ADDR(QMGR_REG_OFFS);
453 cppi41_queue_mgr[0].q_stat_rgn_base = CPPI41_ADDR(QMGR_STAT_OFFS);
454 cppi41_dma_block[0].global_ctrl_base = CPPI41_ADDR(DMA_GLBCTRL_OFFS);
455 cppi41_dma_block[0].ch_ctrl_stat_base = CPPI41_ADDR(DMA_CHCTRL_OFFS);
456 cppi41_dma_block[0].sched_ctrl_base = CPPI41_ADDR(DMA_SCHED_OFFS);
457 cppi41_dma_block[0].sched_table_base = CPPI41_ADDR(DMA_SCHEDTBL_OFFS);
459 /* Initialize for Linking RAM region 0 alone */
460 cppi41_queue_mgr_init(cppi_info->q_mgr, 0, 0x3fff);
462 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
463 numch = USB_CPPI41_NUM_CH * 2;
464 #else
465 numch = USB_CPPI41_NUM_CH * 2 * 2;
466 #endif
467 order = get_count_order(numch);
469 /* TODO: check two teardown desc per channel (5 or 7 ?)*/
470 if (order < 5)
471 order = 5;
473 cppi41_dma_block_init(blknum, cppi_info->q_mgr, order,
474 dma_sched_table, numch);
476 /* attach to the IRQ */
477 if (request_irq(irq, cppi41dma_Interrupt, 0, "cppi41_dma", 0))
478 printk(KERN_INFO "request_irq %d failed!\n", irq);
479 else
480 printk(KERN_INFO "registerd cppi-dma Intr @ IRQ %d\n", irq);
482 cppi41_init_done = 1;
484 DBG(4, "Cppi41 Init Done Qmgr-base(%p) dma-base(%p)\n",
485 cppi41_queue_mgr[0].q_mgr_rgn_base,
486 cppi41_dma_block[0].global_ctrl_base);
488 /* enable all usbss the interrupts */
489 usbss_write(USBSS_IRQ_EOI, 0);
490 usbss_write(USBSS_IRQ_ENABLE_SET, USBSS_INTR_FLAGS);
491 usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0xFFFeFFFe);
493 printk(KERN_INFO "Cppi41 Init Done\n");
495 return 0;
496 }
498 void cppi41_free(void)
499 {
500 u32 numch, blknum, order;
501 struct usb_cppi41_info *cppi_info = &usb_cppi41_info[0];
503 if (!cppi41_init_done)
504 return ;
506 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
507 numch = USB_CPPI41_NUM_CH * 2;
508 #else
509 numch = USB_CPPI41_NUM_CH * 2 * 2;
510 #endif
511 order = get_count_order(numch);
512 blknum = cppi_info->dma_block;
514 cppi41_dma_block_uninit(blknum, cppi_info->q_mgr, order,
515 dma_sched_table, numch);
516 cppi41_queue_mgr_uninit(cppi_info->q_mgr);
518 iounmap(cppi41_dma_base);
519 cppi41_dma_base = 0;
520 cppi41_init_done = 0;
521 }
523 int cppi41_disable_sched_rx(void)
524 {
525 cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
526 return 0;
527 }
529 int cppi41_enable_sched_rx(void)
530 {
531 cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
532 return 0;
533 }
534 #endif /* CONFIG_USB_TI_CPPI41_DMA */
536 /*
537 * Because we don't set CTRL.UINT, it's "important" to:
538 * - not read/write INTRUSB/INTRUSBE (except during
539 * initial setup, as a workaround);
540 * - use INTSET/INTCLR instead.
541 */
543 /**
544 * ti81xx_musb_enable - enable interrupts
545 */
546 void ti81xx_musb_enable(struct musb *musb)
547 {
548 void __iomem *reg_base = musb->ctrl_base;
549 u32 epmask, coremask;
551 /* Workaround: setup IRQs through both register sets. */
552 epmask = ((musb->epmask & USB_TX_EP_MASK) << USB_INTR_TX_SHIFT) |
553 ((musb->epmask & USB_RX_EP_MASK) << USB_INTR_RX_SHIFT);
554 coremask = (0x01ff << USB_INTR_USB_SHIFT);
556 coremask &= ~MUSB_INTR_SOF;
558 musb_writel(reg_base, USB_EP_INTR_SET_REG, epmask);
559 musb_writel(reg_base, USB_CORE_INTR_SET_REG, coremask);
560 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
561 if (is_otg_enabled(musb))
562 musb_writel(reg_base, USB_CORE_INTR_SET_REG,
563 USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT);
564 }
566 /**
567 * ti81xx_musb_disable - disable HDRC and flush interrupts
568 */
569 void ti81xx_musb_disable(struct musb *musb)
570 {
571 void __iomem *reg_base = musb->ctrl_base;
573 musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, USB_INTR_USB_MASK);
574 musb_writel(reg_base, USB_EP_INTR_CLEAR_REG,
575 USB_TX_INTR_MASK | USB_RX_INTR_MASK);
576 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
577 musb_writel(reg_base, USB_IRQ_EOI, 0);
578 }
580 #define POLL_SECONDS 2
582 static struct timer_list otg_workaround;
584 static void otg_timer(unsigned long _musb)
585 {
586 struct musb *musb = (void *)_musb;
587 void __iomem *mregs = musb->mregs;
588 u8 devctl;
589 unsigned long flags;
591 /* We poll because DaVinci's won't expose several OTG-critical
592 * status change events (from the transceiver) otherwise.
593 */
594 devctl = musb_readb(mregs, MUSB_DEVCTL);
595 DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
597 spin_lock_irqsave(&musb->lock, flags);
598 switch (musb->xceiv->state) {
599 case OTG_STATE_A_WAIT_BCON:
600 devctl &= ~MUSB_DEVCTL_SESSION;
601 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
603 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
604 if (devctl & MUSB_DEVCTL_BDEVICE) {
605 musb->xceiv->state = OTG_STATE_B_IDLE;
606 MUSB_DEV_MODE(musb);
607 } else {
608 musb->xceiv->state = OTG_STATE_A_IDLE;
609 MUSB_HST_MODE(musb);
610 }
611 break;
612 case OTG_STATE_A_WAIT_VFALL:
613 /*
614 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
615 * RTL seems to mis-handle session "start" otherwise (or in
616 * our case "recover"), in routine "VBUS was valid by the time
617 * VBUSERR got reported during enumeration" cases.
618 */
619 if (devctl & MUSB_DEVCTL_VBUS) {
620 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
621 break;
622 }
623 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
624 musb_writel(musb->ctrl_base, USB_CORE_INTR_SET_REG,
625 MUSB_INTR_VBUSERROR << USB_INTR_USB_SHIFT);
626 break;
627 case OTG_STATE_B_IDLE:
628 if (!is_peripheral_enabled(musb))
629 break;
631 /*
632 * There's no ID-changed IRQ, so we have no good way to tell
633 * when to switch to the A-Default state machine (by setting
634 * the DEVCTL.SESSION flag).
635 *
636 * Workaround: whenever we're in B_IDLE, try setting the
637 * session flag every few seconds. If it works, ID was
638 * grounded and we're now in the A-Default state machine.
639 *
640 * NOTE: setting the session flag is _supposed_ to trigger
641 * SRP but clearly it doesn't.
642 */
643 devctl = musb_readb(mregs, MUSB_DEVCTL);
644 if (devctl & MUSB_DEVCTL_BDEVICE)
645 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
646 else
647 musb->xceiv->state = OTG_STATE_A_IDLE;
648 break;
649 default:
650 break;
651 }
652 spin_unlock_irqrestore(&musb->lock, flags);
653 }
655 void ti81xx_musb_try_idle(struct musb *musb, unsigned long timeout)
656 {
657 static unsigned long last_timer;
659 if (!is_otg_enabled(musb))
660 return;
662 if (timeout == 0)
663 timeout = jiffies + msecs_to_jiffies(3);
665 /* Never idle if active, or when VBUS timeout is not set as host */
666 if (musb->is_active || (musb->a_wait_bcon == 0 &&
667 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
668 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
669 del_timer(&otg_workaround);
670 last_timer = jiffies;
671 return;
672 }
674 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
675 DBG(4, "Longer idle timer already pending, ignoring...\n");
676 return;
677 }
678 last_timer = timeout;
680 DBG(4, "%s inactive, starting idle timer for %u ms\n",
681 otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
682 mod_timer(&otg_workaround, timeout);
683 }
685 #ifdef CONFIG_USB_TI_CPPI41_DMA
686 static irqreturn_t cppi41dma_Interrupt(int irq, void *hci)
687 {
688 struct musb *musb = hci;
689 u32 intr_status;
690 irqreturn_t ret = IRQ_NONE;
691 u32 q_cmpl_status_0, q_cmpl_status_1, q_cmpl_status_2;
692 u32 usb0_tx_intr, usb0_rx_intr;
693 u32 usb1_tx_intr, usb1_rx_intr;
694 void *q_mgr_base = cppi41_queue_mgr[0].q_mgr_rgn_base;
695 unsigned long flags;
697 musb = hci;
698 /*
699 * CPPI 4.1 interrupts share the same IRQ and the EOI register but
700 * don't get reflected in the interrupt source/mask registers.
701 */
702 /*
703 * Check for the interrupts from Tx/Rx completion queues; they
704 * are level-triggered and will stay asserted until the queues
705 * are emptied. We're using the queue pending register 0 as a
706 * substitute for the interrupt status register and reading it
707 * directly for speed.
708 */
709 intr_status = usbss_read(USBSS_IRQ_STATUS);
711 if (intr_status)
712 usbss_write(USBSS_IRQ_STATUS, intr_status);
713 else
714 printk(KERN_DEBUG "spurious usbss intr\n");
716 q_cmpl_status_0 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG2);
717 q_cmpl_status_1 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG3);
718 q_cmpl_status_2 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG4);
720 /* USB0 tx/rx completion */
721 /* usb0 tx completion interrupt for ep1..15 */
722 usb0_tx_intr = (q_cmpl_status_0 >> 29) |
723 ((q_cmpl_status_1 & 0xFFF) << 3);
724 usb0_rx_intr = ((q_cmpl_status_1 & 0x07FFe000) >> 13);
726 usb1_tx_intr = (q_cmpl_status_1 >> 29) |
727 ((q_cmpl_status_2 & 0xFFF) << 3);
728 usb1_rx_intr = ((q_cmpl_status_2 & 0x0fffe000) >> 13);
730 /* get proper musb handle based usb0/usb1 ctrl-id */
732 DBG(4, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", usb0_tx_intr,
733 usb0_rx_intr);
734 if (gmusb[0] && (usb0_tx_intr || usb0_rx_intr)) {
735 spin_lock_irqsave(&gmusb[0]->lock, flags);
736 cppi41_completion(gmusb[0], usb0_rx_intr,
737 usb0_tx_intr);
738 spin_unlock_irqrestore(&gmusb[0]->lock, flags);
739 ret = IRQ_HANDLED;
740 }
742 DBG(4, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", usb1_tx_intr,
743 usb1_rx_intr);
744 if (gmusb[1] && (usb1_rx_intr || usb1_tx_intr)) {
745 spin_lock_irqsave(&gmusb[1]->lock, flags);
746 cppi41_completion(gmusb[1], usb1_rx_intr,
747 usb1_tx_intr);
748 spin_unlock_irqrestore(&gmusb[1]->lock, flags);
749 ret = IRQ_HANDLED;
750 }
751 usbss_write(USBSS_IRQ_EOI, 0);
753 return ret;
754 }
755 #endif
757 int musb_simulate_babble(struct musb *musb)
758 {
759 void __iomem *reg_base = musb->ctrl_base;
760 void __iomem *mbase = musb->mregs;
761 u8 reg;
763 /* during babble condition musb controller
764 * remove the session
765 */
766 reg = musb_readb(mbase, MUSB_DEVCTL);
767 reg &= ~MUSB_DEVCTL_SESSION;
768 musb_writeb(mbase, MUSB_DEVCTL, reg);
769 mdelay(100);
771 /* generate s/w babble interrupt */
772 musb_writel(reg_base, USB_IRQ_STATUS_RAW_1,
773 MUSB_INTR_BABBLE);
774 return 0;
775 }
776 EXPORT_SYMBOL(musb_simulate_babble);
778 void musb_babble_workaround(struct musb *musb)
779 {
780 void __iomem *reg_base = musb->ctrl_base;
781 struct device *dev = musb->controller;
782 struct musb_hdrc_platform_data *plat = dev->platform_data;
783 struct omap_musb_board_data *data = plat->board_data;
785 /* Reset the controller */
786 musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
787 udelay(100);
789 /* Shutdown the on-chip PHY and its PLL. */
790 if (data->set_phy_power)
791 data->set_phy_power(0);
792 udelay(100);
794 musb_platform_set_mode(musb, MUSB_HOST);
795 udelay(100);
797 /* enable the usbphy */
798 if (data->set_phy_power)
799 data->set_phy_power(1);
800 mdelay(100);
802 /* save the usbotgss register contents */
803 musb_platform_enable(musb);
805 musb_start(musb);
806 }
808 static void evm_deferred_musb_restart(struct work_struct *work)
809 {
810 struct musb *musb =
811 container_of(work, struct musb, work);
813 ERR("deferred musb restart musbid(%d)\n", musb->id);
814 musb_babble_workaround(musb);
815 }
817 static irqreturn_t ti81xx_interrupt(int irq, void *hci)
818 {
819 struct musb *musb = hci;
820 void __iomem *reg_base = musb->ctrl_base;
821 unsigned long flags;
822 irqreturn_t ret = IRQ_NONE;
823 u32 pend1 = 0, pend2 = 0;
824 u32 epintr, usbintr;
825 u8 is_babble = 0;
827 spin_lock_irqsave(&musb->lock, flags);
829 /* Acknowledge and handle non-CPPI interrupts */
830 /* Get endpoint interrupts */
831 epintr = musb_readl(reg_base, USB_EP_INTR_STATUS_REG);
832 musb->int_rx = (epintr & USB_RX_INTR_MASK) >> USB_INTR_RX_SHIFT;
833 musb->int_tx = (epintr & USB_TX_INTR_MASK) >> USB_INTR_TX_SHIFT;
834 if (epintr)
835 musb_writel(reg_base, USB_EP_INTR_STATUS_REG, epintr);
837 /* Get usb core interrupts */
838 usbintr = musb_readl(reg_base, USB_CORE_INTR_STATUS_REG);
839 if (!usbintr && !epintr) {
840 DBG(4, "sprious interrupt\n");
841 goto eoi;
842 }
844 if (usbintr)
845 musb_writel(reg_base, USB_CORE_INTR_STATUS_REG, usbintr);
846 musb->int_usb = (usbintr & USB_INTR_USB_MASK) >> USB_INTR_USB_SHIFT;
848 DBG(4, "usbintr (%x) epintr(%x)\n", usbintr, epintr);
849 /*
850 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
851 * AM3517's missing ID change IRQ. We need an ID change IRQ to
852 * switch appropriately between halves of the OTG state machine.
853 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
854 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
855 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
856 */
857 if ((usbintr & MUSB_INTR_BABBLE) && is_host_enabled(musb)) {
858 ERR("CAUTION: musb%d: Babble Interrupt Occured\n", musb->id);
859 ERR("Please issue long reset to make usb functional !!\n");
860 }
862 is_babble = is_host_capable() && (musb->int_usb & MUSB_INTR_BABBLE);
863 if (is_babble && musb->enable_babble_work)
864 musb->int_usb |= MUSB_INTR_DISCONNECT;
866 if (usbintr & (USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT)) {
867 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
868 void __iomem *mregs = musb->mregs;
869 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
870 int err;
872 err = is_host_enabled(musb) && (musb->int_usb &
873 MUSB_INTR_VBUSERROR);
874 if (err) {
875 /*
876 * The Mentor core doesn't debounce VBUS as needed
877 * to cope with device connect current spikes. This
878 * means it's not uncommon for bus-powered devices
879 * to get VBUS errors during enumeration.
880 *
881 * This is a workaround, but newer RTL from Mentor
882 * seems to allow a better one: "re"-starting sessions
883 * without waiting for VBUS to stop registering in
884 * devctl.
885 */
886 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
887 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
888 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
889 WARNING("VBUS error workaround (delay coming)\n");
890 } else if (is_host_enabled(musb) && drvvbus) {
891 musb->is_active = 1;
892 MUSB_HST_MODE(musb);
893 musb->xceiv->default_a = 1;
894 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
895 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
896 del_timer(&otg_workaround);
897 } else {
898 musb->is_active = 0;
899 MUSB_DEV_MODE(musb);
900 musb->xceiv->default_a = 0;
901 musb->xceiv->state = OTG_STATE_B_IDLE;
902 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
903 }
905 /* NOTE: this must complete power-on within 100 ms. */
906 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
907 drvvbus ? "on" : "off",
908 otg_state_string(musb),
909 err ? " ERROR" : "",
910 devctl);
911 ret = IRQ_HANDLED;
912 }
914 if (musb->int_tx || musb->int_rx || musb->int_usb)
915 ret |= musb_interrupt(musb);
917 eoi:
918 /* EOI needs to be written for the IRQ to be re-asserted. */
919 if (ret == IRQ_HANDLED || epintr || usbintr) {
920 /* write EOI */
921 musb_writel(reg_base, USB_IRQ_EOI, 1);
922 }
924 /* Poll for ID change */
925 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
926 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
928 spin_unlock_irqrestore(&musb->lock, flags);
930 if (ret != IRQ_HANDLED) {
931 if (epintr || usbintr)
932 /*
933 * We sometimes get unhandled IRQs in the peripheral
934 * mode from EP0 and SOF...
935 */
936 DBG(2, "Unhandled USB IRQ %08x-%08x\n",
937 epintr, usbintr);
938 else if (printk_ratelimit())
939 /*
940 * We've seen series of spurious interrupts in the
941 * peripheral mode after USB reset and then after some
942 * time a real interrupt storm starting...
943 */
944 DBG(2, "Spurious IRQ, CPPI 4.1 status %08x, %08x\n",
945 pend1, pend2);
946 }
948 if (is_babble) {
949 if (!musb->enable_babble_work) {
950 musb_writeb(musb->mregs, MUSB_DEVCTL,
951 musb_readb(musb->mregs, MUSB_DEVCTL) |
952 MUSB_DEVCTL_SESSION);
953 } else {
954 ERR("Babble: devtcl(%x)Restarting musb....\n",
955 musb_readb(musb->mregs, MUSB_DEVCTL));
956 schedule_work(&musb->work);
957 }
958 }
959 return ret;
960 }
961 int ti81xx_musb_set_mode(struct musb *musb, u8 musb_mode)
962 {
963 void __iomem *reg_base = musb->ctrl_base;
964 u32 regval;
966 /* TODO: implement this using CONF0 */
967 if (musb_mode == MUSB_HOST) {
968 regval = musb_readl(reg_base, USB_MODE_REG);
970 regval &= ~USBMODE_USBID_HIGH;
971 if (usbid_sw_ctrl && cpu_is_ti816x())
972 regval |= USBMODE_USBID_MUXSEL;
974 musb_writel(reg_base, USB_MODE_REG, regval);
975 musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
976 DBG(4, "host: value of mode reg=%x regval(%x)\n",
977 musb_readl(reg_base, USB_MODE_REG), regval);
978 } else if (musb_mode == MUSB_PERIPHERAL) {
979 /* TODO commmented writing 8 to USB_MODE_REG device
980 mode is not working */
981 regval = musb_readl(reg_base, USB_MODE_REG);
983 regval |= USBMODE_USBID_HIGH;
984 if (usbid_sw_ctrl && cpu_is_ti816x())
985 regval |= USBMODE_USBID_MUXSEL;
987 musb_writel(reg_base, USB_MODE_REG, regval);
988 DBG(4, "device: value of mode reg=%x regval(%x)\n",
989 musb_readl(reg_base, USB_MODE_REG), regval);
990 } else if (musb_mode == MUSB_OTG) {
991 musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
992 } else
993 return -EIO;
995 return 0;
996 }
998 int ti81xx_musb_init(struct musb *musb)
999 {
1000 void __iomem *reg_base = musb->ctrl_base;
1001 struct device *dev = musb->controller;
1002 struct musb_hdrc_platform_data *plat = dev->platform_data;
1003 struct omap_musb_board_data *data = plat->board_data;
1004 u32 rev, status = 0;
1005 u8 mode;
1007 if (musb->id < 2)
1008 gmusb[musb->id] = musb;
1010 usb_nop_xceiv_register(musb->id);
1012 musb->xceiv = otg_get_transceiver(musb->id);
1013 if (!musb->xceiv)
1014 return -ENODEV;
1016 status = pm_runtime_get_sync(dev);
1017 if (status < 0) {
1018 dev_err(dev, "pm_runtime_get_sync FAILED");
1019 goto err1;
1020 }
1022 /* mentor is at offset of 0x400 in am3517/ti81xx */
1023 musb->mregs += USB_MENTOR_CORE_OFFSET;
1026 /* Returns zero if e.g. not clocked */
1027 rev = musb_readl(reg_base, USB_REVISION_REG);
1028 if (!rev)
1029 return -ENODEV;
1031 if (is_host_enabled(musb))
1032 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
1034 /* Reset the controller */
1035 musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
1037 /* wait till reset bit clears */
1038 while ((musb_readl(reg_base, USB_CTRL_REG) & 0x1))
1039 cpu_relax();
1041 /* Start the on-chip PHY and its PLL. */
1042 if (data->set_phy_power)
1043 data->set_phy_power(1);
1045 musb->a_wait_bcon = A_WAIT_BCON_TIMEOUT;
1046 musb->isr = ti81xx_interrupt;
1048 if (cpu_is_ti816x())
1049 usbid_sw_ctrl = 1;
1051 if (is_otg_enabled(musb)) {
1052 /* if usb-id contolled through software for ti816x then
1053 * configure the usb0 in peripheral mode and usb1 in
1054 * host mode
1055 */
1056 if (usbid_sw_ctrl && cpu_is_ti816x())
1057 mode = musb->id ? MUSB_HOST : MUSB_PERIPHERAL;
1058 else
1059 mode = MUSB_OTG;
1060 } else
1061 /* set musb controller to host mode */
1062 mode = is_host_enabled(musb) ? MUSB_HOST : MUSB_PERIPHERAL;
1064 /* set musb controller to host mode */
1065 musb_platform_set_mode(musb, mode);
1067 /* enable babble workaround */
1068 INIT_WORK(&musb->work, evm_deferred_musb_restart);
1069 musb->enable_babble_work = 0;
1071 musb_writel(reg_base, USB_IRQ_EOI, 0);
1073 return 0;
1074 err1:
1075 pm_runtime_disable(dev);
1076 return status;
1077 }
1079 /* TI81xx supports only 32bit read operation */
1080 void ti81xx_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
1081 {
1082 void __iomem *fifo = hw_ep->fifo;
1083 u32 val;
1084 int i;
1086 /* Read for 32bit-aligned destination address */
1087 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
1088 readsl(fifo, dst, len >> 2);
1089 dst += len & ~0x03;
1090 len &= 0x03;
1091 }
1092 /*
1093 * Now read the remaining 1 to 3 byte or complete length if
1094 * unaligned address.
1095 */
1096 if (len > 4) {
1097 for (i = 0; i < (len >> 2); i++) {
1098 *(u32 *) dst = musb_readl(fifo, 0);
1099 dst += 4;
1100 }
1101 len &= 0x03;
1102 }
1103 if (len > 0) {
1104 val = musb_readl(fifo, 0);
1105 memcpy(dst, &val, len);
1106 }
1107 }
1109 int ti81xx_musb_exit(struct musb *musb)
1110 {
1111 struct device *dev = musb->controller;
1112 struct musb_hdrc_platform_data *plat = dev->platform_data;
1113 struct omap_musb_board_data *data = plat->board_data;
1115 if (is_host_enabled(musb))
1116 del_timer_sync(&otg_workaround);
1118 /* Shutdown the on-chip PHY and its PLL. */
1119 if (data->set_phy_power)
1120 data->set_phy_power(0);
1122 otg_put_transceiver(musb->xceiv);
1123 usb_nop_xceiv_unregister(musb->id);
1125 return 0;
1126 }
1128 static struct musb_platform_ops ti81xx_ops = {
1129 .fifo_mode = 4,
1130 .flags = MUSB_GLUE_EP_ADDR_FLAT_MAPPING | MUSB_GLUE_DMA_CPPI41,
1131 .init = ti81xx_musb_init,
1132 .exit = ti81xx_musb_exit,
1134 .enable = ti81xx_musb_enable,
1135 .disable = ti81xx_musb_disable,
1137 .try_idle = ti81xx_musb_try_idle,
1138 .set_mode = ti81xx_musb_set_mode,
1140 .read_fifo = ti81xx_musb_read_fifo,
1141 .write_fifo = musb_write_fifo,
1143 .dma_controller_create = cppi41_dma_controller_create,
1144 .dma_controller_destroy = cppi41_dma_controller_destroy,
1145 .simulate_babble_intr = musb_simulate_babble,
1146 };
1148 static void __devexit ti81xx_delete_musb_pdev(struct ti81xx_glue *glue, u8 id)
1149 {
1150 platform_device_del(glue->musb[id]);
1151 platform_device_put(glue->musb[id]);
1152 }
1154 static int __devinit ti81xx_create_musb_pdev(struct ti81xx_glue *glue, u8 id)
1155 {
1156 struct device *dev = glue->dev;
1157 struct platform_device *pdev = to_platform_device(dev);
1158 struct musb_hdrc_platform_data *pdata = dev->platform_data;
1159 struct platform_device *musb;
1160 struct resource *res;
1161 struct resource resources[2];
1162 char res_name[10];
1163 int ret;
1165 /* get memory resource */
1166 sprintf(res_name, "musb%d", id);
1167 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name);
1168 if (!res) {
1169 dev_err(dev, "%s get mem resource failed\n", res_name);
1170 ret = -ENODEV;
1171 goto err0;
1172 }
1173 res->parent = NULL;
1174 resources[0] = *res;
1176 /* get irq resource */
1177 sprintf(res_name, "musb%d-irq", id);
1178 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res_name);
1179 if (!res) {
1180 dev_err(dev, "%s get irq resource failed\n", res_name);
1181 ret = -ENODEV;
1182 goto err0;
1183 }
1184 res->parent = NULL;
1185 resources[1] = *res;
1187 /* allocate the child platform device */
1188 musb = platform_device_alloc("musb-hdrc", id);
1189 if (!musb) {
1190 dev_err(dev, "failed to allocate musb device\n");
1191 goto err0;
1192 }
1194 musb->id = id;
1195 musb->dev.parent = dev;
1196 musb->dev.dma_mask = &musb_dmamask;
1197 musb->dev.coherent_dma_mask = musb_dmamask;
1199 glue->musb[id] = musb;
1201 pdata->platform_ops = &ti81xx_ops;
1203 ret = platform_device_add_resources(musb, resources, 2);
1204 if (ret) {
1205 dev_err(dev, "failed to add resources\n");
1206 goto err1;
1207 }
1209 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
1210 if (ret) {
1211 dev_err(dev, "failed to add platform_data\n");
1212 goto err1;
1213 }
1215 ret = platform_device_add(musb);
1216 if (ret) {
1217 dev_err(dev, "failed to register musb device\n");
1218 goto err1;
1219 }
1221 return 0;
1223 err1:
1224 platform_device_put(musb);
1225 err0:
1226 return ret;
1227 }
1229 static int __init ti81xx_probe(struct platform_device *pdev)
1230 {
1231 struct ti81xx_glue *glue;
1232 struct device *dev = &pdev->dev;
1233 struct musb_hdrc_platform_data *plat = dev->platform_data;
1234 struct omap_musb_board_data *data = plat->board_data;
1235 int ret, i;
1236 struct resource *res;
1238 /* allocate glue */
1239 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1240 if (!glue) {
1241 dev_err(&pdev->dev, "unable to allocate glue memory\n");
1242 ret = -ENOMEM;
1243 goto err0;
1244 }
1246 /* interface clock needs to be enabled for usbss register programming */
1247 glue->ick = clk_get(&pdev->dev, "usbotg_ick");
1248 if (IS_ERR(glue->ick)) {
1249 dev_err(&pdev->dev, "unable to get usbss interface clock\n");
1250 ret = PTR_ERR(glue->ick);
1251 goto err1;
1252 }
1254 /* functional clock needs to be enabled for usbss register programming */
1255 glue->fck = clk_get(&pdev->dev, "usbotg_fck");
1256 if (IS_ERR(glue->fck)) {
1257 dev_err(&pdev->dev, "unable to get usbss functional clock\n");
1258 ret = PTR_ERR(glue->fck);
1259 goto err2;
1260 }
1262 /* get memory resource */
1263 glue->mem_pa = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1264 if (!glue->mem_pa) {
1265 dev_err(&pdev->dev, "failed to get usbss mem resourse\n");
1266 ret = -ENODEV;
1267 goto err3;
1268 }
1270 /* get memory resource */
1271 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "usbss-irq");
1272 if (!res) {
1273 dev_err(&pdev->dev, "failed to get usbss irq resourse\n");
1274 ret = -ENODEV;
1275 goto err3;
1276 }
1277 glue->irq = res->start;
1279 /* enable interface clock */
1280 ret = clk_enable(glue->ick);
1281 if (ret) {
1282 dev_err(&pdev->dev, "failed to enable usbss interface clock\n");
1283 goto err3;
1284 }
1286 /* enable functional clock */
1287 ret = clk_enable(glue->fck);
1288 if (ret) {
1289 dev_err(&pdev->dev, "failed to enable usbss functional clock\n");
1290 goto err4;
1291 }
1293 /* iomap for usbss mem space */
1294 glue->mem_va =
1295 ioremap(glue->mem_pa->start, resource_size(glue->mem_pa));
1296 if (!glue->mem_va) {
1297 dev_err(&pdev->dev, "usbss ioremap failed\n");
1298 ret = -ENOMEM;
1299 goto err5;
1300 }
1301 usbss_virt_base = glue->mem_va;
1303 glue->dev = &pdev->dev;
1304 platform_set_drvdata(pdev, glue);
1306 /* usb subsystem init */
1307 usbotg_ss_init();
1309 /* clear any USBSS interrupts */
1310 __raw_writel(0, glue->mem_va + USBSS_IRQ_EOI);
1311 __raw_writel(__raw_readl(glue->mem_va + USBSS_IRQ_STATUS),
1312 glue->mem_va + USBSS_IRQ_STATUS);
1314 /* create the child platform device for mulitple instances of musb */
1315 for (i = 0; i <= data->instances; ++i) {
1316 #ifdef CONFIG_USB_TI_CPPI41_DMA
1317 /* initialize the cppi41dma init */
1318 cppi41_init(i, glue->irq);
1319 #endif
1320 ret |= ti81xx_create_musb_pdev(glue, i);
1321 if (ret != 0)
1322 goto err6;
1323 }
1325 return 0;
1327 err6:
1328 iounmap(glue->mem_va);
1329 err5:
1330 clk_disable(glue->fck);
1331 err4:
1332 clk_disable(glue->ick);
1333 err3:
1334 clk_put(glue->fck);
1335 err2:
1336 clk_put(glue->ick);
1337 err1:
1338 kfree(glue);
1339 err0:
1340 return ret;
1341 }
1343 static int __exit ti81xx_remove(struct platform_device *pdev)
1344 {
1345 struct ti81xx_glue *glue = platform_get_drvdata(pdev);
1346 struct device *dev = &pdev->dev;
1347 struct musb_hdrc_platform_data *plat = dev->platform_data;
1348 struct omap_musb_board_data *data = plat->board_data;
1349 int i;
1351 /* delete the child platform device for mulitple instances of musb */
1352 for (i = 0; i <= data->instances; ++i)
1353 ti81xx_delete_musb_pdev(glue, i);
1355 #ifdef CONFIG_USB_TI_CPPI41_DMA
1356 cppi41_free();
1357 #endif
1358 /* iounmap */
1359 iounmap(glue->mem_va);
1360 usbotg_ss_uninit();
1362 /* disable common usbss functional clock */
1363 clk_disable(glue->fck);
1364 clk_put(glue->fck);
1365 /* disable common usbss interface clock */
1366 clk_disable(glue->ick);
1367 clk_put(glue->ick);
1368 kfree(glue);
1370 return 0;
1371 }
1373 #ifdef CONFIG_PM
1374 static int ti81xx_suspend(struct device *dev)
1375 {
1376 struct ti81xx_glue *glue = dev_get_drvdata(dev);
1377 struct musb_hdrc_platform_data *plat = dev->platform_data;
1378 struct omap_musb_board_data *data = plat->board_data;
1379 int i;
1381 /* Shutdown the on-chip PHY and its PLL. */
1382 for (i = 0; i <= data->instances; ++i) {
1383 if (data->set_phy_power)
1384 data->set_phy_power(i);
1385 }
1387 /* disable the common usbss functional clock */
1388 clk_disable(glue->fck);
1389 /* disable the common usbss interface clock */
1390 clk_disable(glue->ick);
1391 return 0;
1392 }
1394 static int ti81xx_resume(struct device *dev)
1395 {
1396 struct ti81xx_glue *glue = dev_get_drvdata(dev);
1397 struct musb_hdrc_platform_data *plat = dev->platform_data;
1398 struct omap_musb_board_data *data = plat->board_data;
1399 int ret, i;
1401 /* Start the on-chip PHY and its PLL. */
1402 for (i = 0; i <= data->instances; ++i) {
1403 if (data->set_phy_power)
1404 data->set_phy_power(i);
1405 }
1407 /* enable the common usbss interface clock */
1408 ret = clk_enable(glue->ick);
1409 if (ret) {
1410 dev_err(dev, "failed to enable iclock\n");
1411 return ret;
1412 }
1413 /* enable the common usbss functional clock */
1414 ret = clk_enable(glue->fck);
1415 if (ret) {
1416 dev_err(dev, "failed to enable fclock\n");
1417 return ret;
1418 }
1419 return 0;
1420 }
1422 static const struct dev_pm_ops ti81xx_pm_ops = {
1423 .suspend = ti81xx_suspend,
1424 .resume = ti81xx_resume,
1425 };
1427 #define DEV_PM_OPS (&ti81xx_pm_ops)
1428 #else
1429 #define DEV_PM_OPS NULL
1430 #endif
1432 static struct platform_driver ti81xx_musb_driver = {
1433 .remove = __exit_p(ti81xx_remove),
1434 .driver = {
1435 .name = "musb-ti81xx",
1436 .pm = DEV_PM_OPS,
1437 },
1438 };
1440 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1441 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
1442 MODULE_LICENSE("GPL v2");
1444 static int __init ti81xx_glue_init(void)
1445 {
1446 return platform_driver_probe(&ti81xx_musb_driver, ti81xx_probe);
1447 }
1448 subsys_initcall(ti81xx_glue_init);
1450 static void __exit ti81xx_glue_exit(void)
1451 {
1452 #ifdef CONFIG_USB_TI_CPPI41_DMA
1453 /* free the usbss irq */
1454 free_irq(TI81XX_IRQ_USBSS, 0);
1455 #endif
1457 /* disable the interrupts */
1458 usbss_write(USBSS_IRQ_EOI, 0);
1459 usbss_write(USBSS_IRQ_ENABLE_SET, 0);
1460 usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0);
1462 /* unregister platform driver */
1463 platform_driver_unregister(&ti81xx_musb_driver);
1464 }
1465 module_exit(ti81xx_glue_exit);
1467 #ifdef CONFIG_PM
1468 void musb_platform_save_context(struct musb *musb,
1469 struct musb_context_registers *musb_context)
1470 {
1471 /* Save CPPI41 DMA related registers */
1472 }
1474 void musb_platform_restore_context(struct musb *musb,
1475 struct musb_context_registers *musb_context)
1476 {
1477 /* Restore CPPI41 DMA related registers */
1478 }
1479 #endif