1 /*
2 * Texas Instruments TI81XX "usb platform glue layer"
3 *
4 * Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * Based on the DaVinci "glue layer" code.
7 * Copyright (C) 2005-2006 by Texas Instruments
8 *
9 * This file is part of the Inventra Controller Driver for Linux.
10 *
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
14 * Foundation.
15 *
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
29 #include <linux/init.h>
30 #include <linux/clk.h>
31 #include <linux/io.h>
32 #include <linux/usb/otg.h>
33 #include <linux/platform_device.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/module.h>
37 #include "cppi41.h"
38 #include "ti81xx.h"
40 #include "musb_core.h"
41 #include "cppi41_dma.h"
43 struct ti81xx_glue {
44 struct device *dev;
45 struct platform_device *musb;
46 struct clk *phy_clk;
47 struct clk *clk;
48 };
49 static u64 musb_dmamask = DMA_BIT_MASK(32);
50 static void *usbss_virt_base;
51 static u8 usbss_init_done;
52 struct musb *gmusb[2];
54 u8 usbid_sw_ctrl;
55 #undef USB_TI81XX_DEBUG
57 #ifdef USB_TI81XX_DEBUG
58 #define dprintk(x, ...) printk(x, ## __VA_ARGS__)
59 #else
60 #define dprintk(x, ...)
61 #endif
63 #ifdef CONFIG_USB_TI_CPPI41_DMA
64 static irqreturn_t cppi41dma_Interrupt(int irq, void *hci);
65 static u8 cppi41_init_done;
66 static void *cppi41_dma_base;
67 #define CPPI41_ADDR(offs) ((void *)((u32)cppi41_dma_base + (offs - 0x2000)))
68 #endif
70 extern void omap_ctrl_writel(u32 val, u16 offset);
71 extern u32 omap_ctrl_readl(u16 offset);
73 static inline u32 usbss_read(u32 offset)
74 {
75 if (!usbss_init_done)
76 return 0;
77 return __raw_readl(usbss_virt_base + offset);
78 }
80 static inline void usbss_write(u32 offset, u32 data)
81 {
82 if (!usbss_init_done)
83 return ;
84 __raw_writel(data, usbss_virt_base + offset);
85 }
87 static void usbotg_ss_init(struct musb *musb)
88 {
89 if (!usbss_init_done) {
90 usbss_virt_base = ioremap(TI81XX_USBSS_BASE,
91 TI81XX_USBSS_LEN);
92 usbss_init_done = 1;
93 /* clear any USBSS interrupts */
94 usbss_write(USBSS_IRQ_EOI, 0);
95 usbss_write(USBSS_IRQ_STATUS, usbss_read(USBSS_IRQ_STATUS));
96 }
97 }
98 static void usbotg_ss_uninit(void)
99 {
100 if (usbss_init_done) {
101 iounmap(usbss_virt_base);
102 usbss_init_done = 0;
103 usbss_virt_base = 0;
104 }
105 }
106 void set_frame_threshold(u8 musb_id, u8 is_tx, u8 epnum, u8 value, u8 en_intr)
107 {
108 u32 base, reg_val, frame_intr = 0, frame_base = 0;
109 u32 offs = epnum/4*4;
110 u8 indx = (epnum % 4) * 8;
112 if (is_tx)
113 base = musb_id ? USBSS_IRQ_FRAME_THRESHOLD_TX1 :
114 USBSS_IRQ_FRAME_THRESHOLD_TX0;
115 else
116 base = musb_id ? USBSS_IRQ_FRAME_THRESHOLD_RX1 :
117 USBSS_IRQ_FRAME_THRESHOLD_RX0;
119 reg_val = usbss_read(base + offs);
120 reg_val &= ~(0xFF << indx);
121 reg_val |= (value << indx);
122 usbss_write(base + offs, reg_val);
124 if (en_intr) {
125 frame_base = musb_id ? USBSS_IRQ_FRAME_ENABLE_1 :
126 USBSS_IRQ_FRAME_ENABLE_0;
127 frame_intr = musb_id ? usbss_read(USBSS_IRQ_FRAME_ENABLE_0) :
128 usbss_read(USBSS_IRQ_FRAME_ENABLE_1);
129 frame_intr |= is_tx ? (1 << epnum) : (1 << (16 + epnum));
130 usbss_write(frame_base, frame_intr);
131 DBG(4, "%s: framebase=%x, frame_intr=%x\n", is_tx ? "tx" : "rx",
132 frame_base, frame_intr);
133 }
134 }
136 void set_dma_threshold(u8 musb_id, u8 is_tx, u8 epnum, u8 value)
137 {
138 u32 base, reg_val;
139 u32 offs = epnum/4*4;
140 u8 indx = (epnum % 4) * 8;
142 if (musb_id == 0)
143 base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX0 :
144 USBSS_IRQ_DMA_THRESHOLD_RX0;
145 else
146 base = is_tx ? USBSS_IRQ_DMA_THRESHOLD_TX1 :
147 USBSS_IRQ_DMA_THRESHOLD_RX1;
149 reg_val = usbss_read(base + offs);
150 reg_val &= ~(0xFF << indx);
151 reg_val |= (value << indx);
152 DBG(4, "base=%x, offs=%x, indx=%d, reg_val = (%x)%x\n",
153 base, offs, indx, reg_val, usbss_read(base + offs));
154 usbss_write(base + offs, reg_val);
155 }
157 /* ti81xx specific read/write functions */
158 u16 ti81xx_musb_readw(const void __iomem *addr, unsigned offset)
159 {
160 u32 tmp;
161 u16 val;
163 tmp = __raw_readl(addr + (offset & ~3));
165 switch (offset & 0x3) {
166 case 0:
167 val = (tmp & 0xffff);
168 break;
169 case 1:
170 val = (tmp >> 8) & 0xffff;
171 break;
172 case 2:
173 case 3:
174 default:
175 val = (tmp >> 16) & 0xffff;
176 break;
177 }
178 return val;
179 }
181 void ti81xx_musb_writew(void __iomem *addr, unsigned offset, u16 data)
182 {
183 __raw_writew(data, addr + offset);
184 }
186 u8 ti81xx_musb_readb(const void __iomem *addr, unsigned offset)
187 {
188 u32 tmp;
189 u8 val;
191 tmp = __raw_readl(addr + (offset & ~3));
193 switch (offset & 0x3) {
194 case 0:
195 val = tmp & 0xff;
196 break;
197 case 1:
198 val = (tmp >> 8);
199 break;
200 case 2:
201 val = (tmp >> 16);
202 break;
203 case 3:
204 default:
205 val = (tmp >> 24);
206 break;
207 }
208 return val;
209 }
210 void ti81xx_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
211 {
212 __raw_writeb(data, addr + offset);
213 }
215 #ifdef CONFIG_USB_TI_CPPI41_DMA
216 /*
217 * CPPI 4.1 resources used for USB OTG controller module:
218 *
219 tx/rx completion queues for usb0 */
220 static u16 tx_comp_q[] = {93, 94, 95, 96, 97,
221 98, 99, 100, 101, 102,
222 103, 104, 105, 106, 107 };
224 static u16 rx_comp_q[] = {109, 110, 111, 112, 113,
225 114, 115, 116, 117, 118,
226 119, 120, 121, 122, 123 };
228 /* tx/rx completion queues for usb1 */
229 static u16 tx_comp_q1[] = {125, 126, 127, 128, 129,
230 130, 131, 132, 133, 134,
231 135, 136, 137, 138, 139 };
233 static u16 rx_comp_q1[] = {141, 142, 143, 144, 145,
234 146, 147, 148, 149, 150,
235 151, 152, 153, 154, 155 };
237 /* Fair scheduling */
238 u32 dma_sched_table[] = {
239 0x81018000, 0x83038202, 0x85058404, 0x87078606,
240 0x89098808, 0x8b0b8a0a, 0x8d0d8c0c, 0x8f0f8e0e,
241 0x91119010, 0x93139212, 0x95159414, 0x97179616,
242 0x99199818, 0x9b1b9a1a, 0x9d1d9c1c, 0x00009e1e,
243 };
245 /* cppi41 dma tx channel info */
246 static const struct cppi41_tx_ch tx_ch_info[] = {
247 [0] = {
248 .port_num = 1,
249 .num_tx_queue = 2,
250 .tx_queue = { {0, 32} , {0, 33} }
251 },
252 [1] = {
253 .port_num = 2,
254 .num_tx_queue = 2,
255 .tx_queue = { {0, 34} , {0, 35} }
256 },
257 [2] = {
258 .port_num = 3,
259 .num_tx_queue = 2,
260 .tx_queue = { {0, 36} , {0, 37} }
261 },
262 [3] = {
263 .port_num = 4,
264 .num_tx_queue = 2,
265 .tx_queue = { {0, 38} , {0, 39} }
266 },
267 [4] = {
268 .port_num = 5,
269 .num_tx_queue = 2,
270 .tx_queue = { {0, 40} , {0, 41} }
271 },
272 [5] = {
273 .port_num = 6,
274 .num_tx_queue = 2,
275 .tx_queue = { {0, 42} , {0, 43} }
276 },
277 [6] = {
278 .port_num = 7,
279 .num_tx_queue = 2,
280 .tx_queue = { {0, 44} , {0, 45} }
281 },
282 [7] = {
283 .port_num = 8,
284 .num_tx_queue = 2,
285 .tx_queue = { {0, 46} , {0, 47} }
286 },
287 [8] = {
288 .port_num = 9,
289 .num_tx_queue = 2,
290 .tx_queue = { {0, 48} , {0, 49} }
291 },
292 [9] = {
293 .port_num = 10,
294 .num_tx_queue = 2,
295 .tx_queue = { {0, 50} , {0, 51} }
296 },
297 [10] = {
298 .port_num = 11,
299 .num_tx_queue = 2,
300 .tx_queue = { {0, 52} , {0, 53} }
301 },
302 [11] = {
303 .port_num = 12,
304 .num_tx_queue = 2,
305 .tx_queue = { {0, 54} , {0, 55} }
306 },
307 [12] = {
308 .port_num = 13,
309 .num_tx_queue = 2,
310 .tx_queue = { {0, 56} , {0, 57} }
311 },
312 [13] = {
313 .port_num = 14,
314 .num_tx_queue = 2,
315 .tx_queue = { {0, 58} , {0, 59} }
316 },
317 [14] = {
318 .port_num = 15,
319 .num_tx_queue = 2,
320 .tx_queue = { {0, 60} , {0, 61} }
321 },
322 [15] = {
323 .port_num = 1,
324 .num_tx_queue = 2,
325 .tx_queue = { {0, 62} , {0, 63} }
326 },
327 [16] = {
328 .port_num = 2,
329 .num_tx_queue = 2,
330 .tx_queue = { {0, 64} , {0, 65} }
331 },
332 [17] = {
333 .port_num = 3,
334 .num_tx_queue = 2,
335 .tx_queue = { {0, 66} , {0, 67} }
336 },
337 [18] = {
338 .port_num = 4,
339 .num_tx_queue = 2,
340 .tx_queue = { {0, 68} , {0, 69} }
341 },
342 [19] = {
343 .port_num = 5,
344 .num_tx_queue = 2,
345 .tx_queue = { {0, 70} , {0, 71} }
346 },
347 [20] = {
348 .port_num = 6,
349 .num_tx_queue = 2,
350 .tx_queue = { {0, 72} , {0, 73} }
351 },
352 [21] = {
353 .port_num = 7,
354 .num_tx_queue = 2,
355 .tx_queue = { {0, 74} , {0, 75} }
356 },
357 [22] = {
358 .port_num = 8,
359 .num_tx_queue = 2,
360 .tx_queue = { {0, 76} , {0, 77} }
361 },
362 [23] = {
363 .port_num = 9,
364 .num_tx_queue = 2,
365 .tx_queue = { {0, 78} , {0, 79} }
366 },
367 [24] = {
368 .port_num = 10,
369 .num_tx_queue = 2,
370 .tx_queue = { {0, 80} , {0, 81} }
371 },
372 [25] = {
373 .port_num = 11,
374 .num_tx_queue = 2,
375 .tx_queue = { {0, 82} , {0, 83} }
376 },
377 [26] = {
378 .port_num = 12,
379 .num_tx_queue = 2,
380 .tx_queue = { {0, 84} , {0, 85} }
381 },
382 [27] = {
383 .port_num = 13,
384 .num_tx_queue = 2,
385 .tx_queue = { {0, 86} , {0, 87} }
386 },
387 [28] = {
388 .port_num = 14,
389 .num_tx_queue = 2,
390 .tx_queue = { {0, 88} , {0, 89} }
391 },
392 [29] = {
393 .port_num = 15,
394 .num_tx_queue = 2,
395 .tx_queue = { {0, 90} , {0, 91} }
396 }
397 };
399 /* Queues 0 to 66 are pre-assigned, others are spare */
400 static const u32 assigned_queues[] = { 0xffffffff, /* queue 0..31 */
401 0xffffffff, /* queue 32..63 */
402 0xffffffff, /* queue 64..95 */
403 0xffffffff, /* queue 96..127 */
404 0x0fffffff /* queue 128..155 */
405 };
407 int __devinit cppi41_init(struct musb *musb)
408 {
409 struct usb_cppi41_info *cppi_info = &usb_cppi41_info[musb->id];
410 u16 numch, blknum, order;
411 u32 i, nIrq = TI81XX_IRQ_USBSS;
413 /* init cppi info structure */
414 cppi_info->dma_block = 0;
415 for (i = 0 ; i < USB_CPPI41_NUM_CH ; i++)
416 cppi_info->ep_dma_ch[i] = i + (15 * musb->id);
418 cppi_info->q_mgr = 0;
419 cppi_info->num_tx_comp_q = 15;
420 cppi_info->num_rx_comp_q = 15;
421 cppi_info->tx_comp_q = musb->id ? tx_comp_q1 : tx_comp_q;
422 cppi_info->rx_comp_q = musb->id ? rx_comp_q1 : rx_comp_q;
423 cppi_info->bd_intr_ctrl = 1;
425 if (cppi41_init_done)
426 return 0;
428 blknum = cppi_info->dma_block;
430 /* Queue manager information */
431 cppi41_queue_mgr[0].num_queue = 159;
432 cppi41_queue_mgr[0].queue_types = CPPI41_FREE_DESC_BUF_QUEUE |
433 CPPI41_UNASSIGNED_QUEUE;
434 cppi41_queue_mgr[0].base_fdbq_num = 0;
435 cppi41_queue_mgr[0].assigned = assigned_queues;
437 /* init DMA block */
438 cppi41_dma_block[0].num_tx_ch = 30;
439 cppi41_dma_block[0].num_rx_ch = 30;
440 cppi41_dma_block[0].tx_ch_info = tx_ch_info;
442 /* initilize cppi41 dma & Qmgr address */
443 cppi41_dma_base = ioremap(TI81XX_USB_CPPIDMA_BASE,
444 TI81XX_USB_CPPIDMA_LEN);
446 cppi41_queue_mgr[0].q_mgr_rgn_base = CPPI41_ADDR(QMGR_RGN_OFFS);
447 cppi41_queue_mgr[0].desc_mem_rgn_base = CPPI41_ADDR(QMRG_DESCRGN_OFFS);
448 cppi41_queue_mgr[0].q_mgmt_rgn_base = CPPI41_ADDR(QMGR_REG_OFFS);
449 cppi41_queue_mgr[0].q_stat_rgn_base = CPPI41_ADDR(QMGR_STAT_OFFS);
450 cppi41_dma_block[0].global_ctrl_base = CPPI41_ADDR(DMA_GLBCTRL_OFFS);
451 cppi41_dma_block[0].ch_ctrl_stat_base = CPPI41_ADDR(DMA_CHCTRL_OFFS);
452 cppi41_dma_block[0].sched_ctrl_base = CPPI41_ADDR(DMA_SCHED_OFFS);
453 cppi41_dma_block[0].sched_table_base = CPPI41_ADDR(DMA_SCHEDTBL_OFFS);
455 /* Initialize for Linking RAM region 0 alone */
456 cppi41_queue_mgr_init(cppi_info->q_mgr, 0, 0x3fff);
458 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
459 numch = USB_CPPI41_NUM_CH * 2;
460 #else
461 numch = USB_CPPI41_NUM_CH * 2 * 2;
462 #endif
463 order = get_count_order(numch);
465 /* TODO: check two teardown desc per channel (5 or 7 ?)*/
466 if (order < 5)
467 order = 5;
469 cppi41_dma_block_init(blknum, cppi_info->q_mgr, order,
470 dma_sched_table, numch);
472 /* attach to the IRQ */
473 if (request_irq(nIrq, cppi41dma_Interrupt, 0, "cppi41_dma", 0))
474 printk(KERN_INFO "request_irq %d failed!\n", nIrq);
475 else
476 printk(KERN_INFO "registerd cppi-dma Intr @ IRQ %d\n", nIrq);
478 cppi41_init_done = 1;
480 /* enable all the interrupts */
481 usbss_write(USBSS_IRQ_EOI, 0);
482 usbss_write(USBSS_IRQ_ENABLE_SET, USBSS_INTR_FLAGS);
483 usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0xFFFeFFFe);
485 DBG(4, "Cppi41 Init Done Qmgr-base(%p) dma-base(%p)\n",
486 cppi41_queue_mgr[0].q_mgr_rgn_base,
487 cppi41_dma_block[0].global_ctrl_base);
489 printk(KERN_INFO "Cppi41 Init Done\n");
491 return 0;
492 }
494 void cppi41_free(void)
495 {
496 u32 numch, blknum, order;
497 struct usb_cppi41_info *cppi_info = &usb_cppi41_info[0];
499 if (!cppi41_init_done)
500 return ;
502 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
503 numch = USB_CPPI41_NUM_CH * 2;
504 #else
505 numch = USB_CPPI41_NUM_CH * 2 * 2;
506 #endif
507 order = get_count_order(numch);
508 blknum = cppi_info->dma_block;
510 cppi41_dma_block_uninit(blknum, cppi_info->q_mgr, order,
511 dma_sched_table, numch);
512 cppi41_queue_mgr_uninit(cppi_info->q_mgr);
514 iounmap(cppi41_dma_base);
515 cppi41_dma_base = 0;
516 cppi41_init_done = 0;
517 }
519 int cppi41_disable_sched_rx(void)
520 {
521 cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
522 return 0;
523 }
525 int cppi41_enable_sched_rx(void)
526 {
527 cppi41_dma_sched_tbl_init(0, 0, dma_sched_table, 30);
528 return 0;
529 }
530 #endif /* CONFIG_USB_TI_CPPI41_DMA */
532 /*
533 * Because we don't set CTRL.UINT, it's "important" to:
534 * - not read/write INTRUSB/INTRUSBE (except during
535 * initial setup, as a workaround);
536 * - use INTSET/INTCLR instead.
537 */
539 /**
540 * ti81xx_musb_enable - enable interrupts
541 */
542 void ti81xx_musb_enable(struct musb *musb)
543 {
544 void __iomem *reg_base = musb->ctrl_base;
545 u32 epmask, coremask;
547 /* Workaround: setup IRQs through both register sets. */
548 epmask = ((musb->epmask & USB_TX_EP_MASK) << USB_INTR_TX_SHIFT) |
549 ((musb->epmask & USB_RX_EP_MASK) << USB_INTR_RX_SHIFT);
550 coremask = (0x01ff << USB_INTR_USB_SHIFT);
552 coremask &= ~MUSB_INTR_SOF;
554 musb_writel(reg_base, USB_EP_INTR_SET_REG, epmask);
555 musb_writel(reg_base, USB_CORE_INTR_SET_REG, coremask);
556 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
557 if (is_otg_enabled(musb))
558 musb_writel(reg_base, USB_CORE_INTR_SET_REG,
559 USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT);
560 }
562 /**
563 * ti81xx_musb_disable - disable HDRC and flush interrupts
564 */
565 void ti81xx_musb_disable(struct musb *musb)
566 {
567 void __iomem *reg_base = musb->ctrl_base;
569 musb_writel(reg_base, USB_CORE_INTR_CLEAR_REG, USB_INTR_USB_MASK);
570 musb_writel(reg_base, USB_EP_INTR_CLEAR_REG,
571 USB_TX_INTR_MASK | USB_RX_INTR_MASK);
572 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
573 musb_writel(reg_base, USB_IRQ_EOI, 0);
574 }
576 #define POLL_SECONDS 2
578 static struct timer_list otg_workaround;
580 static void otg_timer(unsigned long _musb)
581 {
582 struct musb *musb = (void *)_musb;
583 void __iomem *mregs = musb->mregs;
584 u8 devctl;
585 unsigned long flags;
587 /* We poll because DaVinci's won't expose several OTG-critical
588 * status change events (from the transceiver) otherwise.
589 */
590 devctl = musb_readb(mregs, MUSB_DEVCTL);
591 DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
593 spin_lock_irqsave(&musb->lock, flags);
594 switch (musb->xceiv->state) {
595 case OTG_STATE_A_WAIT_BCON:
596 devctl &= ~MUSB_DEVCTL_SESSION;
597 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
599 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
600 if (devctl & MUSB_DEVCTL_BDEVICE) {
601 musb->xceiv->state = OTG_STATE_B_IDLE;
602 MUSB_DEV_MODE(musb);
603 } else {
604 musb->xceiv->state = OTG_STATE_A_IDLE;
605 MUSB_HST_MODE(musb);
606 }
607 break;
608 case OTG_STATE_A_WAIT_VFALL:
609 /*
610 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
611 * RTL seems to mis-handle session "start" otherwise (or in
612 * our case "recover"), in routine "VBUS was valid by the time
613 * VBUSERR got reported during enumeration" cases.
614 */
615 if (devctl & MUSB_DEVCTL_VBUS) {
616 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
617 break;
618 }
619 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
620 musb_writel(musb->ctrl_base, USB_CORE_INTR_SET_REG,
621 MUSB_INTR_VBUSERROR << USB_INTR_USB_SHIFT);
622 break;
623 case OTG_STATE_B_IDLE:
624 if (!is_peripheral_enabled(musb))
625 break;
627 /*
628 * There's no ID-changed IRQ, so we have no good way to tell
629 * when to switch to the A-Default state machine (by setting
630 * the DEVCTL.SESSION flag).
631 *
632 * Workaround: whenever we're in B_IDLE, try setting the
633 * session flag every few seconds. If it works, ID was
634 * grounded and we're now in the A-Default state machine.
635 *
636 * NOTE: setting the session flag is _supposed_ to trigger
637 * SRP but clearly it doesn't.
638 */
639 devctl = musb_readb(mregs, MUSB_DEVCTL);
640 if (devctl & MUSB_DEVCTL_BDEVICE)
641 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
642 else
643 musb->xceiv->state = OTG_STATE_A_IDLE;
644 break;
645 default:
646 break;
647 }
648 spin_unlock_irqrestore(&musb->lock, flags);
649 }
651 void ti81xx_musb_try_idle(struct musb *musb, unsigned long timeout)
652 {
653 static unsigned long last_timer;
655 if (!is_otg_enabled(musb))
656 return;
658 if (timeout == 0)
659 timeout = jiffies + msecs_to_jiffies(3);
661 /* Never idle if active, or when VBUS timeout is not set as host */
662 if (musb->is_active || (musb->a_wait_bcon == 0 &&
663 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
664 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
665 del_timer(&otg_workaround);
666 last_timer = jiffies;
667 return;
668 }
670 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
671 DBG(4, "Longer idle timer already pending, ignoring...\n");
672 return;
673 }
674 last_timer = timeout;
676 DBG(4, "%s inactive, starting idle timer for %u ms\n",
677 otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
678 mod_timer(&otg_workaround, timeout);
679 }
681 #ifdef CONFIG_USB_TI_CPPI41_DMA
682 static irqreturn_t cppi41dma_Interrupt(int irq, void *hci)
683 {
684 struct musb *musb = hci;
685 u32 intr_status;
686 irqreturn_t ret = IRQ_NONE;
687 u32 q_cmpl_status_0, q_cmpl_status_1, q_cmpl_status_2;
688 u32 usb0_tx_intr, usb0_rx_intr;
689 u32 usb1_tx_intr, usb1_rx_intr;
690 void *q_mgr_base = cppi41_queue_mgr[0].q_mgr_rgn_base;
691 unsigned long flags;
693 musb = hci;
694 /*
695 * CPPI 4.1 interrupts share the same IRQ and the EOI register but
696 * don't get reflected in the interrupt source/mask registers.
697 */
698 /*
699 * Check for the interrupts from Tx/Rx completion queues; they
700 * are level-triggered and will stay asserted until the queues
701 * are emptied. We're using the queue pending register 0 as a
702 * substitute for the interrupt status register and reading it
703 * directly for speed.
704 */
705 intr_status = usbss_read(USBSS_IRQ_STATUS);
707 if (intr_status)
708 usbss_write(USBSS_IRQ_STATUS, intr_status);
709 else
710 printk(KERN_DEBUG "spurious usbss intr\n");
712 q_cmpl_status_0 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG2);
713 q_cmpl_status_1 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG3);
714 q_cmpl_status_2 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG4);
716 /* USB0 tx/rx completion */
717 /* usb0 tx completion interrupt for ep1..15 */
718 usb0_tx_intr = (q_cmpl_status_0 >> 29) |
719 ((q_cmpl_status_1 & 0xFFF) << 3);
720 usb0_rx_intr = ((q_cmpl_status_1 & 0x07FFe000) >> 13);
722 usb1_tx_intr = (q_cmpl_status_1 >> 29) |
723 ((q_cmpl_status_2 & 0xFFF) << 3);
724 usb1_rx_intr = ((q_cmpl_status_2 & 0x0fffe000) >> 13);
726 /* get proper musb handle based usb0/usb1 ctrl-id */
728 DBG(4, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", usb0_tx_intr,
729 usb0_rx_intr);
730 if (usb0_tx_intr || usb0_rx_intr) {
731 spin_lock_irqsave(&gmusb[0]->lock, flags);
732 cppi41_completion(gmusb[0], usb0_rx_intr,
733 usb0_tx_intr);
734 spin_unlock_irqrestore(&gmusb[0]->lock, flags);
735 ret = IRQ_HANDLED;
736 }
738 DBG(4, "CPPI 4.1 IRQ: Tx %x, Rx %x\n", usb1_tx_intr,
739 usb1_rx_intr);
740 if (usb1_rx_intr || usb1_tx_intr) {
741 spin_lock_irqsave(&gmusb[1]->lock, flags);
742 cppi41_completion(gmusb[1], usb1_rx_intr,
743 usb1_tx_intr);
744 spin_unlock_irqrestore(&gmusb[1]->lock, flags);
745 ret = IRQ_HANDLED;
746 }
747 usbss_write(USBSS_IRQ_EOI, 0);
749 return ret;
750 }
751 #endif
753 int musb_simulate_babble(struct musb *musb)
754 {
755 void __iomem *reg_base = musb->ctrl_base;
756 void __iomem *mbase = musb->mregs;
757 u8 reg;
759 /* during babble condition musb controller
760 * remove the session
761 */
762 reg = musb_readb(mbase, MUSB_DEVCTL);
763 reg &= ~MUSB_DEVCTL_SESSION;
764 musb_writeb(mbase, MUSB_DEVCTL, reg);
765 mdelay(100);
767 /* generate s/w babble interrupt */
768 musb_writel(reg_base, USB_IRQ_STATUS_RAW_1,
769 MUSB_INTR_BABBLE);
770 return 0;
771 }
772 EXPORT_SYMBOL(musb_simulate_babble);
774 void musb_babble_workaround(struct musb *musb)
775 {
776 void __iomem *reg_base = musb->ctrl_base;
777 struct device *dev = musb->controller;
778 struct musb_hdrc_platform_data *plat = dev->platform_data;
779 struct omap_musb_board_data *data = plat->board_data;
781 /* Reset the controller */
782 musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
783 udelay(100);
785 /* Shutdown the on-chip PHY and its PLL. */
786 if (data->set_phy_power)
787 data->set_phy_power(0);
788 udelay(100);
790 musb_platform_set_mode(musb, MUSB_HOST);
791 udelay(100);
793 /* enable the usbphy */
794 if (data->set_phy_power)
795 data->set_phy_power(1);
796 mdelay(100);
798 /* save the usbotgss register contents */
799 musb_platform_enable(musb);
801 musb_start(musb);
802 }
804 static void evm_deferred_musb_restart(struct work_struct *work)
805 {
806 struct musb *musb =
807 container_of(work, struct musb, work);
809 ERR("deferred musb restart musbid(%d)\n", musb->id);
810 musb_babble_workaround(musb);
811 }
813 static irqreturn_t ti81xx_interrupt(int irq, void *hci)
814 {
815 struct musb *musb = hci;
816 void __iomem *reg_base = musb->ctrl_base;
817 unsigned long flags;
818 irqreturn_t ret = IRQ_NONE;
819 u32 pend1 = 0, pend2 = 0;
820 u32 epintr, usbintr;
821 u8 is_babble = 0;
823 spin_lock_irqsave(&musb->lock, flags);
825 /* Acknowledge and handle non-CPPI interrupts */
826 /* Get endpoint interrupts */
827 epintr = musb_readl(reg_base, USB_EP_INTR_STATUS_REG);
828 musb->int_rx = (epintr & USB_RX_INTR_MASK) >> USB_INTR_RX_SHIFT;
829 musb->int_tx = (epintr & USB_TX_INTR_MASK) >> USB_INTR_TX_SHIFT;
830 if (epintr)
831 musb_writel(reg_base, USB_EP_INTR_STATUS_REG, epintr);
833 /* Get usb core interrupts */
834 usbintr = musb_readl(reg_base, USB_CORE_INTR_STATUS_REG);
835 if (!usbintr && !epintr) {
836 DBG(4, "sprious interrupt\n");
837 goto eoi;
838 }
840 if (usbintr)
841 musb_writel(reg_base, USB_CORE_INTR_STATUS_REG, usbintr);
842 musb->int_usb = (usbintr & USB_INTR_USB_MASK) >> USB_INTR_USB_SHIFT;
844 DBG(4, "usbintr (%x) epintr(%x)\n", usbintr, epintr);
845 /*
846 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
847 * AM3517's missing ID change IRQ. We need an ID change IRQ to
848 * switch appropriately between halves of the OTG state machine.
849 * Managing DEVCTL.SESSION per Mentor docs requires that we know its
850 * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
851 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
852 */
853 if ((usbintr & MUSB_INTR_BABBLE) && is_host_enabled(musb)) {
854 ERR("CAUTION: musb%d: Babble Interrupt Occured\n", musb->id);
855 ERR("Please issue long reset to make usb functional !!\n");
856 }
858 is_babble = is_host_capable() && (musb->int_usb & MUSB_INTR_BABBLE);
859 if (is_babble && musb->enable_babble_work)
860 musb->int_usb |= MUSB_INTR_DISCONNECT;
862 if (usbintr & (USB_INTR_DRVVBUS << USB_INTR_USB_SHIFT)) {
863 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
864 void __iomem *mregs = musb->mregs;
865 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
866 int err;
868 err = is_host_enabled(musb) && (musb->int_usb &
869 MUSB_INTR_VBUSERROR);
870 if (err) {
871 /*
872 * The Mentor core doesn't debounce VBUS as needed
873 * to cope with device connect current spikes. This
874 * means it's not uncommon for bus-powered devices
875 * to get VBUS errors during enumeration.
876 *
877 * This is a workaround, but newer RTL from Mentor
878 * seems to allow a better one: "re"-starting sessions
879 * without waiting for VBUS to stop registering in
880 * devctl.
881 */
882 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
883 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
884 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
885 WARNING("VBUS error workaround (delay coming)\n");
886 } else if (is_host_enabled(musb) && drvvbus) {
887 musb->is_active = 1;
888 MUSB_HST_MODE(musb);
889 musb->xceiv->default_a = 1;
890 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
891 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
892 del_timer(&otg_workaround);
893 } else {
894 musb->is_active = 0;
895 MUSB_DEV_MODE(musb);
896 musb->xceiv->default_a = 0;
897 musb->xceiv->state = OTG_STATE_B_IDLE;
898 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
899 }
901 /* NOTE: this must complete power-on within 100 ms. */
902 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
903 drvvbus ? "on" : "off",
904 otg_state_string(musb),
905 err ? " ERROR" : "",
906 devctl);
907 ret = IRQ_HANDLED;
908 }
910 if (musb->int_tx || musb->int_rx || musb->int_usb)
911 ret |= musb_interrupt(musb);
913 eoi:
914 /* EOI needs to be written for the IRQ to be re-asserted. */
915 if (ret == IRQ_HANDLED || epintr || usbintr) {
916 /* write EOI */
917 musb_writel(reg_base, USB_IRQ_EOI, 1);
918 }
920 /* Poll for ID change */
921 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
922 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
924 spin_unlock_irqrestore(&musb->lock, flags);
926 if (ret != IRQ_HANDLED) {
927 if (epintr || usbintr)
928 /*
929 * We sometimes get unhandled IRQs in the peripheral
930 * mode from EP0 and SOF...
931 */
932 DBG(2, "Unhandled USB IRQ %08x-%08x\n",
933 epintr, usbintr);
934 else if (printk_ratelimit())
935 /*
936 * We've seen series of spurious interrupts in the
937 * peripheral mode after USB reset and then after some
938 * time a real interrupt storm starting...
939 */
940 DBG(2, "Spurious IRQ, CPPI 4.1 status %08x, %08x\n",
941 pend1, pend2);
942 }
944 if (is_babble) {
945 if (!musb->enable_babble_work) {
946 musb_writeb(musb->mregs, MUSB_DEVCTL,
947 musb_readb(musb->mregs, MUSB_DEVCTL) |
948 MUSB_DEVCTL_SESSION);
949 } else {
950 ERR("Babble: devtcl(%x)Restarting musb....\n",
951 musb_readb(musb->mregs, MUSB_DEVCTL));
952 schedule_work(&musb->work);
953 }
954 }
955 return ret;
956 }
957 int ti81xx_musb_set_mode(struct musb *musb, u8 musb_mode)
958 {
959 void __iomem *reg_base = musb->ctrl_base;
960 u32 regval;
962 /* TODO: implement this using CONF0 */
963 if (musb_mode == MUSB_HOST) {
964 regval = musb_readl(reg_base, USB_MODE_REG);
966 regval &= ~USBMODE_USBID_HIGH;
967 if (usbid_sw_ctrl && cpu_is_ti816x())
968 regval |= USBMODE_USBID_MUXSEL;
970 musb_writel(reg_base, USB_MODE_REG, regval);
971 musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
972 DBG(4, "host: value of mode reg=%x regval(%x)\n",
973 musb_readl(reg_base, USB_MODE_REG), regval);
974 } else if (musb_mode == MUSB_PERIPHERAL) {
975 /* TODO commmented writing 8 to USB_MODE_REG device
976 mode is not working */
977 regval = musb_readl(reg_base, USB_MODE_REG);
979 regval |= USBMODE_USBID_HIGH;
980 if (usbid_sw_ctrl && cpu_is_ti816x())
981 regval |= USBMODE_USBID_MUXSEL;
983 musb_writel(reg_base, USB_MODE_REG, regval);
984 DBG(4, "device: value of mode reg=%x regval(%x)\n",
985 musb_readl(reg_base, USB_MODE_REG), regval);
986 } else if (musb_mode == MUSB_OTG) {
987 musb_writel(musb->ctrl_base, USB_PHY_UTMI_REG, 0x02);
988 } else
989 return -EIO;
991 return 0;
992 }
994 int ti81xx_musb_init(struct musb *musb)
995 {
996 void __iomem *reg_base = musb->ctrl_base;
997 struct device *dev = musb->controller;
998 struct musb_hdrc_platform_data *plat = dev->platform_data;
999 struct omap_musb_board_data *data = plat->board_data;
1000 u32 rev, status = 0;
1001 u8 mode;
1003 if (musb->id < 2)
1004 gmusb[musb->id] = musb;
1006 usb_nop_xceiv_register(musb->id);
1008 musb->xceiv = otg_get_transceiver(musb->id);
1009 if (!musb->xceiv)
1010 return -ENODEV;
1012 status = pm_runtime_get_sync(dev);
1013 if (status < 0) {
1014 dev_err(dev, "pm_runtime_get_sync FAILED");
1015 goto err1;
1016 }
1018 /* mentor is at offset of 0x400 in am3517/ti81xx */
1019 musb->mregs += USB_MENTOR_CORE_OFFSET;
1021 /* usb subsystem init */
1022 usbotg_ss_init(musb);
1024 /* Returns zero if e.g. not clocked */
1025 rev = musb_readl(reg_base, USB_REVISION_REG);
1026 if (!rev)
1027 return -ENODEV;
1029 if (is_host_enabled(musb))
1030 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
1032 /* Reset the controller */
1033 musb_writel(reg_base, USB_CTRL_REG, USB_SOFT_RESET_MASK);
1035 /* wait till reset bit clears */
1036 while ((musb_readl(reg_base, USB_CTRL_REG) & 0x1))
1037 cpu_relax();
1039 /* Start the on-chip PHY and its PLL. */
1040 if (data->set_phy_power)
1041 data->set_phy_power(1);
1043 msleep(5);
1045 #ifdef CONFIG_USB_TI_CPPI41_DMA
1046 cppi41_init(musb);
1047 #endif
1049 musb->a_wait_bcon = A_WAIT_BCON_TIMEOUT;
1050 musb->isr = ti81xx_interrupt;
1052 if (cpu_is_ti816x())
1053 usbid_sw_ctrl = 1;
1055 if (is_otg_enabled(musb)) {
1056 /* if usb-id contolled through software for ti816x then
1057 * configure the usb0 in peripheral mode and usb1 in
1058 * host mode
1059 */
1060 if (usbid_sw_ctrl && cpu_is_ti816x())
1061 mode = musb->id ? MUSB_HOST : MUSB_PERIPHERAL;
1062 else
1063 mode = MUSB_OTG;
1064 } else
1065 /* set musb controller to host mode */
1066 mode = is_host_enabled(musb) ? MUSB_HOST : MUSB_PERIPHERAL;
1068 /* set musb controller to host mode */
1069 musb_platform_set_mode(musb, mode);
1071 /* enable babble workaround */
1072 INIT_WORK(&musb->work, evm_deferred_musb_restart);
1073 musb->enable_babble_work = 0;
1075 musb_writel(reg_base, USB_IRQ_EOI, 0);
1076 usbss_write(USBSS_IRQ_EOI, 0);
1078 return 0;
1079 err1:
1080 pm_runtime_disable(dev);
1081 return status;
1082 }
1084 /* TI81xx supports only 32bit read operation */
1085 void ti81xx_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
1086 {
1087 void __iomem *fifo = hw_ep->fifo;
1088 u32 val;
1089 int i;
1091 /* Read for 32bit-aligned destination address */
1092 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
1093 readsl(fifo, dst, len >> 2);
1094 dst += len & ~0x03;
1095 len &= 0x03;
1096 }
1097 /*
1098 * Now read the remaining 1 to 3 byte or complete length if
1099 * unaligned address.
1100 */
1101 if (len > 4) {
1102 for (i = 0; i < (len >> 2); i++) {
1103 *(u32 *) dst = musb_readl(fifo, 0);
1104 dst += 4;
1105 }
1106 len &= 0x03;
1107 }
1108 if (len > 0) {
1109 val = musb_readl(fifo, 0);
1110 memcpy(dst, &val, len);
1111 }
1112 }
1114 int ti81xx_musb_exit(struct musb *musb)
1115 {
1116 struct device *dev = musb->controller;
1117 struct musb_hdrc_platform_data *plat = dev->platform_data;
1118 struct omap_musb_board_data *data = plat->board_data;
1120 if (is_host_enabled(musb))
1121 del_timer_sync(&otg_workaround);
1123 /* Shutdown the on-chip PHY and its PLL. */
1124 if (data->set_phy_power)
1125 data->set_phy_power(0);
1127 otg_put_transceiver(musb->xceiv);
1128 usb_nop_xceiv_unregister(musb->id);
1130 return 0;
1131 }
1133 static struct musb_platform_ops ti81xx_ops = {
1134 .fifo_mode = 4,
1135 .flags = MUSB_GLUE_EP_ADDR_FLAT_MAPPING | MUSB_GLUE_DMA_CPPI41,
1136 .init = ti81xx_musb_init,
1137 .exit = ti81xx_musb_exit,
1139 .enable = ti81xx_musb_enable,
1140 .disable = ti81xx_musb_disable,
1142 .try_idle = ti81xx_musb_try_idle,
1143 .set_mode = ti81xx_musb_set_mode,
1145 .read_fifo = ti81xx_musb_read_fifo,
1146 .write_fifo = musb_write_fifo,
1148 .dma_controller_create = cppi41_dma_controller_create,
1149 .dma_controller_destroy = cppi41_dma_controller_destroy,
1150 .simulate_babble_intr = musb_simulate_babble,
1151 };
1153 static int __init ti81xx_probe(struct platform_device *pdev)
1154 {
1155 struct ti81xx_glue *glue;
1156 struct platform_device *musb;
1157 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
1158 int ret;
1159 struct clk *otg_fck = NULL;
1161 pdev->num_resources = 2;
1162 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1163 if (!glue) {
1164 dev_err(&pdev->dev, "unable to allocate memory\n");
1165 return -ENOMEM;
1166 }
1168 if (cpu_is_ti816x())
1169 glue->clk = clk_get(&pdev->dev, "usbotg_ick");
1170 else
1171 glue->clk = clk_get(&pdev->dev, "usb_ick");
1173 if (IS_ERR(glue->clk)) {
1174 dev_err(&pdev->dev, "unable to get clock\n");
1175 ret = PTR_ERR(glue->clk);
1176 goto err0;
1177 }
1179 musb = platform_device_alloc("musb-hdrc", pdev->id);
1180 if (!musb) {
1181 dev_err(&pdev->dev, "failed to allocate musb device\n");
1182 ret = -ENOMEM;
1183 goto err1;
1184 }
1186 musb->dev.parent = &pdev->dev;
1187 musb->dev.dma_mask = &musb_dmamask;
1188 musb->dev.coherent_dma_mask = musb_dmamask;
1190 glue->dev = &pdev->dev;
1191 glue->musb = musb;
1193 pdata->platform_ops = &ti81xx_ops;
1195 platform_set_drvdata(pdev, glue);
1196 ret = platform_device_add_resources(musb, pdev->resource,
1197 pdev->num_resources);
1198 if (ret) {
1199 dev_err(&pdev->dev, "failed to add resources\n");
1200 goto err3;
1201 }
1203 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
1204 if (ret) {
1205 dev_err(&pdev->dev, "failed to add platform_data\n");
1206 goto err2;
1207 }
1209 ret = clk_enable(glue->clk);
1210 if (ret) {
1211 dev_err(&pdev->dev, "failed to enable clock\n");
1212 goto err2;
1213 }
1215 /* Enable musb phy clock */
1216 if (cpu_is_ti816x())
1217 otg_fck = clk_get(NULL, "usbotg_ick");
1218 else if (cpu_is_ti814x() && musb->id == 0)
1219 otg_fck = clk_get(NULL, "usb_phy0_rclk_ick");
1220 else if (cpu_is_ti814x() && musb->id == 1)
1221 otg_fck = clk_get(NULL, "usb_phy1_rclk_ick");
1223 clk_enable(otg_fck);
1224 DBG(2, "usbotg_phy_ck=%lud\n", clk_get_rate(otg_fck));
1226 platform_set_drvdata(pdev, glue);
1227 glue->dev = &pdev->dev;
1228 glue->phy_clk = otg_fck;
1230 ret = platform_device_add(musb);
1231 if (ret) {
1232 dev_err(&pdev->dev, "failed to register musb device\n");
1233 goto err3;
1234 }
1236 return 0;
1238 err3:
1239 clk_disable(glue->clk);
1241 err2:
1242 platform_device_put(musb);
1244 err1:
1245 clk_put(glue->clk);
1247 err0:
1248 kfree(glue);
1250 return ret;
1251 }
1253 static int __exit ti81xx_remove(struct platform_device *pdev)
1254 {
1255 struct ti81xx_glue *glue = platform_get_drvdata(pdev);
1257 platform_device_del(glue->musb);
1258 platform_device_put(glue->musb);
1260 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1261 #ifdef CONFIG_USB_TI_CPPI41_DMA
1262 cppi41_free();
1263 #endif
1264 usbotg_ss_uninit();
1265 #endif
1266 clk_disable(glue->clk);
1267 clk_disable(glue->phy_clk);
1268 clk_put(glue->clk);
1269 clk_put(glue->phy_clk);
1270 kfree(glue);
1271 pdev->num_resources = 0;
1273 return 0;
1274 }
1276 #ifdef CONFIG_PM
1277 static int ti81xx_suspend(struct device *dev)
1278 {
1279 struct ti81xx_glue *glue = dev_get_drvdata(dev);
1280 struct musb_hdrc_platform_data *plat = dev->platform_data;
1281 struct omap_musb_board_data *data = plat->board_data;
1282 int i;
1284 /* Shutdown the on-chip PHY and its PLL. */
1285 for (i = 0; i <= data->instances; ++i) {
1286 if (data->set_phy_power)
1287 data->set_phy_power(i);
1288 }
1290 /* disable the common usbss interface clock */
1291 clk_disable(glue->ick);
1292 return 0;
1293 }
1295 static int ti81xx_resume(struct device *dev)
1296 {
1297 struct ti81xx_glue *glue = dev_get_drvdata(dev);
1298 struct musb_hdrc_platform_data *plat = dev->platform_data;
1299 struct omap_musb_board_data *data = plat->board_data;
1300 int ret, i;
1302 /* Start the on-chip PHY and its PLL. */
1303 for (i = 0; i <= data->instances; ++i) {
1304 if (data->set_phy_power)
1305 data->set_phy_power(i);
1306 }
1308 /* enable the common usbss interface clock */
1309 ret = clk_enable(glue->ick);
1310 if (ret) {
1311 dev_err(dev, "failed to enable iclock\n");
1312 return ret;
1313 }
1314 /* enable the common usbss functional clock */
1315 ret = clk_enable(glue->fck);
1316 if (ret) {
1317 dev_err(dev, "failed to enable fclock\n");
1318 return ret;
1319 }
1320 return 0;
1321 }
1323 static const struct dev_pm_ops ti81xx_pm_ops = {
1324 .suspend = ti81xx_suspend,
1325 .resume = ti81xx_resume,
1326 };
1328 #define DEV_PM_OPS (&ti81xx_pm_ops)
1329 #else
1330 #define DEV_PM_OPS NULL
1331 #endif
1333 static struct platform_driver ti81xx_musb_driver = {
1334 .remove = __exit_p(ti81xx_remove),
1335 .driver = {
1336 .name = "musb-ti81xx",
1337 .pm = DEV_PM_OPS,
1338 },
1339 };
1341 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1342 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
1343 MODULE_LICENSE("GPL v2");
1345 static int __init ti81xx_glue_init(void)
1346 {
1347 return platform_driver_probe(&ti81xx_musb_driver, ti81xx_probe);
1348 }
1349 subsys_initcall(ti81xx_glue_init);
1351 static void __exit ti81xx_glue_exit(void)
1352 {
1353 /* free the usbss irq */
1354 free_irq(TI81XX_IRQ_USBSS, 0);
1356 /* disable the interrupts */
1357 usbss_write(USBSS_IRQ_EOI, 0);
1358 usbss_write(USBSS_IRQ_ENABLE_SET, 0);
1359 usbss_write(USBSS_IRQ_DMA_ENABLE_0, 0);
1361 /* unregister platform driver */
1362 platform_driver_unregister(&ti81xx_musb_driver);
1364 #ifndef CONFIG_USB_GADGET_MUSB_HDRC
1365 #ifdef CONFIG_USB_TI_CPPI41_DMA
1366 cppi41_free();
1367 #endif
1368 usbotg_ss_uninit();
1369 #endif
1370 }
1371 module_exit(ti81xx_glue_exit);
1373 #ifdef CONFIG_PM
1374 void musb_platform_save_context(struct musb *musb,
1375 struct musb_context_registers *musb_context)
1376 {
1377 /* Save CPPI41 DMA related registers */
1378 }
1380 void musb_platform_restore_context(struct musb *musb,
1381 struct musb_context_registers *musb_context)
1382 {
1383 /* Restore CPPI41 DMA related registers */
1384 }
1385 #endif