1 /*
2 * Copyright (C) 2005-2006 by Texas Instruments
3 *
4 * The Inventra Controller Driver for Linux is free software; you
5 * can redistribute it and/or modify it under the terms of the GNU
6 * General Public License version 2 as published by the Free Software
7 * Foundation.
8 */
10 #ifndef __MUSB_HDRDF_H__
11 #define __MUSB_HDRDF_H__
13 #define TI81XX_USB_CPPIDMA_BASE 0x47402000
14 #define TI81XX_USB_CPPIDMA_LEN 0x5FFF
15 #define TI81XX_IRQ_USBSS 17
17 /* Netra USB susbsystem register offsets */
18 #define USBSS_REVISION 0x0000
19 #define USBSS_SYSCONFIG 0x0010
20 /* USBSS EOI interrupt register */
21 #define USBSS_IRQ_EOI 0x0020
22 /* USBSS interrupt generation/status register */
23 #define USBSS_IRQ_STATUS_RAW 0x0024
24 /* USBSS interrupt status register */
25 #define USBSS_IRQ_STATUS 0x0028
26 /* USBSS interrupt enable register */
27 #define USBSS_IRQ_ENABLE_SET 0x002c
28 /* USBSS interrupt clear register */
29 #define USBSS_IRQ_ENABLE_CLEAR 0x0030
30 /* USB0: TxDMA 8bit tx completion interrupt pacing
31 threshold value for ep1..15 */
32 #define USBSS_IRQ_DMA_THRESHOLD_TX0 0x0100
33 /* USB0: RxDMA 8bit rx completion interrupt pacing
34 threshold value for ep1..15 */
35 #define USBSS_IRQ_DMA_THRESHOLD_RX0 0x0110
36 /* USB1: TxDMA 8bit tx completion interrupt pacing
37 threshold value for ep1..15 */
38 #define USBSS_IRQ_DMA_THRESHOLD_TX1 0x0120
39 /* USB1: RxDMA 8bit rx completion interrupt pacing
40 threshold value for ep1..15 */
41 #define USBSS_IRQ_DMA_THRESHOLD_RX1 0x0130
42 /* USB0: TxDMA threshold enable tx completion for ep1..ep15
43 RxDMA threshold enable rx completion for ep1..ep15 */
44 #define USBSS_IRQ_DMA_ENABLE_0 0x0140
45 /* USB1: TxDMA threshold enable for ep1..ep15
46 RxDMA threshold enable for ep1..ep15 */
47 #define USBSS_IRQ_DMA_ENABLE_1 0x0144
48 /* USB0: TxDMA Frame threshold for tx completion for ep1..ep15
49 RxDMA Frame threshold for rx completion for ep1..ep15 */
50 #define USBSS_IRQ_FRAME_THRESHOLD_TX0 0x0200
51 #define USBSS_IRQ_FRAME_THRESHOLD_RX0 0x0210
52 /* USB1: TxDMA Frame threshold for tx completion for ep1..ep15
53 RxDMA Frame threshold for rx completion for ep1..ep15 */
54 #define USBSS_IRQ_FRAME_THRESHOLD_TX1 0x0220
55 #define USBSS_IRQ_FRAME_THRESHOLD_RX1 0x0230
56 /* USB0: Frame threshold enable tx completion for ep1..ep15
57 Frame threshold enable rx completion for ep1..ep15 */
58 #define USBSS_IRQ_FRAME_ENABLE_0 0x0240
59 #define USBSS_IRQ_FRAME_ENABLE_1 0x0244
62 /* USB 2.0 OTG module registers */
63 #define USB_REVISION_REG 0x0000
64 #define USB_CTRL_REG 0x0014
65 #define USB_STAT_REG 0x0018
66 #define USB_IRQ_MERGED_STATUS 0x0020
67 #define USB_IRQ_EOI 0x0024
68 #define USB_IRQ_STATUS_RAW_0 0x0028
69 #define USB_IRQ_STATUS_RAW_1 0x002c
70 #define USB_IRQ_STATUS_0 0x0030
71 #define USB_IRQ_STATUS_1 0x0034
72 #define USB_IRQ_ENABLE_SET_0 0x0038
73 #define USB_IRQ_ENABLE_SET_1 0x003c
74 #define USB_IRQ_ENABLE_CLR_0 0x0040
75 #define USB_IRQ_ENABLE_CLR_1 0x0044
77 #define USB_EP_INTR_SET_REG (USB_IRQ_ENABLE_SET_0)
78 #define USB_CORE_INTR_SET_REG (USB_IRQ_ENABLE_SET_1)
79 #define USB_EP_INTR_CLEAR_REG (USB_IRQ_ENABLE_CLR_0)
80 #define USB_CORE_INTR_CLEAR_REG (USB_IRQ_ENABLE_CLR_1)
81 #define USB_EP_INTR_STATUS_REG (USB_IRQ_STATUS_0)
82 #define USB_CORE_INTR_STATUS_REG (USB_IRQ_STATUS_1)
84 #define USB_GRNDIS_EPSIZE_OFFS 0X0080
85 #define USB_SRP_FIX_TIME_REG 0x00d4
86 #define USB_PHY_UTMI_REG 0x00e0
87 #define USB_PHY_UTMI_LB_REG 0x00e4
88 #define USB_MODE_REG 0x00e8
90 #define QUEUE_THRESHOLD_INTR_ENABLE_REG 0xc0
91 #define QUEUE_63_THRESHOLD_REG 0xc4
92 #define QUEUE_63_THRESHOLD_INTR_CLEAR_REG 0xc8
93 #define QUEUE_65_THRESHOLD_REG 0xd4
94 #define QUEUE_65_THRESHOLD_INTR_CLEAR_REG 0xd8
96 /* Control register bits */
97 #define USB_SOFT_RESET_MASK 1
99 /* Mode register bits */
100 #define USB_MODE_SHIFT(n) ((((n) - 1) << 1))
101 #define USB_MODE_MASK(n) (3 << USB_MODE_SHIFT(n))
102 #define USB_RX_MODE_SHIFT(n) USB_MODE_SHIFT(n)
103 #define USB_TX_MODE_SHIFT(n) USB_MODE_SHIFT(n)
104 #define USB_RX_MODE_MASK(n) USB_MODE_MASK(n)
105 #define USB_TX_MODE_MASK(n) USB_MODE_MASK(n)
106 #define USB_TRANSPARENT_MODE 0
107 #define USB_RNDIS_MODE 1
108 #define USB_CDC_MODE 2
109 #define USB_GENERIC_RNDIS_MODE 3
111 /* AutoReq register bits */
112 #define USB_RX_AUTOREQ_SHIFT(n) (((n) - 1) << 1)
113 #define USB_RX_AUTOREQ_MASK(n) (3 << USB_RX_AUTOREQ_SHIFT(n))
114 #define USB_NO_AUTOREQ 0
115 #define USB_AUTOREQ_ALL_BUT_EOP 1
116 #define USB_AUTOREQ_ALWAYS 3
118 /* Teardown register bits */
119 #define USB_TX_TDOWN_SHIFT(n) (16 + (n))
120 #define USB_TX_TDOWN_MASK(n) (1 << USB_TX_TDOWN_SHIFT(n))
121 #define USB_RX_TDOWN_SHIFT(n) (n)
122 #define USB_RX_TDOWN_MASK(n) (1 << USB_RX_TDOWN_SHIFT(n))
124 /* USB interrupt register bits */
125 #define USB_INTR_USB_SHIFT 0
126 #define USB_INTR_USB_MASK (0x1ff << USB_INTR_USB_SHIFT) /* 8 Mentor */
127 /* interrupts and DRVVBUS interrupt */
128 #define USB_INTR_DRVVBUS 0x100
129 #define USB_INTR_RX_SHIFT 16
130 #define USB_INTR_TX_SHIFT 0
132 #define USB_MENTOR_CORE_OFFSET 0x400
133 #define USB_CPPI41_NUM_CH 15
135 #define MAX_MUSB_INSTANCE 2
136 /* CPPI 4.1 queue manager registers */
137 #define QMGR_PEND0_REG 0x4090
138 #define QMGR_PEND1_REG 0x4094
139 #define QMGR_PEND2_REG 0x4098
141 #define QMGR_RGN_OFFS 0x4000
142 #define QMRG_DESCRGN_OFFS 0x5000
143 #define QMGR_REG_OFFS 0x6000
144 #define QMGR_STAT_OFFS 0x7000
145 #define DMA_GLBCTRL_OFFS 0x2000
146 #define DMA_CHCTRL_OFFS 0x2800
147 #define DMA_SCHED_OFFS 0x3000
148 #define DMA_SCHEDTBL_OFFS 0x3800
150 #define USB_TX_EP_MASK 0xffff /* EP0 + 15 Tx EPs */
151 #define USB_RX_EP_MASK 0xfffe /* 15 Rx EPs */
153 #define USB_TX_INTR_MASK (USB_TX_EP_MASK << USB_INTR_TX_SHIFT)
154 #define USB_RX_INTR_MASK (USB_RX_EP_MASK << USB_INTR_RX_SHIFT)
156 #define A_WAIT_BCON_TIMEOUT 1100 /* in ms */
158 #define USBSS_INTR_RX_STARV 0x00000001
159 #define USBSS_INTR_PD_CMPL 0x00000004
160 #define USBSS_INTR_TX_CMPL 0x00000500
161 #define USBSS_INTR_RX_CMPL 0x00000A00
162 #define USBSS_INTR_FLAGS (USBSS_INTR_PD_CMPL | USBSS_INTR_TX_CMPL \
163 | USBSS_INTR_RX_CMPL)
165 #define USBMODE_USBID_MUXSEL 0x80
166 #define USBMODE_USBID_HIGH 0x100
168 extern void usb_nop_xceiv_register(int id);
169 #endif