usb: musb: same MUSB_OFFSET/musb_ep_select for all controller
[sitara-epos/sitara-epos-kernel.git] / drivers / usb / musb / tusb6010.c
1 /*
2  * TUSB6010 USB 2.0 OTG Dual Role controller
3  *
4  * Copyright (C) 2006 Nokia Corporation
5  * Tony Lindgren <tony@atomide.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  * Notes:
12  * - Driver assumes that interface to external host (main CPU) is
13  *   configured for NOR FLASH interface instead of VLYNQ serial
14  *   interface.
15  */
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/init.h>
21 #include <linux/prefetch.h>
22 #include <linux/usb.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/dma-mapping.h>
27 #include "musb_core.h"
29 struct tusb6010_glue {
30         struct device           *dev;
31         struct platform_device  *musb;
32 };
34 static void tusb_musb_set_vbus(struct musb *musb, int is_on);
36 #define TUSB_REV_MAJOR(reg_val)         ((reg_val >> 4) & 0xf)
37 #define TUSB_REV_MINOR(reg_val)         (reg_val & 0xf)
39 /*
40  * Checks the revision. We need to use the DMA register as 3.0 does not
41  * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
42  */
43 static u16 tusb_get_revision(struct musb *musb)
44 {
45         void __iomem    *tbase = musb->ctrl_base;
46         u32             die_id;
47         u16             rev;
49         rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
50         if (TUSB_REV_MAJOR(rev) == 3) {
51                 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
52                                 TUSB_DIDR1_HI));
53                 if (die_id >= TUSB_DIDR1_HI_REV_31)
54                         rev |= 1;
55         }
57         return rev;
58 }
59 EXPORT_SYMBOL_GPL(tusb_get_revision);
61 static int tusb_print_revision(struct musb *musb)
62 {
63         void __iomem    *tbase = musb->ctrl_base;
64         u16             rev;
66         rev = tusb_get_revision(musb);
68         pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
69                 "prcm",
70                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
71                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
72                 "int",
73                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
74                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
75                 "gpio",
76                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
77                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
78                 "dma",
79                 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
80                 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
81                 "dieid",
82                 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
83                 "rev",
84                 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
86         return tusb_get_revision(musb);
87 }
89 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
90                                 | TUSB_PHY_OTG_CTRL_TESTM0)
92 /*
93  * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
94  * Disables power detection in PHY for the duration of idle.
95  */
96 static void tusb_wbus_quirk(struct musb *musb, int enabled)
97 {
98         void __iomem    *tbase = musb->ctrl_base;
99         static u32      phy_otg_ctrl, phy_otg_ena;
100         u32             tmp;
102         if (enabled) {
103                 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
104                 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
105                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
106                                 | phy_otg_ena | WBUS_QUIRK_MASK;
107                 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
108                 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
109                 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
110                 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
111                 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
112                         musb_readl(tbase, TUSB_PHY_OTG_CTRL),
113                         musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
114         } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
115                                         & TUSB_PHY_OTG_CTRL_TESTM2) {
116                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
117                 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
118                 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
119                 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
120                 dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
121                         musb_readl(tbase, TUSB_PHY_OTG_CTRL),
122                         musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
123                 phy_otg_ctrl = 0;
124                 phy_otg_ena = 0;
125         }
128 /*
129  * TUSB 6010 may use a parallel bus that doesn't support byte ops;
130  * so both loading and unloading FIFOs need explicit byte counts.
131  */
133 static inline void
134 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
136         u32             val;
137         int             i;
139         if (len > 4) {
140                 for (i = 0; i < (len >> 2); i++) {
141                         memcpy(&val, buf, 4);
142                         musb_writel(fifo, 0, val);
143                         buf += 4;
144                 }
145                 len %= 4;
146         }
147         if (len > 0) {
148                 /* Write the rest 1 - 3 bytes to FIFO */
149                 memcpy(&val, buf, len);
150                 musb_writel(fifo, 0, val);
151         }
154 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
155                                                 void __iomem *buf, u16 len)
157         u32             val;
158         int             i;
160         if (len > 4) {
161                 for (i = 0; i < (len >> 2); i++) {
162                         val = musb_readl(fifo, 0);
163                         memcpy(buf, &val, 4);
164                         buf += 4;
165                 }
166                 len %= 4;
167         }
168         if (len > 0) {
169                 /* Read the rest 1 - 3 bytes from FIFO */
170                 val = musb_readl(fifo, 0);
171                 memcpy(buf, &val, len);
172         }
175 static void tusb_musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
176                 const u8 *buf)
178         struct musb *musb = hw_ep->musb;
179         void __iomem    *ep_conf = hw_ep->conf;
180         void __iomem    *fifo = hw_ep->fifo;
181         u8              epnum = hw_ep->epnum;
183         prefetch(buf);
185         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
186                         'T', epnum, fifo, len, buf);
188         if (epnum)
189                 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
190                         TUSB_EP_CONFIG_XFR_SIZE(len));
191         else
192                 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
193                         TUSB_EP0_CONFIG_XFR_SIZE(len));
195         if (likely((0x01 & (unsigned long) buf) == 0)) {
197                 /* Best case is 32bit-aligned destination address */
198                 if ((0x02 & (unsigned long) buf) == 0) {
199                         if (len >= 4) {
200                                 writesl(fifo, buf, len >> 2);
201                                 buf += (len & ~0x03);
202                                 len &= 0x03;
203                         }
204                 } else {
205                         if (len >= 2) {
206                                 u32 val;
207                                 int i;
209                                 /* Cannot use writesw, fifo is 32-bit */
210                                 for (i = 0; i < (len >> 2); i++) {
211                                         val = (u32)(*(u16 *)buf);
212                                         buf += 2;
213                                         val |= (*(u16 *)buf) << 16;
214                                         buf += 2;
215                                         musb_writel(fifo, 0, val);
216                                 }
217                                 len &= 0x03;
218                         }
219                 }
220         }
222         if (len > 0)
223                 tusb_fifo_write_unaligned(fifo, buf, len);
226 static void tusb_musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
228         struct musb *musb = hw_ep->musb;
229         void __iomem    *ep_conf = hw_ep->conf;
230         void __iomem    *fifo = hw_ep->fifo;
231         u8              epnum = hw_ep->epnum;
233         dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
234                         'R', epnum, fifo, len, buf);
236         if (epnum)
237                 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
238                         TUSB_EP_CONFIG_XFR_SIZE(len));
239         else
240                 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
242         if (likely((0x01 & (unsigned long) buf) == 0)) {
244                 /* Best case is 32bit-aligned destination address */
245                 if ((0x02 & (unsigned long) buf) == 0) {
246                         if (len >= 4) {
247                                 readsl(fifo, buf, len >> 2);
248                                 buf += (len & ~0x03);
249                                 len &= 0x03;
250                         }
251                 } else {
252                         if (len >= 2) {
253                                 u32 val;
254                                 int i;
256                                 /* Cannot use readsw, fifo is 32-bit */
257                                 for (i = 0; i < (len >> 2); i++) {
258                                         val = musb_readl(fifo, 0);
259                                         *(u16 *)buf = (u16)(val & 0xffff);
260                                         buf += 2;
261                                         *(u16 *)buf = (u16)(val >> 16);
262                                         buf += 2;
263                                 }
264                                 len &= 0x03;
265                         }
266                 }
267         }
269         if (len > 0)
270                 tusb_fifo_read_unaligned(fifo, buf, len);
273 static struct musb *the_musb;
275 /* This is used by gadget drivers, and OTG transceiver logic, allowing
276  * at most mA current to be drawn from VBUS during a Default-B session
277  * (that is, while VBUS exceeds 4.4V).  In Default-A (including pure host
278  * mode), or low power Default-B sessions, something else supplies power.
279  * Caller must take care of locking.
280  */
281 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
283         struct musb     *musb = the_musb;
284         void __iomem    *tbase = musb->ctrl_base;
285         u32             reg;
287         /* tps65030 seems to consume max 100mA, with maybe 60mA available
288          * (measured on one board) for things other than tps and tusb.
289          *
290          * Boards sharing the CPU clock with CLKIN will need to prevent
291          * certain idle sleep states while the USB link is active.
292          *
293          * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
294          * The actual current usage would be very board-specific.  For now,
295          * it's simpler to just use an aggregate (also board-specific).
296          */
297         if (x->default_a || mA < (musb->min_power << 1))
298                 mA = 0;
300         reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
301         if (mA) {
302                 musb->is_bus_powered = 1;
303                 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
304         } else {
305                 musb->is_bus_powered = 0;
306                 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
307         }
308         musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
310         dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
311         return 0;
314 /* workaround for issue 13:  change clock during chip idle
315  * (to be fixed in rev3 silicon) ... symptoms include disconnect
316  * or looping suspend/resume cycles
317  */
318 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
320         void __iomem    *tbase = musb->ctrl_base;
321         u32             reg;
323         reg = musb_readl(tbase, TUSB_PRCM_CONF);
324         reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
326         /* 0 = refclk (clkin, XI)
327          * 1 = PHY 60 MHz (internal PLL)
328          * 2 = not supported
329          * 3 = what?
330          */
331         if (mode > 0)
332                 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
334         musb_writel(tbase, TUSB_PRCM_CONF, reg);
336         /* FIXME tusb6010_platform_retime(mode == 0); */
339 /*
340  * Idle TUSB6010 until next wake-up event; NOR access always wakes.
341  * Other code ensures that we idle unless we're connected _and_ the
342  * USB link is not suspended ... and tells us the relevant wakeup
343  * events.  SW_EN for voltage is handled separately.
344  */
345 static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
347         void __iomem    *tbase = musb->ctrl_base;
348         u32             reg;
350         if ((wakeup_enables & TUSB_PRCM_WBUS)
351                         && (tusb_get_revision(musb) == TUSB_REV_30))
352                 tusb_wbus_quirk(musb, 1);
354         tusb_set_clock_source(musb, 0);
356         wakeup_enables |= TUSB_PRCM_WNORCS;
357         musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
359         /* REVISIT writeup of WID implies that if WID set and ID is grounded,
360          * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
361          * Presumably that's mostly to save power, hence WID is immaterial ...
362          */
364         reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
365         /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
366         if (is_host_active(musb)) {
367                 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
368                 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
369         } else {
370                 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
371                 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
372         }
373         reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
374         musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
376         dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
379 /*
380  * Updates cable VBUS status. Caller must take care of locking.
381  */
382 static int tusb_musb_vbus_status(struct musb *musb)
384         void __iomem    *tbase = musb->ctrl_base;
385         u32             otg_stat, prcm_mngmt;
386         int             ret = 0;
388         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
389         prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
391         /* Temporarily enable VBUS detection if it was disabled for
392          * suspend mode. Unless it's enabled otg_stat and devctl will
393          * not show correct VBUS state.
394          */
395         if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
396                 u32 tmp = prcm_mngmt;
397                 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
398                 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
399                 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
400                 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
401         }
403         if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
404                 ret = 1;
406         return ret;
409 static struct timer_list musb_idle_timer;
411 static void musb_do_idle(unsigned long _musb)
413         struct musb     *musb = (void *)_musb;
414         unsigned long   flags;
416         spin_lock_irqsave(&musb->lock, flags);
418         switch (musb->xceiv->state) {
419         case OTG_STATE_A_WAIT_BCON:
420                 if ((musb->a_wait_bcon != 0)
421                         && (musb->idle_timeout == 0
422                                 || time_after(jiffies, musb->idle_timeout))) {
423                         dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
424                                         otg_state_string(musb->xceiv->state));
425                 }
426                 /* FALLTHROUGH */
427         case OTG_STATE_A_IDLE:
428                 tusb_musb_set_vbus(musb, 0);
429         default:
430                 break;
431         }
433         if (!musb->is_active) {
434                 u32     wakeups;
436                 /* wait until khubd handles port change status */
437                 if (is_host_active(musb) && (musb->port1_status >> 16))
438                         goto done;
440                 if (is_peripheral_enabled(musb) && !musb->gadget_driver) {
441                         wakeups = 0;
442                 } else {
443                         wakeups = TUSB_PRCM_WHOSTDISCON
444                                 | TUSB_PRCM_WBUS
445                                         | TUSB_PRCM_WVBUS;
446                         if (is_otg_enabled(musb))
447                                 wakeups |= TUSB_PRCM_WID;
448                 }
449                 tusb_allow_idle(musb, wakeups);
450         }
451 done:
452         spin_unlock_irqrestore(&musb->lock, flags);
455 /*
456  * Maybe put TUSB6010 into idle mode mode depending on USB link status,
457  * like "disconnected" or "suspended".  We'll be woken out of it by
458  * connect, resume, or disconnect.
459  *
460  * Needs to be called as the last function everywhere where there is
461  * register access to TUSB6010 because of NOR flash wake-up.
462  * Caller should own controller spinlock.
463  *
464  * Delay because peripheral enables D+ pullup 3msec after SE0, and
465  * we don't want to treat that full speed J as a wakeup event.
466  * ... peripherals must draw only suspend current after 10 msec.
467  */
468 static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
470         unsigned long           default_timeout = jiffies + msecs_to_jiffies(3);
471         static unsigned long    last_timer;
473         if (timeout == 0)
474                 timeout = default_timeout;
476         /* Never idle if active, or when VBUS timeout is not set as host */
477         if (musb->is_active || ((musb->a_wait_bcon == 0)
478                         && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
479                 dev_dbg(musb->controller, "%s active, deleting timer\n",
480                         otg_state_string(musb->xceiv->state));
481                 del_timer(&musb_idle_timer);
482                 last_timer = jiffies;
483                 return;
484         }
486         if (time_after(last_timer, timeout)) {
487                 if (!timer_pending(&musb_idle_timer))
488                         last_timer = timeout;
489                 else {
490                         dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
491                         return;
492                 }
493         }
494         last_timer = timeout;
496         dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
497                 otg_state_string(musb->xceiv->state),
498                 (unsigned long)jiffies_to_msecs(timeout - jiffies));
499         mod_timer(&musb_idle_timer, timeout);
502 /* ticks of 60 MHz clock */
503 #define DEVCLOCK                60000000
504 #define OTG_TIMER_MS(msecs)     ((msecs) \
505                 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
506                                 | TUSB_DEV_OTG_TIMER_ENABLE) \
507                 : 0)
509 static void tusb_musb_set_vbus(struct musb *musb, int is_on)
511         void __iomem    *tbase = musb->ctrl_base;
512         u32             conf, prcm, timer;
513         u8              devctl;
515         /* HDRC controls CPEN, but beware current surges during device
516          * connect.  They can trigger transient overcurrent conditions
517          * that must be ignored.
518          */
520         prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
521         conf = musb_readl(tbase, TUSB_DEV_CONF);
522         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
524         if (is_on) {
525                 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
526                 musb->xceiv->default_a = 1;
527                 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
528                 devctl |= MUSB_DEVCTL_SESSION;
530                 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
531                 MUSB_HST_MODE(musb);
532         } else {
533                 u32     otg_stat;
535                 timer = 0;
537                 /* If ID pin is grounded, we want to be a_idle */
538                 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
539                 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
540                         switch (musb->xceiv->state) {
541                         case OTG_STATE_A_WAIT_VRISE:
542                         case OTG_STATE_A_WAIT_BCON:
543                                 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
544                                 break;
545                         case OTG_STATE_A_WAIT_VFALL:
546                                 musb->xceiv->state = OTG_STATE_A_IDLE;
547                                 break;
548                         default:
549                                 musb->xceiv->state = OTG_STATE_A_IDLE;
550                         }
551                         musb->is_active = 0;
552                         musb->xceiv->default_a = 1;
553                         MUSB_HST_MODE(musb);
554                 } else {
555                         musb->is_active = 0;
556                         musb->xceiv->default_a = 0;
557                         musb->xceiv->state = OTG_STATE_B_IDLE;
558                         MUSB_DEV_MODE(musb);
559                 }
561                 devctl &= ~MUSB_DEVCTL_SESSION;
562                 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
563         }
564         prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
566         musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
567         musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
568         musb_writel(tbase, TUSB_DEV_CONF, conf);
569         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
571         dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
572                 otg_state_string(musb->xceiv->state),
573                 musb_readb(musb->mregs, MUSB_DEVCTL),
574                 musb_readl(tbase, TUSB_DEV_OTG_STAT),
575                 conf, prcm);
578 /*
579  * Sets the mode to OTG, peripheral or host by changing the ID detection.
580  * Caller must take care of locking.
581  *
582  * Note that if a mini-A cable is plugged in the ID line will stay down as
583  * the weak ID pull-up is not able to pull the ID up.
584  *
585  * REVISIT: It would be possible to add support for changing between host
586  * and peripheral modes in non-OTG configurations by reconfiguring hardware
587  * and then setting musb->board_mode. For now, only support OTG mode.
588  */
589 static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
591         void __iomem    *tbase = musb->ctrl_base;
592         u32             otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
594         if (musb->board_mode != MUSB_OTG) {
595                 ERR("Changing mode currently only supported in OTG mode\n");
596                 return -EINVAL;
597         }
599         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
600         phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
601         phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
602         dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
604         switch (musb_mode) {
606         case MUSB_HOST:         /* Disable PHY ID detect, ground ID */
607                 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
608                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
609                 dev_conf |= TUSB_DEV_CONF_ID_SEL;
610                 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
611                 break;
612         case MUSB_PERIPHERAL:   /* Disable PHY ID detect, keep ID pull-up on */
613                 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
614                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
615                 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
616                 break;
617         case MUSB_OTG:          /* Use PHY ID detection */
618                 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
619                 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
620                 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
621                 break;
623         default:
624                 dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
625                 return -EINVAL;
626         }
628         musb_writel(tbase, TUSB_PHY_OTG_CTRL,
629                         TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
630         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
631                         TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
632         musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
634         otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
635         if ((musb_mode == MUSB_PERIPHERAL) &&
636                 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
637                         INFO("Cannot be peripheral with mini-A cable "
638                         "otg_stat: %08x\n", otg_stat);
640         return 0;
643 static inline unsigned long
644 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
646         u32             otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
647         unsigned long   idle_timeout = 0;
649         /* ID pin */
650         if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
651                 int     default_a;
653                 if (is_otg_enabled(musb))
654                         default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
655                 else
656                         default_a = is_host_enabled(musb);
657                 dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
658                 musb->xceiv->default_a = default_a;
659                 tusb_musb_set_vbus(musb, default_a);
661                 /* Don't allow idling immediately */
662                 if (default_a)
663                         idle_timeout = jiffies + (HZ * 3);
664         }
666         /* VBUS state change */
667         if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
669                 /* B-dev state machine:  no vbus ~= disconnect */
670                 if ((is_otg_enabled(musb) && !musb->xceiv->default_a)
671                                 || !is_host_enabled(musb)) {
672                         /* ? musb_root_disconnect(musb); */
673                         musb->port1_status &=
674                                 ~(USB_PORT_STAT_CONNECTION
675                                 | USB_PORT_STAT_ENABLE
676                                 | USB_PORT_STAT_LOW_SPEED
677                                 | USB_PORT_STAT_HIGH_SPEED
678                                 | USB_PORT_STAT_TEST
679                                 );
681                         if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
682                                 dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
683                                 if (musb->xceiv->state != OTG_STATE_B_IDLE) {
684                                         /* INTR_DISCONNECT can hide... */
685                                         musb->xceiv->state = OTG_STATE_B_IDLE;
686                                         musb->int_usb |= MUSB_INTR_DISCONNECT;
687                                 }
688                                 musb->is_active = 0;
689                         }
690                         dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
691                                 otg_state_string(musb->xceiv->state), otg_stat);
692                         idle_timeout = jiffies + (1 * HZ);
693                         schedule_work(&musb->irq_work);
695                 } else /* A-dev state machine */ {
696                         dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
697                                 otg_state_string(musb->xceiv->state), otg_stat);
699                         switch (musb->xceiv->state) {
700                         case OTG_STATE_A_IDLE:
701                                 dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
702                                 musb_platform_set_vbus(musb, 1);
704                                 /* CONNECT can wake if a_wait_bcon is set */
705                                 if (musb->a_wait_bcon != 0)
706                                         musb->is_active = 0;
707                                 else
708                                         musb->is_active = 1;
710                                 /*
711                                  * OPT FS A TD.4.6 needs few seconds for
712                                  * A_WAIT_VRISE
713                                  */
714                                 idle_timeout = jiffies + (2 * HZ);
716                                 break;
717                         case OTG_STATE_A_WAIT_VRISE:
718                                 /* ignore; A-session-valid < VBUS_VALID/2,
719                                  * we monitor this with the timer
720                                  */
721                                 break;
722                         case OTG_STATE_A_WAIT_VFALL:
723                                 /* REVISIT this irq triggers during short
724                                  * spikes caused by enumeration ...
725                                  */
726                                 if (musb->vbuserr_retry) {
727                                         musb->vbuserr_retry--;
728                                         tusb_musb_set_vbus(musb, 1);
729                                 } else {
730                                         musb->vbuserr_retry
731                                                 = VBUSERR_RETRY_COUNT;
732                                         tusb_musb_set_vbus(musb, 0);
733                                 }
734                                 break;
735                         default:
736                                 break;
737                         }
738                 }
739         }
741         /* OTG timer expiration */
742         if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
743                 u8      devctl;
745                 dev_dbg(musb->controller, "%s timer, %03x\n",
746                         otg_state_string(musb->xceiv->state), otg_stat);
748                 switch (musb->xceiv->state) {
749                 case OTG_STATE_A_WAIT_VRISE:
750                         /* VBUS has probably been valid for a while now,
751                          * but may well have bounced out of range a bit
752                          */
753                         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
754                         if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
755                                 if ((devctl & MUSB_DEVCTL_VBUS)
756                                                 != MUSB_DEVCTL_VBUS) {
757                                         dev_dbg(musb->controller, "devctl %02x\n", devctl);
758                                         break;
759                                 }
760                                 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
761                                 musb->is_active = 0;
762                                 idle_timeout = jiffies
763                                         + msecs_to_jiffies(musb->a_wait_bcon);
764                         } else {
765                                 /* REVISIT report overcurrent to hub? */
766                                 ERR("vbus too slow, devctl %02x\n", devctl);
767                                 tusb_musb_set_vbus(musb, 0);
768                         }
769                         break;
770                 case OTG_STATE_A_WAIT_BCON:
771                         if (musb->a_wait_bcon != 0)
772                                 idle_timeout = jiffies
773                                         + msecs_to_jiffies(musb->a_wait_bcon);
774                         break;
775                 case OTG_STATE_A_SUSPEND:
776                         break;
777                 case OTG_STATE_B_WAIT_ACON:
778                         break;
779                 default:
780                         break;
781                 }
782         }
783         schedule_work(&musb->irq_work);
785         return idle_timeout;
788 static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
790         struct musb     *musb = __hci;
791         void __iomem    *tbase = musb->ctrl_base;
792         unsigned long   flags, idle_timeout = 0;
793         u32             int_mask, int_src;
795         spin_lock_irqsave(&musb->lock, flags);
797         /* Mask all interrupts to allow using both edge and level GPIO irq */
798         int_mask = musb_readl(tbase, TUSB_INT_MASK);
799         musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
801         int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
802         dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
804         musb->int_usb = (u8) int_src;
806         /* Acknowledge wake-up source interrupts */
807         if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
808                 u32     reg;
809                 u32     i;
811                 if (tusb_get_revision(musb) == TUSB_REV_30)
812                         tusb_wbus_quirk(musb, 0);
814                 /* there are issues re-locking the PLL on wakeup ... */
816                 /* work around issue 8 */
817                 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
818                         musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
819                         musb_writel(tbase, TUSB_SCRATCH_PAD, i);
820                         reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
821                         if (reg == i)
822                                 break;
823                         dev_dbg(musb->controller, "TUSB NOR not ready\n");
824                 }
826                 /* work around issue 13 (2nd half) */
827                 tusb_set_clock_source(musb, 1);
829                 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
830                 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
831                 if (reg & ~TUSB_PRCM_WNORCS) {
832                         musb->is_active = 1;
833                         schedule_work(&musb->irq_work);
834                 }
835                 dev_dbg(musb->controller, "wake %sactive %02x\n",
836                                 musb->is_active ? "" : "in", reg);
838                 /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
839         }
841         if (int_src & TUSB_INT_SRC_USB_IP_CONN)
842                 del_timer(&musb_idle_timer);
844         /* OTG state change reports (annoyingly) not issued by Mentor core */
845         if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
846                                 | TUSB_INT_SRC_OTG_TIMEOUT
847                                 | TUSB_INT_SRC_ID_STATUS_CHNG))
848                 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
850         /* TX dma callback must be handled here, RX dma callback is
851          * handled in tusb_omap_dma_cb.
852          */
853         if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
854                 u32     dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
855                 u32     real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
857                 dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
858                 real_dma_src = ~real_dma_src & dma_src;
859                 if (tusb_dma_omap() && real_dma_src) {
860                         int     tx_source = (real_dma_src & 0xffff);
861                         int     i;
863                         for (i = 1; i <= 15; i++) {
864                                 if (tx_source & (1 << i)) {
865                                         dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
866                                         musb_dma_completion(musb, i, 1);
867                                 }
868                         }
869                 }
870                 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
871         }
873         /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
874         if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
875                 u32     musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
877                 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
878                 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
879                 musb->int_tx = (musb_src & 0xffff);
880         } else {
881                 musb->int_rx = 0;
882                 musb->int_tx = 0;
883         }
885         if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
886                 musb_interrupt(musb);
888         /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
889         musb_writel(tbase, TUSB_INT_SRC_CLEAR,
890                 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
892         tusb_musb_try_idle(musb, idle_timeout);
894         musb_writel(tbase, TUSB_INT_MASK, int_mask);
895         spin_unlock_irqrestore(&musb->lock, flags);
897         return IRQ_HANDLED;
900 static int dma_off;
902 /*
903  * Enables TUSB6010. Caller must take care of locking.
904  * REVISIT:
905  * - Check what is unnecessary in MGC_HdrcStart()
906  */
907 static void tusb_musb_enable(struct musb *musb)
909         void __iomem    *tbase = musb->ctrl_base;
911         /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
912          * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
913         musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
915         /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
916         musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
917         musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
918         musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
920         /* Clear all subsystem interrups */
921         musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
922         musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
923         musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
925         /* Acknowledge pending interrupt(s) */
926         musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
928         /* Only 0 clock cycles for minimum interrupt de-assertion time and
929          * interrupt polarity active low seems to work reliably here */
930         musb_writel(tbase, TUSB_INT_CTRL_CONF,
931                         TUSB_INT_CTRL_CONF_INT_RELCYC(0));
933         irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
935         /* maybe force into the Default-A OTG state machine */
936         if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
937                         & TUSB_DEV_OTG_STAT_ID_STATUS))
938                 musb_writel(tbase, TUSB_INT_SRC_SET,
939                                 TUSB_INT_SRC_ID_STATUS_CHNG);
941         if (is_dma_capable() && dma_off)
942                 printk(KERN_WARNING "%s %s: dma not reactivated\n",
943                                 __FILE__, __func__);
944         else
945                 dma_off = 1;
948 /*
949  * Disables TUSB6010. Caller must take care of locking.
950  */
951 static void tusb_musb_disable(struct musb *musb)
953         void __iomem    *tbase = musb->ctrl_base;
955         /* FIXME stop DMA, IRQs, timers, ... */
957         /* disable all IRQs */
958         musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
959         musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
960         musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
961         musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
963         del_timer(&musb_idle_timer);
965         if (is_dma_capable() && !dma_off) {
966                 printk(KERN_WARNING "%s %s: dma still active\n",
967                                 __FILE__, __func__);
968                 dma_off = 1;
969         }
972 /*
973  * Sets up TUSB6010 CPU interface specific signals and registers
974  * Note: Settings optimized for OMAP24xx
975  */
976 static void tusb_setup_cpu_interface(struct musb *musb)
978         void __iomem    *tbase = musb->ctrl_base;
980         /*
981          * Disable GPIO[5:0] pullups (used as output DMA requests)
982          * Don't disable GPIO[7:6] as they are needed for wake-up.
983          */
984         musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
986         /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
987         musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
989         /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
990         musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
992         /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
993          * de-assertion time 2 system clocks p 62 */
994         musb_writel(tbase, TUSB_DMA_REQ_CONF,
995                 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
996                 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
997                 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
999         /* Set 0 wait count for synchronous burst access */
1000         musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1003 static int tusb_musb_start(struct musb *musb)
1005         void __iomem    *tbase = musb->ctrl_base;
1006         int             ret = 0;
1007         unsigned long   flags;
1008         u32             reg;
1010         if (musb->board_set_power)
1011                 ret = musb->board_set_power(1);
1012         if (ret != 0) {
1013                 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1014                 return ret;
1015         }
1017         spin_lock_irqsave(&musb->lock, flags);
1019         if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1020                 TUSB_PROD_TEST_RESET_VAL) {
1021                 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1022                 goto err;
1023         }
1025         ret = tusb_print_revision(musb);
1026         if (ret < 2) {
1027                 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1028                                 ret);
1029                 goto err;
1030         }
1032         /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1033          * NOR FLASH interface is used */
1034         musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1036         /* Select PHY free running 60MHz as a system clock */
1037         tusb_set_clock_source(musb, 1);
1039         /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1040          * power saving, enable VBus detect and session end comparators,
1041          * enable IDpullup, enable VBus charging */
1042         musb_writel(tbase, TUSB_PRCM_MNGMT,
1043                 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1044                 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1045                 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1046                 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1047                 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1048         tusb_setup_cpu_interface(musb);
1050         /* simplify:  always sense/pullup ID pins, as if in OTG mode */
1051         reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1052         reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1053         musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1055         reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1056         reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1057         musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
1059         spin_unlock_irqrestore(&musb->lock, flags);
1061         return 0;
1063 err:
1064         spin_unlock_irqrestore(&musb->lock, flags);
1066         if (musb->board_set_power)
1067                 musb->board_set_power(0);
1069         return -ENODEV;
1072 static int tusb_musb_init(struct musb *musb)
1074         struct platform_device  *pdev;
1075         struct resource         *mem;
1076         void __iomem            *sync = NULL;
1077         int                     ret;
1079         usb_nop_xceiv_register();
1080         musb->xceiv = otg_get_transceiver();
1081         if (!musb->xceiv)
1082                 return -ENODEV;
1084         pdev = to_platform_device(musb->controller);
1086         /* dma address for async dma */
1087         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1088         musb->async = mem->start;
1090         /* dma address for sync dma */
1091         mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1092         if (!mem) {
1093                 pr_debug("no sync dma resource?\n");
1094                 ret = -ENODEV;
1095                 goto done;
1096         }
1097         musb->sync = mem->start;
1099         sync = ioremap(mem->start, resource_size(mem));
1100         if (!sync) {
1101                 pr_debug("ioremap for sync failed\n");
1102                 ret = -ENOMEM;
1103                 goto done;
1104         }
1105         musb->sync_va = sync;
1107         /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1108          * FIFOs at 0x600, TUSB at 0x800
1109          */
1110         musb->mregs += TUSB_BASE_OFFSET;
1112         ret = tusb_musb_start(musb);
1113         if (ret) {
1114                 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1115                                 ret);
1116                 goto done;
1117         }
1118         musb->isr = tusb_musb_interrupt;
1120         if (is_peripheral_enabled(musb)) {
1121                 musb->xceiv->set_power = tusb_draw_power;
1122                 the_musb = musb;
1123         }
1125         setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1127 done:
1128         if (ret < 0) {
1129                 if (sync)
1130                         iounmap(sync);
1132                 otg_put_transceiver(musb->xceiv);
1133                 usb_nop_xceiv_unregister();
1134         }
1135         return ret;
1138 static int tusb_musb_exit(struct musb *musb)
1140         del_timer_sync(&musb_idle_timer);
1141         the_musb = NULL;
1143         if (musb->board_set_power)
1144                 musb->board_set_power(0);
1146         iounmap(musb->sync_va);
1148         otg_put_transceiver(musb->xceiv);
1149         usb_nop_xceiv_unregister();
1150         return 0;
1153 static const struct musb_platform_ops tusb_ops = {
1154         .fifo_mode      = 4,
1155         .flags          = MUSB_GLUE_TUSB_STYLE |
1156                                 MUSB_GLUE_EP_ADDR_INDEXED_MAPPING,
1157         .init           = tusb_musb_init,
1158         .exit           = tusb_musb_exit,
1160         .enable         = tusb_musb_enable,
1161         .disable        = tusb_musb_disable,
1163         .set_mode       = tusb_musb_set_mode,
1164         .try_idle       = tusb_musb_try_idle,
1166         .get_hw_revision        = tusb_get_revision,
1168         .vbus_status    = tusb_musb_vbus_status,
1169         .set_vbus       = tusb_musb_set_vbus,
1170         .read_fifo      = tusb_musb_read_fifo,
1171         .write_fifo     = tusb_musb_write_fifo,
1172 };
1174 static u64 tusb_dmamask = DMA_BIT_MASK(32);
1176 static int __init tusb_probe(struct platform_device *pdev)
1178         struct musb_hdrc_platform_data  *pdata = pdev->dev.platform_data;
1179         struct platform_device          *musb;
1180         struct tusb6010_glue            *glue;
1182         int                             ret = -ENOMEM;
1184         glue = kzalloc(sizeof(*glue), GFP_KERNEL);
1185         if (!glue) {
1186                 dev_err(&pdev->dev, "failed to allocate glue context\n");
1187                 goto err0;
1188         }
1190         musb = platform_device_alloc("musb-hdrc", -1);
1191         if (!musb) {
1192                 dev_err(&pdev->dev, "failed to allocate musb device\n");
1193                 goto err1;
1194         }
1196         musb->dev.parent                = &pdev->dev;
1197         musb->dev.dma_mask              = &tusb_dmamask;
1198         musb->dev.coherent_dma_mask     = tusb_dmamask;
1200         glue->dev                       = &pdev->dev;
1201         glue->musb                      = musb;
1203         pdata->platform_ops             = &tusb_ops;
1205         platform_set_drvdata(pdev, glue);
1207         ret = platform_device_add_resources(musb, pdev->resource,
1208                         pdev->num_resources);
1209         if (ret) {
1210                 dev_err(&pdev->dev, "failed to add resources\n");
1211                 goto err2;
1212         }
1214         ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
1215         if (ret) {
1216                 dev_err(&pdev->dev, "failed to add platform_data\n");
1217                 goto err2;
1218         }
1220         ret = platform_device_add(musb);
1221         if (ret) {
1222                 dev_err(&pdev->dev, "failed to register musb device\n");
1223                 goto err1;
1224         }
1226         return 0;
1228 err2:
1229         platform_device_put(musb);
1231 err1:
1232         kfree(glue);
1234 err0:
1235         return ret;
1238 static int __exit tusb_remove(struct platform_device *pdev)
1240         struct tusb6010_glue            *glue = platform_get_drvdata(pdev);
1242         platform_device_del(glue->musb);
1243         platform_device_put(glue->musb);
1244         kfree(glue);
1246         return 0;
1249 static struct platform_driver tusb_driver = {
1250         .remove         = __exit_p(tusb_remove),
1251         .driver         = {
1252                 .name   = "musb-tusb",
1253         },
1254 };
1256 MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
1257 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1258 MODULE_LICENSE("GPL v2");
1260 static int __init tusb_init(void)
1262         return platform_driver_probe(&tusb_driver, tusb_probe);
1264 subsys_initcall(tusb_init);
1266 static void __exit tusb_exit(void)
1268         platform_driver_unregister(&tusb_driver);
1270 module_exit(tusb_exit);