1 /*
2 * Copyright (C) 2008-2009 MontaVista Software Inc.
3 * Copyright (C) 2008-2009 Texas Instruments Inc
4 *
5 * Based on the LCD driver for TI Avalanche processors written by
6 * Ajay Singh and Shalom Hai.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option)any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/fb.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/interrupt.h>
30 #include <linux/clk.h>
31 #include <linux/cpufreq.h>
32 #include <linux/console.h>
33 #include <linux/slab.h>
34 #include <video/da8xx-fb.h>
36 #define DRIVER_NAME "da8xx_lcdc"
38 #define LCD_VERSION_1 1
39 #define LCD_VERSION_2 2
41 /* LCD Status Register */
42 #define LCD_END_OF_FRAME1 BIT(9)
43 #define LCD_END_OF_FRAME0 BIT(8)
44 #define LCD_PL_LOAD_DONE BIT(6)
45 #define LCD_FIFO_UNDERFLOW BIT(5)
46 #define LCD_SYNC_LOST BIT(2)
48 /* LCD DMA Control Register */
49 #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
50 #define LCD_DMA_BURST_1 0x0
51 #define LCD_DMA_BURST_2 0x1
52 #define LCD_DMA_BURST_4 0x2
53 #define LCD_DMA_BURST_8 0x3
54 #define LCD_DMA_BURST_16 0x4
55 #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)
56 #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8)
57 #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9)
58 #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
60 /* LCD Control Register */
61 #define LCD_CLK_DIVISOR(x) ((x) << 8)
62 #define LCD_RASTER_MODE 0x01
64 /* LCD Raster Control Register */
65 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
66 #define PALETTE_AND_DATA 0x00
67 #define PALETTE_ONLY 0x01
68 #define DATA_ONLY 0x02
70 #define LCD_MONO_8BIT_MODE BIT(9)
71 #define LCD_RASTER_ORDER BIT(8)
72 #define LCD_TFT_MODE BIT(7)
73 #define LCD_V1_UNDERFLOW_INT_ENA BIT(6)
74 #define LCD_V2_UNDERFLOW_INT_ENA BIT(5)
75 #define LCD_V1_PL_INT_ENA BIT(4)
76 #define LCD_V2_PL_INT_ENA BIT(6)
77 #define LCD_MONOCHROME_MODE BIT(1)
78 #define LCD_RASTER_ENABLE BIT(0)
79 #define LCD_TFT_ALT_ENABLE BIT(23)
80 #define LCD_STN_565_ENABLE BIT(24)
81 #define LCD_V2_DMA_CLK_EN BIT(2)
82 #define LCD_V2_LIDD_CLK_EN BIT(1)
83 #define LCD_V2_CORE_CLK_EN BIT(0)
84 #define LCD_V2_LPP_B10 26
85 #define LCD_V2_TFT_24BPP_MODE BIT(25)
86 #define LCD_V2_TFT_24BPP_UNPACK BIT(26)
88 /* LCD Raster Timing 2 Register */
89 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
90 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
91 #define LCD_SYNC_CTRL BIT(25)
92 #define LCD_SYNC_EDGE BIT(24)
93 #define LCD_INVERT_PIXEL_CLOCK BIT(22)
94 #define LCD_INVERT_LINE_CLOCK BIT(21)
95 #define LCD_INVERT_FRAME_CLOCK BIT(20)
97 /* LCD Block */
98 #define LCD_PID_REG 0x0
99 #define LCD_CTRL_REG 0x4
100 #define LCD_STAT_REG 0x8
101 #define LCD_RASTER_CTRL_REG 0x28
102 #define LCD_RASTER_TIMING_0_REG 0x2C
103 #define LCD_RASTER_TIMING_1_REG 0x30
104 #define LCD_RASTER_TIMING_2_REG 0x34
105 #define LCD_DMA_CTRL_REG 0x40
106 #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44
107 #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
108 #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C
109 #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50
111 /* Interrupt Registers available only in Version 2 */
112 #define LCD_RAW_STAT_REG 0x58
113 #define LCD_MASKED_STAT_REG 0x5c
114 #define LCD_INT_ENABLE_SET_REG 0x60
115 #define LCD_INT_ENABLE_CLR_REG 0x64
116 #define LCD_END_OF_INT_IND_REG 0x68
118 /* Clock registers available only on Version 2 */
119 #define LCD_CLK_ENABLE_REG 0x6c
120 #define LCD_CLK_RESET_REG 0x70
121 #define LCD_CLK_MAIN_RESET BIT(3)
123 #define LCD_NUM_BUFFERS 2
125 #define WSI_TIMEOUT 50
126 #define PALETTE_SIZE 256
127 #define LEFT_MARGIN 64
128 #define RIGHT_MARGIN 64
129 #define UPPER_MARGIN 32
130 #define LOWER_MARGIN 32
132 static resource_size_t da8xx_fb_reg_base;
133 static struct resource *lcdc_regs;
134 static unsigned int lcd_revision;
135 static irq_handler_t lcdc_irq_handler;
137 static inline unsigned int lcdc_read(unsigned int addr)
138 {
139 return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
140 }
142 static inline void lcdc_write(unsigned int val, unsigned int addr)
143 {
144 __raw_writel(val, da8xx_fb_reg_base + (addr));
145 }
147 struct da8xx_fb_par {
148 resource_size_t p_palette_base;
149 unsigned char *v_palette_base;
150 dma_addr_t vram_phys;
151 unsigned long vram_size;
152 void *vram_virt;
153 unsigned int dma_start;
154 unsigned int dma_end;
155 struct clk *lcdc_clk;
156 int irq;
157 unsigned long pseudo_palette[32];
158 unsigned int palette_sz;
159 unsigned int pxl_clk;
160 int blank;
161 wait_queue_head_t vsync_wait;
162 int vsync_flag;
163 int vsync_timeout;
164 #ifdef CONFIG_CPU_FREQ
165 struct notifier_block freq_transition;
166 #endif
167 void (*panel_power_ctrl)(int);
168 };
170 /* Variable Screen Information */
171 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
172 .xoffset = 0,
173 .yoffset = 0,
174 .transp = {0, 0, 0},
175 .nonstd = 0,
176 .activate = 0,
177 .height = -1,
178 .width = -1,
179 .pixclock = 46666, /* 46us - AUO display */
180 .accel_flags = 0,
181 .left_margin = LEFT_MARGIN,
182 .right_margin = RIGHT_MARGIN,
183 .upper_margin = UPPER_MARGIN,
184 .lower_margin = LOWER_MARGIN,
185 .sync = 0,
186 .vmode = FB_VMODE_NONINTERLACED
187 };
189 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
190 .id = "DA8xx FB Drv",
191 .type = FB_TYPE_PACKED_PIXELS,
192 .type_aux = 0,
193 .visual = FB_VISUAL_PSEUDOCOLOR,
194 .xpanstep = 0,
195 .ypanstep = 1,
196 .ywrapstep = 0,
197 .accel = FB_ACCEL_NONE
198 };
200 struct da8xx_panel {
201 const char name[25]; /* Full name <vendor>_<model> */
202 unsigned short width;
203 unsigned short height;
204 int hfp; /* Horizontal front porch */
205 int hbp; /* Horizontal back porch */
206 int hsw; /* Horizontal Sync Pulse Width */
207 int vfp; /* Vertical front porch */
208 int vbp; /* Vertical back porch */
209 int vsw; /* Vertical Sync Pulse Width */
210 unsigned int pxl_clk; /* Pixel clock */
211 unsigned char invert_pxl_clk; /* Invert Pixel clock */
212 };
214 static struct da8xx_panel known_lcd_panels[] = {
215 /* Sharp LCD035Q3DG01 */
216 [0] = {
217 .name = "Sharp_LCD035Q3DG01",
218 .width = 320,
219 .height = 240,
220 .hfp = 8,
221 .hbp = 6,
222 .hsw = 0,
223 .vfp = 2,
224 .vbp = 2,
225 .vsw = 0,
226 .pxl_clk = 4608000,
227 .invert_pxl_clk = 1,
228 },
229 /* Sharp LK043T1DG01 */
230 [1] = {
231 .name = "Sharp_LK043T1DG01",
232 .width = 480,
233 .height = 272,
234 .hfp = 2,
235 .hbp = 2,
236 .hsw = 41,
237 .vfp = 2,
238 .vbp = 2,
239 .vsw = 10,
240 .pxl_clk = 7833600,
241 .invert_pxl_clk = 0,
242 },
243 };
245 /* Enable the Raster Engine of the LCD Controller */
246 static inline void lcd_enable_raster(void)
247 {
248 u32 reg;
250 /* Bring LCDC out of reset */
251 if (lcd_revision == LCD_VERSION_2)
252 lcdc_write(0, LCD_CLK_RESET_REG);
254 reg = lcdc_read(LCD_RASTER_CTRL_REG);
255 if (!(reg & LCD_RASTER_ENABLE))
256 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
257 }
259 /* Disable the Raster Engine of the LCD Controller */
260 static inline void lcd_disable_raster(void)
261 {
262 u32 reg;
264 reg = lcdc_read(LCD_RASTER_CTRL_REG);
265 if (reg & LCD_RASTER_ENABLE)
266 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
268 if (lcd_revision == LCD_VERSION_2)
269 /* Write 1 to reset LCDC */
270 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
271 }
273 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
274 {
275 u32 start;
276 u32 end;
277 u32 reg_ras;
278 u32 reg_dma;
279 u32 reg_int;
281 /* init reg to clear PLM (loading mode) fields */
282 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
283 reg_ras &= ~(3 << 20);
285 reg_dma = lcdc_read(LCD_DMA_CTRL_REG);
287 if (load_mode == LOAD_DATA) {
288 start = par->dma_start;
289 end = par->dma_end;
291 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
292 if (lcd_revision == LCD_VERSION_1) {
293 reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
294 } else {
295 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
296 LCD_V2_END_OF_FRAME0_INT_ENA |
297 LCD_V2_END_OF_FRAME1_INT_ENA;
298 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
299 }
300 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
302 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
303 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
304 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
305 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
306 } else if (load_mode == LOAD_PALETTE) {
307 start = par->p_palette_base;
308 end = start + par->palette_sz - 1;
310 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
312 if (lcd_revision == LCD_VERSION_1) {
313 reg_ras |= LCD_V1_PL_INT_ENA;
314 } else {
315 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
316 LCD_V2_PL_INT_ENA;
317 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
318 }
320 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
321 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
322 }
324 lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
325 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
327 /*
328 * The Raster enable bit must be set after all other control fields are
329 * set.
330 */
331 lcd_enable_raster();
332 }
334 /* Configure the Burst Size of DMA */
335 static int lcd_cfg_dma(int burst_size)
336 {
337 u32 reg;
339 reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
340 switch (burst_size) {
341 case 1:
342 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
343 break;
344 case 2:
345 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
346 break;
347 case 4:
348 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
349 break;
350 case 8:
351 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
352 break;
353 case 16:
354 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
355 break;
356 default:
357 return -EINVAL;
358 }
359 lcdc_write(reg, LCD_DMA_CTRL_REG);
361 return 0;
362 }
364 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
365 {
366 u32 reg;
368 /* Set the AC Bias Period and Number of Transisitons per Interrupt */
369 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
370 reg |= LCD_AC_BIAS_FREQUENCY(period) |
371 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
372 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
373 }
375 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
376 int front_porch)
377 {
378 u32 reg;
380 reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
381 reg |= ((back_porch & 0xff) << 24)
382 | ((front_porch & 0xff) << 16)
383 | ((pulse_width & 0x3f) << 10);
384 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
385 }
387 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
388 int front_porch)
389 {
390 u32 reg;
392 reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
393 reg |= ((back_porch & 0xff) << 24)
394 | ((front_porch & 0xff) << 16)
395 | ((pulse_width & 0x3f) << 10);
396 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
397 }
399 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
400 {
401 u32 reg;
402 u32 reg_int;
404 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
405 LCD_MONO_8BIT_MODE |
406 LCD_MONOCHROME_MODE);
408 switch (cfg->p_disp_panel->panel_shade) {
409 case MONOCHROME:
410 reg |= LCD_MONOCHROME_MODE;
411 if (cfg->mono_8bit_mode)
412 reg |= LCD_MONO_8BIT_MODE;
413 break;
414 case COLOR_ACTIVE:
415 reg |= LCD_TFT_MODE;
416 if (cfg->tft_alt_mode)
417 reg |= LCD_TFT_ALT_ENABLE;
418 break;
420 case COLOR_PASSIVE:
421 if (cfg->stn_565_mode)
422 reg |= LCD_STN_565_ENABLE;
423 break;
425 default:
426 return -EINVAL;
427 }
429 /* enable additional interrupts here */
430 if (lcd_revision == LCD_VERSION_1) {
431 reg |= LCD_V1_UNDERFLOW_INT_ENA;
432 } else {
433 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
434 LCD_V2_UNDERFLOW_INT_ENA;
435 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
436 }
438 lcdc_write(reg, LCD_RASTER_CTRL_REG);
440 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
442 if (cfg->sync_ctrl)
443 reg |= LCD_SYNC_CTRL;
444 else
445 reg &= ~LCD_SYNC_CTRL;
447 if (cfg->sync_edge)
448 reg |= LCD_SYNC_EDGE;
449 else
450 reg &= ~LCD_SYNC_EDGE;
452 if (cfg->invert_line_clock)
453 reg |= LCD_INVERT_LINE_CLOCK;
454 else
455 reg &= ~LCD_INVERT_LINE_CLOCK;
457 if (cfg->invert_frm_clock)
458 reg |= LCD_INVERT_FRAME_CLOCK;
459 else
460 reg &= ~LCD_INVERT_FRAME_CLOCK;
462 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
464 return 0;
465 }
467 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
468 u32 bpp, u32 raster_order)
469 {
470 u32 reg;
472 /* Set the Panel Width */
473 /* Pixels per line = (PPL + 1)*16 */
474 if (lcd_revision == LCD_VERSION_1) {
475 /*
476 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
477 * pixels.
478 */
479 width &= 0x3f0;
480 } else {
481 /*
482 * 0x7F in bits 4..10 gives max horizontal resolution = 2048
483 * pixels.
484 */
485 width &= 0x7f0;
486 }
488 reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
489 reg &= 0xfffffc00;
490 if (lcd_revision == LCD_VERSION_1) {
491 reg |= ((width >> 4) - 1) << 4;
492 } else {
493 width = (width >> 4) - 1;
494 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
495 }
496 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
498 /* Set the Panel Height */
499 /* Set bits 9:0 of Lines Per Pixel */
500 reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
501 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
502 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
504 /* Set bit 10 of Lines Per Pixel */
505 if (lcd_revision == LCD_VERSION_2) {
506 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
507 reg |= ((height - 1) & 0x400) << 16;
508 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
509 }
511 /* Set the Raster Order of the Frame Buffer */
512 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
513 if (raster_order)
514 reg |= LCD_RASTER_ORDER;
516 if (bpp == 24)
517 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
518 else if (bpp == 32)
519 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
520 | LCD_V2_TFT_24BPP_UNPACK);
522 lcdc_write(reg, LCD_RASTER_CTRL_REG);
524 switch (bpp) {
525 case 1:
526 case 2:
527 case 4:
528 case 16:
529 case 24:
530 case 32:
531 par->palette_sz = 16 * 2;
532 break;
534 case 8:
535 par->palette_sz = 256 * 2;
536 break;
538 default:
539 return -EINVAL;
540 }
542 return 0;
543 }
545 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
546 unsigned blue, unsigned transp,
547 struct fb_info *info)
548 {
549 struct da8xx_fb_par *par = info->par;
550 unsigned short *palette = (unsigned short *) par->v_palette_base;
551 u_short pal;
552 int update_hw = 0;
554 if (regno > 255)
555 return 1;
557 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
558 return 1;
560 if (info->var.bits_per_pixel == 8) {
561 red >>= 4;
562 green >>= 8;
563 blue >>= 12;
565 pal = (red & 0x0f00);
566 pal |= (green & 0x00f0);
567 pal |= (blue & 0x000f);
569 if (palette[regno] != pal) {
570 update_hw = 1;
571 palette[regno] = pal;
572 }
573 } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
574 red >>= (16 - info->var.red.length);
575 red <<= info->var.red.offset;
577 green >>= (16 - info->var.green.length);
578 green <<= info->var.green.offset;
580 blue >>= (16 - info->var.blue.length);
581 blue <<= info->var.blue.offset;
583 par->pseudo_palette[regno] = red | green | blue;
585 if (palette[0] != 0x4000) {
586 update_hw = 1;
587 palette[0] = 0x4000;
588 }
589 } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
590 ((info->var.bits_per_pixel == 24) && regno < 24)) {
591 red >>= (24 - info->var.red.length);
592 red <<= info->var.red.offset;
594 green >>= (24 - info->var.green.length);
595 green <<= info->var.green.offset;
597 blue >>= (24 - info->var.blue.length);
598 blue <<= info->var.blue.offset;
600 par->pseudo_palette[regno] = red | green | blue;
602 if (palette[0] != 0x4000) {
603 update_hw = 1;
604 palette[0] = 0x4000;
605 }
606 }
608 /* Update the palette in the h/w as needed. */
609 if (update_hw)
610 lcd_blit(LOAD_PALETTE, par);
612 return 0;
613 }
615 static void lcd_reset(struct da8xx_fb_par *par)
616 {
617 /* Disable the Raster if previously Enabled */
618 lcd_disable_raster();
620 /* DMA has to be disabled */
621 lcdc_write(0, LCD_DMA_CTRL_REG);
622 lcdc_write(0, LCD_RASTER_CTRL_REG);
624 if (lcd_revision == LCD_VERSION_2) {
625 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
626 /* Write 1 to reset */
627 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
628 lcdc_write(0, LCD_CLK_RESET_REG);
629 }
630 }
632 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
633 {
634 unsigned int lcd_clk, div;
636 lcd_clk = clk_get_rate(par->lcdc_clk);
637 div = lcd_clk / par->pxl_clk;
639 /* Configure the LCD clock divisor. */
640 lcdc_write(LCD_CLK_DIVISOR(div) |
641 (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
643 if (lcd_revision == LCD_VERSION_2)
644 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
645 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
647 }
649 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
650 struct da8xx_panel *panel)
651 {
652 u32 bpp;
653 int ret = 0;
655 lcd_reset(par);
657 /* Calculate the divider */
658 lcd_calc_clk_divider(par);
660 if (panel->invert_pxl_clk)
661 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
662 LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
663 else
664 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
665 ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
667 /* Configure the DMA burst size. */
668 ret = lcd_cfg_dma(cfg->dma_burst_sz);
669 if (ret < 0)
670 return ret;
672 /* Configure the AC bias properties. */
673 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
675 /* Configure the vertical and horizontal sync properties. */
676 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
677 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
679 /* Configure for disply */
680 ret = lcd_cfg_display(cfg);
681 if (ret < 0)
682 return ret;
684 if (QVGA != cfg->p_disp_panel->panel_type)
685 return -EINVAL;
687 if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
688 cfg->bpp >= cfg->p_disp_panel->min_bpp)
689 bpp = cfg->bpp;
690 else
691 bpp = cfg->p_disp_panel->max_bpp;
692 if (bpp == 12)
693 bpp = 16;
694 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
695 (unsigned int)panel->height, bpp,
696 cfg->raster_order);
697 if (ret < 0)
698 return ret;
700 /* Configure FDD */
701 lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
702 (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
704 return 0;
705 }
707 /* IRQ handler for version 2 of LCDC */
708 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
709 {
710 struct da8xx_fb_par *par = arg;
711 u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
712 u32 reg_int;
714 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
715 lcd_disable_raster();
716 lcdc_write(stat, LCD_MASKED_STAT_REG);
717 lcd_enable_raster();
718 } else if (stat & LCD_PL_LOAD_DONE) {
719 /*
720 * Must disable raster before changing state of any control bit.
721 * And also must be disabled before clearing the PL loading
722 * interrupt via the following write to the status register. If
723 * this is done after then one gets multiple PL done interrupts.
724 */
725 lcd_disable_raster();
727 lcdc_write(stat, LCD_MASKED_STAT_REG);
729 /* Disable PL completion inerrupt */
730 reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |
731 (LCD_V2_PL_INT_ENA);
732 lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);
734 /* Setup and start data loading mode */
735 lcd_blit(LOAD_DATA, par);
736 } else {
737 lcdc_write(stat, LCD_MASKED_STAT_REG);
739 if (stat & LCD_END_OF_FRAME0) {
740 lcdc_write(par->dma_start,
741 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
742 lcdc_write(par->dma_end,
743 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
744 par->vsync_flag = 1;
745 wake_up_interruptible(&par->vsync_wait);
746 }
748 if (stat & LCD_END_OF_FRAME1) {
749 lcdc_write(par->dma_start,
750 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
751 lcdc_write(par->dma_end,
752 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
753 par->vsync_flag = 1;
754 wake_up_interruptible(&par->vsync_wait);
755 }
756 }
758 lcdc_write(0, LCD_END_OF_INT_IND_REG);
759 return IRQ_HANDLED;
760 }
762 /* IRQ handler for version 1 LCDC */
763 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
764 {
765 struct da8xx_fb_par *par = arg;
766 u32 stat = lcdc_read(LCD_STAT_REG);
767 u32 reg_ras;
769 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
770 lcd_disable_raster();
771 lcdc_write(stat, LCD_STAT_REG);
772 lcd_enable_raster();
773 } else if (stat & LCD_PL_LOAD_DONE) {
774 /*
775 * Must disable raster before changing state of any control bit.
776 * And also must be disabled before clearing the PL loading
777 * interrupt via the following write to the status register. If
778 * this is done after then one gets multiple PL done interrupts.
779 */
780 lcd_disable_raster();
782 lcdc_write(stat, LCD_STAT_REG);
784 /* Disable PL completion inerrupt */
785 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
786 reg_ras &= ~LCD_V1_PL_INT_ENA;
787 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
789 /* Setup and start data loading mode */
790 lcd_blit(LOAD_DATA, par);
791 } else {
792 lcdc_write(stat, LCD_STAT_REG);
794 if (stat & LCD_END_OF_FRAME0) {
795 lcdc_write(par->dma_start,
796 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
797 lcdc_write(par->dma_end,
798 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
799 par->vsync_flag = 1;
800 wake_up_interruptible(&par->vsync_wait);
801 }
803 if (stat & LCD_END_OF_FRAME1) {
804 lcdc_write(par->dma_start,
805 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
806 lcdc_write(par->dma_end,
807 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
808 par->vsync_flag = 1;
809 wake_up_interruptible(&par->vsync_wait);
810 }
811 }
813 return IRQ_HANDLED;
814 }
816 static int fb_check_var(struct fb_var_screeninfo *var,
817 struct fb_info *info)
818 {
819 int err = 0;
821 switch (var->bits_per_pixel) {
822 case 1:
823 case 8:
824 var->red.offset = 0;
825 var->red.length = 8;
826 var->green.offset = 0;
827 var->green.length = 8;
828 var->blue.offset = 0;
829 var->blue.length = 8;
830 var->transp.offset = 0;
831 var->transp.length = 0;
832 break;
833 case 4:
834 var->red.offset = 0;
835 var->red.length = 4;
836 var->green.offset = 0;
837 var->green.length = 4;
838 var->blue.offset = 0;
839 var->blue.length = 4;
840 var->transp.offset = 0;
841 var->transp.length = 0;
842 break;
843 case 16: /* RGB 565 */
844 var->red.offset = 11;
845 var->red.length = 5;
846 var->green.offset = 5;
847 var->green.length = 6;
848 var->blue.offset = 0;
849 var->blue.length = 5;
850 var->transp.offset = 0;
851 var->transp.length = 0;
852 break;
853 case 24:
854 var->red.offset = 16;
855 var->red.length = 8;
856 var->green.offset = 8;
857 var->green.length = 8;
858 var->blue.offset = 0;
859 var->blue.length = 8;
860 break;
861 case 32:
862 var->transp.offset = 24;
863 var->transp.length = 8;
864 var->red.offset = 16;
865 var->red.length = 8;
866 var->green.offset = 8;
867 var->green.length = 8;
868 var->blue.offset = 0;
869 var->blue.length = 8;
870 break;
871 default:
872 err = -EINVAL;
873 }
875 var->red.msb_right = 0;
876 var->green.msb_right = 0;
877 var->blue.msb_right = 0;
878 var->transp.msb_right = 0;
879 return err;
880 }
882 #ifdef CONFIG_CPU_FREQ
883 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
884 unsigned long val, void *data)
885 {
886 struct da8xx_fb_par *par;
888 par = container_of(nb, struct da8xx_fb_par, freq_transition);
889 if (val == CPUFREQ_PRECHANGE) {
890 lcd_disable_raster();
891 } else if (val == CPUFREQ_POSTCHANGE) {
892 lcd_calc_clk_divider(par);
893 lcd_enable_raster();
894 }
896 return 0;
897 }
899 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
900 {
901 par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
903 return cpufreq_register_notifier(&par->freq_transition,
904 CPUFREQ_TRANSITION_NOTIFIER);
905 }
907 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
908 {
909 cpufreq_unregister_notifier(&par->freq_transition,
910 CPUFREQ_TRANSITION_NOTIFIER);
911 }
912 #endif
914 static int __devexit fb_remove(struct platform_device *dev)
915 {
916 struct fb_info *info = dev_get_drvdata(&dev->dev);
918 if (info) {
919 struct da8xx_fb_par *par = info->par;
921 #ifdef CONFIG_CPU_FREQ
922 lcd_da8xx_cpufreq_deregister(par);
923 #endif
924 if (par->panel_power_ctrl)
925 par->panel_power_ctrl(0);
927 lcd_disable_raster();
928 lcdc_write(0, LCD_RASTER_CTRL_REG);
930 /* disable DMA */
931 lcdc_write(0, LCD_DMA_CTRL_REG);
933 unregister_framebuffer(info);
934 fb_dealloc_cmap(&info->cmap);
935 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
936 par->p_palette_base);
937 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
938 par->vram_phys);
939 free_irq(par->irq, par);
940 clk_disable(par->lcdc_clk);
941 clk_put(par->lcdc_clk);
942 framebuffer_release(info);
943 iounmap((void __iomem *)da8xx_fb_reg_base);
944 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
946 }
947 return 0;
948 }
950 /*
951 * Function to wait for vertical sync which for this LCD peripheral
952 * translates into waiting for the current raster frame to complete.
953 */
954 static int fb_wait_for_vsync(struct fb_info *info)
955 {
956 struct da8xx_fb_par *par = info->par;
957 int ret;
959 /*
960 * Set flag to 0 and wait for isr to set to 1. It would seem there is a
961 * race condition here where the ISR could have occurred just before or
962 * just after this set. But since we are just coarsely waiting for
963 * a frame to complete then that's OK. i.e. if the frame completed
964 * just before this code executed then we have to wait another full
965 * frame time but there is no way to avoid such a situation. On the
966 * other hand if the frame completed just after then we don't need
967 * to wait long at all. Either way we are guaranteed to return to the
968 * user immediately after a frame completion which is all that is
969 * required.
970 */
971 par->vsync_flag = 0;
972 ret = wait_event_interruptible_timeout(par->vsync_wait,
973 par->vsync_flag != 0,
974 par->vsync_timeout);
975 if (ret < 0)
976 return ret;
977 if (ret == 0)
978 return -ETIMEDOUT;
980 return 0;
981 }
983 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
984 unsigned long arg)
985 {
986 struct lcd_sync_arg sync_arg;
988 switch (cmd) {
989 case FBIOGET_CONTRAST:
990 case FBIOPUT_CONTRAST:
991 case FBIGET_BRIGHTNESS:
992 case FBIPUT_BRIGHTNESS:
993 case FBIGET_COLOR:
994 case FBIPUT_COLOR:
995 return -ENOTTY;
996 case FBIPUT_HSYNC:
997 if (copy_from_user(&sync_arg, (char *)arg,
998 sizeof(struct lcd_sync_arg)))
999 return -EFAULT;
1000 lcd_cfg_horizontal_sync(sync_arg.back_porch,
1001 sync_arg.pulse_width,
1002 sync_arg.front_porch);
1003 break;
1004 case FBIPUT_VSYNC:
1005 if (copy_from_user(&sync_arg, (char *)arg,
1006 sizeof(struct lcd_sync_arg)))
1007 return -EFAULT;
1008 lcd_cfg_vertical_sync(sync_arg.back_porch,
1009 sync_arg.pulse_width,
1010 sync_arg.front_porch);
1011 break;
1012 case FBIO_WAITFORVSYNC:
1013 return fb_wait_for_vsync(info);
1014 default:
1015 return -EINVAL;
1016 }
1017 return 0;
1018 }
1020 static int cfb_blank(int blank, struct fb_info *info)
1021 {
1022 struct da8xx_fb_par *par = info->par;
1023 int ret = 0;
1025 if (par->blank == blank)
1026 return 0;
1028 par->blank = blank;
1029 switch (blank) {
1030 case FB_BLANK_UNBLANK:
1031 if (par->panel_power_ctrl)
1032 par->panel_power_ctrl(1);
1034 lcd_enable_raster();
1035 break;
1036 case FB_BLANK_POWERDOWN:
1037 if (par->panel_power_ctrl)
1038 par->panel_power_ctrl(0);
1040 lcd_disable_raster();
1041 break;
1042 default:
1043 ret = -EINVAL;
1044 }
1046 return ret;
1047 }
1049 /*
1050 * Set new x,y offsets in the virtual display for the visible area and switch
1051 * to the new mode.
1052 */
1053 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1054 struct fb_info *fbi)
1055 {
1056 int ret = 0;
1057 struct fb_var_screeninfo new_var;
1058 struct da8xx_fb_par *par = fbi->par;
1059 struct fb_fix_screeninfo *fix = &fbi->fix;
1060 unsigned int end;
1061 unsigned int start;
1063 if (var->xoffset != fbi->var.xoffset ||
1064 var->yoffset != fbi->var.yoffset) {
1065 memcpy(&new_var, &fbi->var, sizeof(new_var));
1066 new_var.xoffset = var->xoffset;
1067 new_var.yoffset = var->yoffset;
1068 if (fb_check_var(&new_var, fbi))
1069 ret = -EINVAL;
1070 else {
1071 memcpy(&fbi->var, &new_var, sizeof(new_var));
1073 start = fix->smem_start +
1074 new_var.yoffset * fix->line_length +
1075 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1076 end = start + fbi->var.yres * fix->line_length - 1;
1077 par->dma_start = start;
1078 par->dma_end = end;
1079 }
1080 }
1082 return ret;
1083 }
1085 static struct fb_ops da8xx_fb_ops = {
1086 .owner = THIS_MODULE,
1087 .fb_check_var = fb_check_var,
1088 .fb_setcolreg = fb_setcolreg,
1089 .fb_pan_display = da8xx_pan_display,
1090 .fb_ioctl = fb_ioctl,
1091 .fb_fillrect = cfb_fillrect,
1092 .fb_copyarea = cfb_copyarea,
1093 .fb_imageblit = cfb_imageblit,
1094 .fb_blank = cfb_blank,
1095 };
1097 static int __devinit fb_probe(struct platform_device *device)
1098 {
1099 struct da8xx_lcdc_platform_data *fb_pdata =
1100 device->dev.platform_data;
1101 struct lcd_ctrl_config *lcd_cfg;
1102 struct da8xx_panel *lcdc_info;
1103 struct fb_info *da8xx_fb_info;
1104 struct clk *fb_clk = NULL;
1105 struct da8xx_fb_par *par;
1106 resource_size_t len;
1107 int ret, i;
1109 if (fb_pdata == NULL) {
1110 dev_err(&device->dev, "Can not get platform data\n");
1111 return -ENOENT;
1112 }
1114 lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1115 if (!lcdc_regs) {
1116 dev_err(&device->dev,
1117 "Can not get memory resource for LCD controller\n");
1118 return -ENOENT;
1119 }
1121 len = resource_size(lcdc_regs);
1123 lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
1124 if (!lcdc_regs)
1125 return -EBUSY;
1127 da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
1128 if (!da8xx_fb_reg_base) {
1129 ret = -EBUSY;
1130 goto err_request_mem;
1131 }
1133 fb_clk = clk_get(&device->dev, NULL);
1134 if (IS_ERR(fb_clk)) {
1135 dev_err(&device->dev, "Can not get device clock\n");
1136 ret = -ENODEV;
1137 goto err_ioremap;
1138 }
1139 ret = clk_enable(fb_clk);
1140 if (ret)
1141 goto err_clk_put;
1143 /* Determine LCD IP Version */
1144 switch (lcdc_read(LCD_PID_REG)) {
1145 case 0x4C100102:
1146 lcd_revision = LCD_VERSION_1;
1147 break;
1148 case 0x4F200800:
1149 lcd_revision = LCD_VERSION_2;
1150 break;
1151 default:
1152 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1153 "defaulting to LCD revision 1\n",
1154 lcdc_read(LCD_PID_REG));
1155 lcd_revision = LCD_VERSION_1;
1156 break;
1157 }
1159 for (i = 0, lcdc_info = known_lcd_panels;
1160 i < ARRAY_SIZE(known_lcd_panels);
1161 i++, lcdc_info++) {
1162 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1163 break;
1164 }
1166 if (i == ARRAY_SIZE(known_lcd_panels)) {
1167 dev_err(&device->dev, "GLCD: No valid panel found\n");
1168 ret = -ENODEV;
1169 goto err_clk_disable;
1170 } else
1171 dev_info(&device->dev, "GLCD: Found %s panel\n",
1172 fb_pdata->type);
1174 lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1176 da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1177 &device->dev);
1178 if (!da8xx_fb_info) {
1179 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1180 ret = -ENOMEM;
1181 goto err_clk_disable;
1182 }
1184 par = da8xx_fb_info->par;
1185 par->lcdc_clk = fb_clk;
1186 par->pxl_clk = lcdc_info->pxl_clk;
1187 if (fb_pdata->panel_power_ctrl) {
1188 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1189 par->panel_power_ctrl(1);
1190 }
1192 if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
1193 dev_err(&device->dev, "lcd_init failed\n");
1194 ret = -EFAULT;
1195 goto err_release_fb;
1196 }
1198 /* allocate frame buffer */
1199 par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
1200 par->vram_size = PAGE_ALIGN(par->vram_size/8);
1201 par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1203 par->vram_virt = dma_alloc_coherent(NULL,
1204 par->vram_size,
1205 (resource_size_t *) &par->vram_phys,
1206 GFP_KERNEL | GFP_DMA);
1207 if (!par->vram_virt) {
1208 dev_err(&device->dev,
1209 "GLCD: kmalloc for frame buffer failed\n");
1210 ret = -EINVAL;
1211 goto err_release_fb;
1212 }
1214 da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1215 da8xx_fb_fix.smem_start = par->vram_phys;
1216 da8xx_fb_fix.smem_len = par->vram_size;
1217 da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8;
1219 par->dma_start = par->vram_phys;
1220 par->dma_end = par->dma_start + lcdc_info->height *
1221 da8xx_fb_fix.line_length - 1;
1223 /* allocate palette buffer */
1224 par->v_palette_base = dma_alloc_coherent(NULL,
1225 PALETTE_SIZE,
1226 (resource_size_t *)
1227 &par->p_palette_base,
1228 GFP_KERNEL | GFP_DMA);
1229 if (!par->v_palette_base) {
1230 dev_err(&device->dev,
1231 "GLCD: kmalloc for palette buffer failed\n");
1232 ret = -EINVAL;
1233 goto err_release_fb_mem;
1234 }
1235 memset(par->v_palette_base, 0, PALETTE_SIZE);
1237 par->irq = platform_get_irq(device, 0);
1238 if (par->irq < 0) {
1239 ret = -ENOENT;
1240 goto err_release_pl_mem;
1241 }
1243 /* Initialize par */
1244 da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
1246 da8xx_fb_var.xres = lcdc_info->width;
1247 da8xx_fb_var.xres_virtual = lcdc_info->width;
1249 da8xx_fb_var.yres = lcdc_info->height;
1250 da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
1252 da8xx_fb_var.grayscale =
1253 lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
1254 da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1256 da8xx_fb_var.hsync_len = lcdc_info->hsw;
1257 da8xx_fb_var.vsync_len = lcdc_info->vsw;
1259 /* Initialize fbinfo */
1260 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1261 da8xx_fb_info->fix = da8xx_fb_fix;
1262 da8xx_fb_info->var = da8xx_fb_var;
1263 da8xx_fb_info->fbops = &da8xx_fb_ops;
1264 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1265 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1266 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1268 ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1269 if (ret)
1270 goto err_release_pl_mem;
1271 da8xx_fb_info->cmap.len = par->palette_sz;
1273 /* initialize var_screeninfo */
1274 da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1275 fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1277 dev_set_drvdata(&device->dev, da8xx_fb_info);
1279 /* initialize the vsync wait queue */
1280 init_waitqueue_head(&par->vsync_wait);
1281 par->vsync_timeout = HZ / 5;
1283 /* Register the Frame Buffer */
1284 if (register_framebuffer(da8xx_fb_info) < 0) {
1285 dev_err(&device->dev,
1286 "GLCD: Frame Buffer Registration Failed!\n");
1287 ret = -EINVAL;
1288 goto err_dealloc_cmap;
1289 }
1291 #ifdef CONFIG_CPU_FREQ
1292 ret = lcd_da8xx_cpufreq_register(par);
1293 if (ret) {
1294 dev_err(&device->dev, "failed to register cpufreq\n");
1295 goto err_cpu_freq;
1296 }
1297 #endif
1299 if (lcd_revision == LCD_VERSION_1)
1300 lcdc_irq_handler = lcdc_irq_handler_rev01;
1301 else
1302 lcdc_irq_handler = lcdc_irq_handler_rev02;
1304 ret = request_irq(par->irq, lcdc_irq_handler, 0,
1305 DRIVER_NAME, par);
1306 if (ret)
1307 goto irq_freq;
1308 return 0;
1310 irq_freq:
1311 #ifdef CONFIG_CPU_FREQ
1312 lcd_da8xx_cpufreq_deregister(par);
1313 #endif
1314 err_cpu_freq:
1315 unregister_framebuffer(da8xx_fb_info);
1317 err_dealloc_cmap:
1318 fb_dealloc_cmap(&da8xx_fb_info->cmap);
1320 err_release_pl_mem:
1321 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1322 par->p_palette_base);
1324 err_release_fb_mem:
1325 dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1327 err_release_fb:
1328 framebuffer_release(da8xx_fb_info);
1330 err_clk_disable:
1331 clk_disable(fb_clk);
1333 err_clk_put:
1334 clk_put(fb_clk);
1336 err_ioremap:
1337 iounmap((void __iomem *)da8xx_fb_reg_base);
1339 err_request_mem:
1340 release_mem_region(lcdc_regs->start, len);
1342 return ret;
1343 }
1345 #ifdef CONFIG_PM
1346 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1347 {
1348 struct fb_info *info = platform_get_drvdata(dev);
1349 struct da8xx_fb_par *par = info->par;
1351 console_lock();
1352 if (par->panel_power_ctrl)
1353 par->panel_power_ctrl(0);
1355 fb_set_suspend(info, 1);
1356 lcd_disable_raster();
1357 clk_disable(par->lcdc_clk);
1358 console_unlock();
1360 return 0;
1361 }
1362 static int fb_resume(struct platform_device *dev)
1363 {
1364 struct fb_info *info = platform_get_drvdata(dev);
1365 struct da8xx_fb_par *par = info->par;
1367 console_lock();
1368 if (par->panel_power_ctrl)
1369 par->panel_power_ctrl(1);
1371 clk_enable(par->lcdc_clk);
1372 lcd_enable_raster();
1373 fb_set_suspend(info, 0);
1374 console_unlock();
1376 return 0;
1377 }
1378 #else
1379 #define fb_suspend NULL
1380 #define fb_resume NULL
1381 #endif
1383 static struct platform_driver da8xx_fb_driver = {
1384 .probe = fb_probe,
1385 .remove = __devexit_p(fb_remove),
1386 .suspend = fb_suspend,
1387 .resume = fb_resume,
1388 .driver = {
1389 .name = DRIVER_NAME,
1390 .owner = THIS_MODULE,
1391 },
1392 };
1394 static int __init da8xx_fb_init(void)
1395 {
1396 return platform_driver_register(&da8xx_fb_driver);
1397 }
1399 static void __exit da8xx_fb_cleanup(void)
1400 {
1401 platform_driver_unregister(&da8xx_fb_driver);
1402 }
1404 module_init(da8xx_fb_init);
1405 module_exit(da8xx_fb_cleanup);
1407 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1408 MODULE_AUTHOR("Texas Instruments");
1409 MODULE_LICENSE("GPL");