video:da8xx-fb: Disable and reset sequence on version2 of LCDC
[sitara-epos/sitara-epos-kernel.git] / drivers / video / da8xx-fb.c
1 /*
2  * Copyright (C) 2008-2009 MontaVista Software Inc.
3  * Copyright (C) 2008-2009 Texas Instruments Inc
4  *
5  * Based on the LCD driver for TI Avalanche processors written by
6  * Ajay Singh and Shalom Hai.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option)any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21  */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/fb.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/interrupt.h>
30 #include <linux/clk.h>
31 #include <linux/cpufreq.h>
32 #include <linux/console.h>
33 #include <linux/slab.h>
34 #include <video/da8xx-fb.h>
36 #define DRIVER_NAME "da8xx_lcdc"
38 #define LCD_VERSION_1   1
39 #define LCD_VERSION_2   2
41 /* LCD Status Register */
42 #define LCD_END_OF_FRAME1               BIT(9)
43 #define LCD_END_OF_FRAME0               BIT(8)
44 #define LCD_PL_LOAD_DONE                BIT(6)
45 #define LCD_FIFO_UNDERFLOW              BIT(5)
46 #define LCD_SYNC_LOST                   BIT(2)
48 /* LCD DMA Control Register */
49 #define LCD_DMA_BURST_SIZE(x)           ((x) << 4)
50 #define LCD_DMA_BURST_1                 0x0
51 #define LCD_DMA_BURST_2                 0x1
52 #define LCD_DMA_BURST_4                 0x2
53 #define LCD_DMA_BURST_8                 0x3
54 #define LCD_DMA_BURST_16                0x4
55 #define LCD_V1_END_OF_FRAME_INT_ENA     BIT(2)
56 #define LCD_V2_END_OF_FRAME0_INT_ENA    BIT(8)
57 #define LCD_V2_END_OF_FRAME1_INT_ENA    BIT(9)
58 #define LCD_DUAL_FRAME_BUFFER_ENABLE    BIT(0)
60 /* LCD Control Register */
61 #define LCD_CLK_DIVISOR(x)              ((x) << 8)
62 #define LCD_RASTER_MODE                 0x01
64 /* LCD Raster Control Register */
65 #define LCD_PALETTE_LOAD_MODE(x)        ((x) << 20)
66 #define PALETTE_AND_DATA                0x00
67 #define PALETTE_ONLY                    0x01
68 #define DATA_ONLY                       0x02
70 #define LCD_MONO_8BIT_MODE              BIT(9)
71 #define LCD_RASTER_ORDER                BIT(8)
72 #define LCD_TFT_MODE                    BIT(7)
73 #define LCD_V1_UNDERFLOW_INT_ENA        BIT(6)
74 #define LCD_V2_UNDERFLOW_INT_ENA        BIT(5)
75 #define LCD_V1_PL_INT_ENA               BIT(4)
76 #define LCD_V2_PL_INT_ENA               BIT(6)
77 #define LCD_MONOCHROME_MODE             BIT(1)
78 #define LCD_RASTER_ENABLE               BIT(0)
79 #define LCD_TFT_ALT_ENABLE              BIT(23)
80 #define LCD_STN_565_ENABLE              BIT(24)
81 #define LCD_V2_DMA_CLK_EN               BIT(2)
82 #define LCD_V2_LIDD_CLK_EN              BIT(1)
83 #define LCD_V2_CORE_CLK_EN              BIT(0)
84 #define LCD_V2_LPP_B10                  26
86 /* LCD Raster Timing 2 Register */
87 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
88 #define LCD_AC_BIAS_FREQUENCY(x)                ((x) << 8)
89 #define LCD_SYNC_CTRL                           BIT(25)
90 #define LCD_SYNC_EDGE                           BIT(24)
91 #define LCD_INVERT_PIXEL_CLOCK                  BIT(22)
92 #define LCD_INVERT_LINE_CLOCK                   BIT(21)
93 #define LCD_INVERT_FRAME_CLOCK                  BIT(20)
95 /* LCD Block */
96 #define  LCD_PID_REG                            0x0
97 #define  LCD_CTRL_REG                           0x4
98 #define  LCD_STAT_REG                           0x8
99 #define  LCD_RASTER_CTRL_REG                    0x28
100 #define  LCD_RASTER_TIMING_0_REG                0x2C
101 #define  LCD_RASTER_TIMING_1_REG                0x30
102 #define  LCD_RASTER_TIMING_2_REG                0x34
103 #define  LCD_DMA_CTRL_REG                       0x40
104 #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG        0x44
105 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG     0x48
106 #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG        0x4C
107 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG     0x50
109 /* Interrupt Registers available only in Version 2 */
110 #define  LCD_RAW_STAT_REG                       0x58
111 #define  LCD_MASKED_STAT_REG                    0x5c
112 #define  LCD_INT_ENABLE_SET_REG                 0x60
113 #define  LCD_INT_ENABLE_CLR_REG                 0x64
114 #define  LCD_END_OF_INT_IND_REG                 0x68
116 /* Clock registers available only on Version 2 */
117 #define  LCD_CLK_ENABLE_REG                     0x6c
118 #define  LCD_CLK_RESET_REG                      0x70
119 #define  LCD_CLK_MAIN_RESET                     BIT(3)
121 #define LCD_NUM_BUFFERS 2
123 #define WSI_TIMEOUT     50
124 #define PALETTE_SIZE    256
125 #define LEFT_MARGIN     64
126 #define RIGHT_MARGIN    64
127 #define UPPER_MARGIN    32
128 #define LOWER_MARGIN    32
130 static resource_size_t da8xx_fb_reg_base;
131 static struct resource *lcdc_regs;
132 static unsigned int lcd_revision;
133 static irq_handler_t lcdc_irq_handler;
135 static inline unsigned int lcdc_read(unsigned int addr)
137         return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
140 static inline void lcdc_write(unsigned int val, unsigned int addr)
142         __raw_writel(val, da8xx_fb_reg_base + (addr));
145 struct da8xx_fb_par {
146         resource_size_t p_palette_base;
147         unsigned char *v_palette_base;
148         dma_addr_t              vram_phys;
149         unsigned long           vram_size;
150         void                    *vram_virt;
151         unsigned int            dma_start;
152         unsigned int            dma_end;
153         struct clk *lcdc_clk;
154         int irq;
155         unsigned short pseudo_palette[16];
156         unsigned int palette_sz;
157         unsigned int pxl_clk;
158         int blank;
159         wait_queue_head_t       vsync_wait;
160         int                     vsync_flag;
161         int                     vsync_timeout;
162 #ifdef CONFIG_CPU_FREQ
163         struct notifier_block   freq_transition;
164 #endif
165         void (*panel_power_ctrl)(int);
166 };
168 /* Variable Screen Information */
169 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
170         .xoffset = 0,
171         .yoffset = 0,
172         .transp = {0, 0, 0},
173         .nonstd = 0,
174         .activate = 0,
175         .height = -1,
176         .width = -1,
177         .pixclock = 46666,      /* 46us - AUO display */
178         .accel_flags = 0,
179         .left_margin = LEFT_MARGIN,
180         .right_margin = RIGHT_MARGIN,
181         .upper_margin = UPPER_MARGIN,
182         .lower_margin = LOWER_MARGIN,
183         .sync = 0,
184         .vmode = FB_VMODE_NONINTERLACED
185 };
187 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
188         .id = "DA8xx FB Drv",
189         .type = FB_TYPE_PACKED_PIXELS,
190         .type_aux = 0,
191         .visual = FB_VISUAL_PSEUDOCOLOR,
192         .xpanstep = 0,
193         .ypanstep = 1,
194         .ywrapstep = 0,
195         .accel = FB_ACCEL_NONE
196 };
198 struct da8xx_panel {
199         const char      name[25];       /* Full name <vendor>_<model> */
200         unsigned short  width;
201         unsigned short  height;
202         int             hfp;            /* Horizontal front porch */
203         int             hbp;            /* Horizontal back porch */
204         int             hsw;            /* Horizontal Sync Pulse Width */
205         int             vfp;            /* Vertical front porch */
206         int             vbp;            /* Vertical back porch */
207         int             vsw;            /* Vertical Sync Pulse Width */
208         unsigned int    pxl_clk;        /* Pixel clock */
209         unsigned char   invert_pxl_clk; /* Invert Pixel clock */
210 };
212 static struct da8xx_panel known_lcd_panels[] = {
213         /* Sharp LCD035Q3DG01 */
214         [0] = {
215                 .name = "Sharp_LCD035Q3DG01",
216                 .width = 320,
217                 .height = 240,
218                 .hfp = 8,
219                 .hbp = 6,
220                 .hsw = 0,
221                 .vfp = 2,
222                 .vbp = 2,
223                 .vsw = 0,
224                 .pxl_clk = 4608000,
225                 .invert_pxl_clk = 1,
226         },
227         /* Sharp LK043T1DG01 */
228         [1] = {
229                 .name = "Sharp_LK043T1DG01",
230                 .width = 480,
231                 .height = 272,
232                 .hfp = 2,
233                 .hbp = 2,
234                 .hsw = 41,
235                 .vfp = 2,
236                 .vbp = 2,
237                 .vsw = 10,
238                 .pxl_clk = 7833600,
239                 .invert_pxl_clk = 0,
240         },
241 };
243 /* Enable the Raster Engine of the LCD Controller */
244 static inline void lcd_enable_raster(void)
246         u32 reg;
248         /* Bring LCDC out of reset */
249         if (lcd_revision == LCD_VERSION_2)
250                 lcdc_write(0, LCD_CLK_RESET_REG);
252         reg = lcdc_read(LCD_RASTER_CTRL_REG);
253         if (!(reg & LCD_RASTER_ENABLE))
254                 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
257 /* Disable the Raster Engine of the LCD Controller */
258 static inline void lcd_disable_raster(void)
260         u32 reg;
262         reg = lcdc_read(LCD_RASTER_CTRL_REG);
263         if (reg & LCD_RASTER_ENABLE)
264                 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
266         if (lcd_revision == LCD_VERSION_2)
267                 /* Write 1 to reset LCDC */
268                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
271 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
273         u32 start;
274         u32 end;
275         u32 reg_ras;
276         u32 reg_dma;
277         u32 reg_int;
279         /* init reg to clear PLM (loading mode) fields */
280         reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
281         reg_ras &= ~(3 << 20);
283         reg_dma  = lcdc_read(LCD_DMA_CTRL_REG);
285         if (load_mode == LOAD_DATA) {
286                 start    = par->dma_start;
287                 end      = par->dma_end;
289                 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
290                 if (lcd_revision == LCD_VERSION_1) {
291                         reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
292                 } else {
293                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
294                                 LCD_V2_END_OF_FRAME0_INT_ENA |
295                                 LCD_V2_END_OF_FRAME1_INT_ENA;
296                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
297                 }
298                 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
300                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
301                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
302                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
303                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
304         } else if (load_mode == LOAD_PALETTE) {
305                 start    = par->p_palette_base;
306                 end      = start + par->palette_sz - 1;
308                 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
310                 if (lcd_revision == LCD_VERSION_1) {
311                         reg_ras |= LCD_V1_PL_INT_ENA;
312                 } else {
313                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
314                                 LCD_V2_PL_INT_ENA;
315                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
316                 }
318                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
319                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
320         }
322         lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
323         lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
325         /*
326          * The Raster enable bit must be set after all other control fields are
327          * set.
328          */
329         lcd_enable_raster();
332 /* Configure the Burst Size of DMA */
333 static int lcd_cfg_dma(int burst_size)
335         u32 reg;
337         reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
338         switch (burst_size) {
339         case 1:
340                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
341                 break;
342         case 2:
343                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
344                 break;
345         case 4:
346                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
347                 break;
348         case 8:
349                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
350                 break;
351         case 16:
352                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
353                 break;
354         default:
355                 return -EINVAL;
356         }
357         lcdc_write(reg, LCD_DMA_CTRL_REG);
359         return 0;
362 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
364         u32 reg;
366         /* Set the AC Bias Period and Number of Transisitons per Interrupt */
367         reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
368         reg |= LCD_AC_BIAS_FREQUENCY(period) |
369                 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
370         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
373 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
374                 int front_porch)
376         u32 reg;
378         reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
379         reg |= ((back_porch & 0xff) << 24)
380             | ((front_porch & 0xff) << 16)
381             | ((pulse_width & 0x3f) << 10);
382         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
385 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
386                 int front_porch)
388         u32 reg;
390         reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
391         reg |= ((back_porch & 0xff) << 24)
392             | ((front_porch & 0xff) << 16)
393             | ((pulse_width & 0x3f) << 10);
394         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
397 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
399         u32 reg;
400         u32 reg_int;
402         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
403                                                 LCD_MONO_8BIT_MODE |
404                                                 LCD_MONOCHROME_MODE);
406         switch (cfg->p_disp_panel->panel_shade) {
407         case MONOCHROME:
408                 reg |= LCD_MONOCHROME_MODE;
409                 if (cfg->mono_8bit_mode)
410                         reg |= LCD_MONO_8BIT_MODE;
411                 break;
412         case COLOR_ACTIVE:
413                 reg |= LCD_TFT_MODE;
414                 if (cfg->tft_alt_mode)
415                         reg |= LCD_TFT_ALT_ENABLE;
416                 break;
418         case COLOR_PASSIVE:
419                 if (cfg->stn_565_mode)
420                         reg |= LCD_STN_565_ENABLE;
421                 break;
423         default:
424                 return -EINVAL;
425         }
427         /* enable additional interrupts here */
428         if (lcd_revision == LCD_VERSION_1) {
429                 reg |= LCD_V1_UNDERFLOW_INT_ENA;
430         } else {
431                 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
432                         LCD_V2_UNDERFLOW_INT_ENA;
433                 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
434         }
436         lcdc_write(reg, LCD_RASTER_CTRL_REG);
438         reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
440         if (cfg->sync_ctrl)
441                 reg |= LCD_SYNC_CTRL;
442         else
443                 reg &= ~LCD_SYNC_CTRL;
445         if (cfg->sync_edge)
446                 reg |= LCD_SYNC_EDGE;
447         else
448                 reg &= ~LCD_SYNC_EDGE;
450         if (cfg->invert_line_clock)
451                 reg |= LCD_INVERT_LINE_CLOCK;
452         else
453                 reg &= ~LCD_INVERT_LINE_CLOCK;
455         if (cfg->invert_frm_clock)
456                 reg |= LCD_INVERT_FRAME_CLOCK;
457         else
458                 reg &= ~LCD_INVERT_FRAME_CLOCK;
460         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
462         return 0;
465 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
466                 u32 bpp, u32 raster_order)
468         u32 reg;
470         /* Set the Panel Width */
471         /* Pixels per line = (PPL + 1)*16 */
472         if (lcd_revision == LCD_VERSION_1) {
473                 /*
474                  * 0x3F in bits 4..9 gives max horizontal resolution = 1024
475                  * pixels.
476                  */
477                 width &= 0x3f0;
478         } else {
479                 /*
480                  * 0x7F in bits 4..10 gives max horizontal resolution = 2048
481                  * pixels.
482                  */
483                 width &= 0x7f0;
484         }
486         reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
487         reg &= 0xfffffc00;
488         if (lcd_revision == LCD_VERSION_1) {
489                 reg |= ((width >> 4) - 1) << 4;
490         } else {
491                 width = (width >> 4) - 1;
492                 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
493         }
494         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
496         /* Set the Panel Height */
497         /* Set bits 9:0 of Lines Per Pixel */
498         reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
499         reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
500         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
502         /* Set bit 10 of Lines Per Pixel */
503         if (lcd_revision == LCD_VERSION_2) {
504                 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
505                 reg |= ((height - 1) & 0x400) << 16;
506                 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
507         }
509         /* Set the Raster Order of the Frame Buffer */
510         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
511         if (raster_order)
512                 reg |= LCD_RASTER_ORDER;
513         lcdc_write(reg, LCD_RASTER_CTRL_REG);
515         switch (bpp) {
516         case 1:
517         case 2:
518         case 4:
519         case 16:
520                 par->palette_sz = 16 * 2;
521                 break;
523         case 8:
524                 par->palette_sz = 256 * 2;
525                 break;
527         default:
528                 return -EINVAL;
529         }
531         return 0;
534 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
535                               unsigned blue, unsigned transp,
536                               struct fb_info *info)
538         struct da8xx_fb_par *par = info->par;
539         unsigned short *palette = (unsigned short *) par->v_palette_base;
540         u_short pal;
541         int update_hw = 0;
543         if (regno > 255)
544                 return 1;
546         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
547                 return 1;
549         if (info->var.bits_per_pixel == 8) {
550                 red >>= 4;
551                 green >>= 8;
552                 blue >>= 12;
554                 pal = (red & 0x0f00);
555                 pal |= (green & 0x00f0);
556                 pal |= (blue & 0x000f);
558                 if (palette[regno] != pal) {
559                         update_hw = 1;
560                         palette[regno] = pal;
561                 }
562         } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
563                 red >>= (16 - info->var.red.length);
564                 red <<= info->var.red.offset;
566                 green >>= (16 - info->var.green.length);
567                 green <<= info->var.green.offset;
569                 blue >>= (16 - info->var.blue.length);
570                 blue <<= info->var.blue.offset;
572                 par->pseudo_palette[regno] = red | green | blue;
574                 if (palette[0] != 0x4000) {
575                         update_hw = 1;
576                         palette[0] = 0x4000;
577                 }
578         }
580         /* Update the palette in the h/w as needed. */
581         if (update_hw)
582                 lcd_blit(LOAD_PALETTE, par);
584         return 0;
587 static void lcd_reset(struct da8xx_fb_par *par)
589         /* Disable the Raster if previously Enabled */
590         lcd_disable_raster();
592         /* DMA has to be disabled */
593         lcdc_write(0, LCD_DMA_CTRL_REG);
594         lcdc_write(0, LCD_RASTER_CTRL_REG);
596         if (lcd_revision == LCD_VERSION_2) {
597                 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
598                 /* Write 1 to reset */
599                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
600                 lcdc_write(0, LCD_CLK_RESET_REG);
601         }
604 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
606         unsigned int lcd_clk, div;
608         lcd_clk = clk_get_rate(par->lcdc_clk);
609         div = lcd_clk / par->pxl_clk;
611         /* Configure the LCD clock divisor. */
612         lcdc_write(LCD_CLK_DIVISOR(div) |
613                         (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
615         if (lcd_revision == LCD_VERSION_2)
616                 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
617                                 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
621 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
622                 struct da8xx_panel *panel)
624         u32 bpp;
625         int ret = 0;
627         lcd_reset(par);
629         /* Calculate the divider */
630         lcd_calc_clk_divider(par);
632         if (panel->invert_pxl_clk)
633                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
634                         LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
635         else
636                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
637                         ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
639         /* Configure the DMA burst size. */
640         ret = lcd_cfg_dma(cfg->dma_burst_sz);
641         if (ret < 0)
642                 return ret;
644         /* Configure the AC bias properties. */
645         lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
647         /* Configure the vertical and horizontal sync properties. */
648         lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
649         lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
651         /* Configure for disply */
652         ret = lcd_cfg_display(cfg);
653         if (ret < 0)
654                 return ret;
656         if (QVGA != cfg->p_disp_panel->panel_type)
657                 return -EINVAL;
659         if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
660             cfg->bpp >= cfg->p_disp_panel->min_bpp)
661                 bpp = cfg->bpp;
662         else
663                 bpp = cfg->p_disp_panel->max_bpp;
664         if (bpp == 12)
665                 bpp = 16;
666         ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
667                                 (unsigned int)panel->height, bpp,
668                                 cfg->raster_order);
669         if (ret < 0)
670                 return ret;
672         /* Configure FDD */
673         lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
674                        (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
676         return 0;
679 /* IRQ handler for version 2 of LCDC */
680 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
682         struct da8xx_fb_par *par = arg;
683         u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
684         u32 reg_int;
686         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
687                 lcd_disable_raster();
688                 lcdc_write(stat, LCD_MASKED_STAT_REG);
689                 lcd_enable_raster();
690         } else if (stat & LCD_PL_LOAD_DONE) {
691                 /*
692                  * Must disable raster before changing state of any control bit.
693                  * And also must be disabled before clearing the PL loading
694                  * interrupt via the following write to the status register. If
695                  * this is done after then one gets multiple PL done interrupts.
696                  */
697                 lcd_disable_raster();
699                 lcdc_write(stat, LCD_MASKED_STAT_REG);
701                 /* Disable PL completion inerrupt */
702                 reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |
703                        (LCD_V2_PL_INT_ENA);
704                 lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);
706                 /* Setup and start data loading mode */
707                 lcd_blit(LOAD_DATA, par);
708         } else {
709                 lcdc_write(stat, LCD_MASKED_STAT_REG);
711                 if (stat & LCD_END_OF_FRAME0) {
712                         lcdc_write(par->dma_start,
713                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
714                         lcdc_write(par->dma_end,
715                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
716                         par->vsync_flag = 1;
717                         wake_up_interruptible(&par->vsync_wait);
718                 }
720                 if (stat & LCD_END_OF_FRAME1) {
721                         lcdc_write(par->dma_start,
722                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
723                         lcdc_write(par->dma_end,
724                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
725                         par->vsync_flag = 1;
726                         wake_up_interruptible(&par->vsync_wait);
727                 }
728         }
730         lcdc_write(0, LCD_END_OF_INT_IND_REG);
731         return IRQ_HANDLED;
734 /* IRQ handler for version 1 LCDC */
735 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
737         struct da8xx_fb_par *par = arg;
738         u32 stat = lcdc_read(LCD_STAT_REG);
739         u32 reg_ras;
741         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
742                 lcd_disable_raster();
743                 lcdc_write(stat, LCD_STAT_REG);
744                 lcd_enable_raster();
745         } else if (stat & LCD_PL_LOAD_DONE) {
746                 /*
747                  * Must disable raster before changing state of any control bit.
748                  * And also must be disabled before clearing the PL loading
749                  * interrupt via the following write to the status register. If
750                  * this is done after then one gets multiple PL done interrupts.
751                  */
752                 lcd_disable_raster();
754                 lcdc_write(stat, LCD_STAT_REG);
756                 /* Disable PL completion inerrupt */
757                 reg_ras  = lcdc_read(LCD_RASTER_CTRL_REG);
758                 reg_ras &= ~LCD_V1_PL_INT_ENA;
759                 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
761                 /* Setup and start data loading mode */
762                 lcd_blit(LOAD_DATA, par);
763         } else {
764                 lcdc_write(stat, LCD_STAT_REG);
766                 if (stat & LCD_END_OF_FRAME0) {
767                         lcdc_write(par->dma_start,
768                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
769                         lcdc_write(par->dma_end,
770                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
771                         par->vsync_flag = 1;
772                         wake_up_interruptible(&par->vsync_wait);
773                 }
775                 if (stat & LCD_END_OF_FRAME1) {
776                         lcdc_write(par->dma_start,
777                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
778                         lcdc_write(par->dma_end,
779                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
780                         par->vsync_flag = 1;
781                         wake_up_interruptible(&par->vsync_wait);
782                 }
783         }
785         return IRQ_HANDLED;
788 static int fb_check_var(struct fb_var_screeninfo *var,
789                         struct fb_info *info)
791         int err = 0;
793         switch (var->bits_per_pixel) {
794         case 1:
795         case 8:
796                 var->red.offset = 0;
797                 var->red.length = 8;
798                 var->green.offset = 0;
799                 var->green.length = 8;
800                 var->blue.offset = 0;
801                 var->blue.length = 8;
802                 var->transp.offset = 0;
803                 var->transp.length = 0;
804                 break;
805         case 4:
806                 var->red.offset = 0;
807                 var->red.length = 4;
808                 var->green.offset = 0;
809                 var->green.length = 4;
810                 var->blue.offset = 0;
811                 var->blue.length = 4;
812                 var->transp.offset = 0;
813                 var->transp.length = 0;
814                 break;
815         case 16:                /* RGB 565 */
816                 var->red.offset = 11;
817                 var->red.length = 5;
818                 var->green.offset = 5;
819                 var->green.length = 6;
820                 var->blue.offset = 0;
821                 var->blue.length = 5;
822                 var->transp.offset = 0;
823                 var->transp.length = 0;
824                 break;
825         default:
826                 err = -EINVAL;
827         }
829         var->red.msb_right = 0;
830         var->green.msb_right = 0;
831         var->blue.msb_right = 0;
832         var->transp.msb_right = 0;
833         return err;
836 #ifdef CONFIG_CPU_FREQ
837 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
838                                      unsigned long val, void *data)
840         struct da8xx_fb_par *par;
842         par = container_of(nb, struct da8xx_fb_par, freq_transition);
843         if (val == CPUFREQ_PRECHANGE) {
844                 lcd_disable_raster();
845         } else if (val == CPUFREQ_POSTCHANGE) {
846                 lcd_calc_clk_divider(par);
847                 lcd_enable_raster();
848         }
850         return 0;
853 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
855         par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
857         return cpufreq_register_notifier(&par->freq_transition,
858                                          CPUFREQ_TRANSITION_NOTIFIER);
861 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
863         cpufreq_unregister_notifier(&par->freq_transition,
864                                     CPUFREQ_TRANSITION_NOTIFIER);
866 #endif
868 static int __devexit fb_remove(struct platform_device *dev)
870         struct fb_info *info = dev_get_drvdata(&dev->dev);
872         if (info) {
873                 struct da8xx_fb_par *par = info->par;
875 #ifdef CONFIG_CPU_FREQ
876                 lcd_da8xx_cpufreq_deregister(par);
877 #endif
878                 if (par->panel_power_ctrl)
879                         par->panel_power_ctrl(0);
881                 lcd_disable_raster();
882                 lcdc_write(0, LCD_RASTER_CTRL_REG);
884                 /* disable DMA  */
885                 lcdc_write(0, LCD_DMA_CTRL_REG);
887                 unregister_framebuffer(info);
888                 fb_dealloc_cmap(&info->cmap);
889                 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
890                                   par->p_palette_base);
891                 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
892                                   par->vram_phys);
893                 free_irq(par->irq, par);
894                 clk_disable(par->lcdc_clk);
895                 clk_put(par->lcdc_clk);
896                 framebuffer_release(info);
897                 iounmap((void __iomem *)da8xx_fb_reg_base);
898                 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
900         }
901         return 0;
904 /*
905  * Function to wait for vertical sync which for this LCD peripheral
906  * translates into waiting for the current raster frame to complete.
907  */
908 static int fb_wait_for_vsync(struct fb_info *info)
910         struct da8xx_fb_par *par = info->par;
911         int ret;
913         /*
914          * Set flag to 0 and wait for isr to set to 1. It would seem there is a
915          * race condition here where the ISR could have occurred just before or
916          * just after this set. But since we are just coarsely waiting for
917          * a frame to complete then that's OK. i.e. if the frame completed
918          * just before this code executed then we have to wait another full
919          * frame time but there is no way to avoid such a situation. On the
920          * other hand if the frame completed just after then we don't need
921          * to wait long at all. Either way we are guaranteed to return to the
922          * user immediately after a frame completion which is all that is
923          * required.
924          */
925         par->vsync_flag = 0;
926         ret = wait_event_interruptible_timeout(par->vsync_wait,
927                                                par->vsync_flag != 0,
928                                                par->vsync_timeout);
929         if (ret < 0)
930                 return ret;
931         if (ret == 0)
932                 return -ETIMEDOUT;
934         return 0;
937 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
938                           unsigned long arg)
940         struct lcd_sync_arg sync_arg;
942         switch (cmd) {
943         case FBIOGET_CONTRAST:
944         case FBIOPUT_CONTRAST:
945         case FBIGET_BRIGHTNESS:
946         case FBIPUT_BRIGHTNESS:
947         case FBIGET_COLOR:
948         case FBIPUT_COLOR:
949                 return -ENOTTY;
950         case FBIPUT_HSYNC:
951                 if (copy_from_user(&sync_arg, (char *)arg,
952                                 sizeof(struct lcd_sync_arg)))
953                         return -EFAULT;
954                 lcd_cfg_horizontal_sync(sync_arg.back_porch,
955                                         sync_arg.pulse_width,
956                                         sync_arg.front_porch);
957                 break;
958         case FBIPUT_VSYNC:
959                 if (copy_from_user(&sync_arg, (char *)arg,
960                                 sizeof(struct lcd_sync_arg)))
961                         return -EFAULT;
962                 lcd_cfg_vertical_sync(sync_arg.back_porch,
963                                         sync_arg.pulse_width,
964                                         sync_arg.front_porch);
965                 break;
966         case FBIO_WAITFORVSYNC:
967                 return fb_wait_for_vsync(info);
968         default:
969                 return -EINVAL;
970         }
971         return 0;
974 static int cfb_blank(int blank, struct fb_info *info)
976         struct da8xx_fb_par *par = info->par;
977         int ret = 0;
979         if (par->blank == blank)
980                 return 0;
982         par->blank = blank;
983         switch (blank) {
984         case FB_BLANK_UNBLANK:
985                 if (par->panel_power_ctrl)
986                         par->panel_power_ctrl(1);
988                 lcd_enable_raster();
989                 break;
990         case FB_BLANK_POWERDOWN:
991                 if (par->panel_power_ctrl)
992                         par->panel_power_ctrl(0);
994                 lcd_disable_raster();
995                 break;
996         default:
997                 ret = -EINVAL;
998         }
1000         return ret;
1003 /*
1004  * Set new x,y offsets in the virtual display for the visible area and switch
1005  * to the new mode.
1006  */
1007 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1008                              struct fb_info *fbi)
1010         int ret = 0;
1011         struct fb_var_screeninfo new_var;
1012         struct da8xx_fb_par         *par = fbi->par;
1013         struct fb_fix_screeninfo    *fix = &fbi->fix;
1014         unsigned int end;
1015         unsigned int start;
1017         if (var->xoffset != fbi->var.xoffset ||
1018                         var->yoffset != fbi->var.yoffset) {
1019                 memcpy(&new_var, &fbi->var, sizeof(new_var));
1020                 new_var.xoffset = var->xoffset;
1021                 new_var.yoffset = var->yoffset;
1022                 if (fb_check_var(&new_var, fbi))
1023                         ret = -EINVAL;
1024                 else {
1025                         memcpy(&fbi->var, &new_var, sizeof(new_var));
1027                         start   = fix->smem_start +
1028                                 new_var.yoffset * fix->line_length +
1029                                 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1030                         end     = start + fbi->var.yres * fix->line_length - 1;
1031                         par->dma_start  = start;
1032                         par->dma_end    = end;
1033                 }
1034         }
1036         return ret;
1039 static struct fb_ops da8xx_fb_ops = {
1040         .owner = THIS_MODULE,
1041         .fb_check_var = fb_check_var,
1042         .fb_setcolreg = fb_setcolreg,
1043         .fb_pan_display = da8xx_pan_display,
1044         .fb_ioctl = fb_ioctl,
1045         .fb_fillrect = cfb_fillrect,
1046         .fb_copyarea = cfb_copyarea,
1047         .fb_imageblit = cfb_imageblit,
1048         .fb_blank = cfb_blank,
1049 };
1051 static int __devinit fb_probe(struct platform_device *device)
1053         struct da8xx_lcdc_platform_data *fb_pdata =
1054                                                 device->dev.platform_data;
1055         struct lcd_ctrl_config *lcd_cfg;
1056         struct da8xx_panel *lcdc_info;
1057         struct fb_info *da8xx_fb_info;
1058         struct clk *fb_clk = NULL;
1059         struct da8xx_fb_par *par;
1060         resource_size_t len;
1061         int ret, i;
1063         if (fb_pdata == NULL) {
1064                 dev_err(&device->dev, "Can not get platform data\n");
1065                 return -ENOENT;
1066         }
1068         lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1069         if (!lcdc_regs) {
1070                 dev_err(&device->dev,
1071                         "Can not get memory resource for LCD controller\n");
1072                 return -ENOENT;
1073         }
1075         len = resource_size(lcdc_regs);
1077         lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
1078         if (!lcdc_regs)
1079                 return -EBUSY;
1081         da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
1082         if (!da8xx_fb_reg_base) {
1083                 ret = -EBUSY;
1084                 goto err_request_mem;
1085         }
1087         fb_clk = clk_get(&device->dev, NULL);
1088         if (IS_ERR(fb_clk)) {
1089                 dev_err(&device->dev, "Can not get device clock\n");
1090                 ret = -ENODEV;
1091                 goto err_ioremap;
1092         }
1093         ret = clk_enable(fb_clk);
1094         if (ret)
1095                 goto err_clk_put;
1097         /* Determine LCD IP Version */
1098         switch (lcdc_read(LCD_PID_REG)) {
1099         case 0x4C100102:
1100                 lcd_revision = LCD_VERSION_1;
1101                 break;
1102         case 0x4F200800:
1103                 lcd_revision = LCD_VERSION_2;
1104                 break;
1105         default:
1106                 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1107                                 "defaulting to LCD revision 1\n",
1108                                 lcdc_read(LCD_PID_REG));
1109                 lcd_revision = LCD_VERSION_1;
1110                 break;
1111         }
1113         for (i = 0, lcdc_info = known_lcd_panels;
1114                 i < ARRAY_SIZE(known_lcd_panels);
1115                 i++, lcdc_info++) {
1116                 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1117                         break;
1118         }
1120         if (i == ARRAY_SIZE(known_lcd_panels)) {
1121                 dev_err(&device->dev, "GLCD: No valid panel found\n");
1122                 ret = -ENODEV;
1123                 goto err_clk_disable;
1124         } else
1125                 dev_info(&device->dev, "GLCD: Found %s panel\n",
1126                                         fb_pdata->type);
1128         lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1130         da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1131                                         &device->dev);
1132         if (!da8xx_fb_info) {
1133                 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1134                 ret = -ENOMEM;
1135                 goto err_clk_disable;
1136         }
1138         par = da8xx_fb_info->par;
1139         par->lcdc_clk = fb_clk;
1140         par->pxl_clk = lcdc_info->pxl_clk;
1141         if (fb_pdata->panel_power_ctrl) {
1142                 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1143                 par->panel_power_ctrl(1);
1144         }
1146         if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
1147                 dev_err(&device->dev, "lcd_init failed\n");
1148                 ret = -EFAULT;
1149                 goto err_release_fb;
1150         }
1152         /* allocate frame buffer */
1153         par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
1154         par->vram_size = PAGE_ALIGN(par->vram_size/8);
1155         par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1157         par->vram_virt = dma_alloc_coherent(NULL,
1158                                             par->vram_size,
1159                                             (resource_size_t *) &par->vram_phys,
1160                                             GFP_KERNEL | GFP_DMA);
1161         if (!par->vram_virt) {
1162                 dev_err(&device->dev,
1163                         "GLCD: kmalloc for frame buffer failed\n");
1164                 ret = -EINVAL;
1165                 goto err_release_fb;
1166         }
1168         da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1169         da8xx_fb_fix.smem_start    = par->vram_phys;
1170         da8xx_fb_fix.smem_len      = par->vram_size;
1171         da8xx_fb_fix.line_length   = (lcdc_info->width * lcd_cfg->bpp) / 8;
1173         par->dma_start = par->vram_phys;
1174         par->dma_end   = par->dma_start + lcdc_info->height *
1175                 da8xx_fb_fix.line_length - 1;
1177         /* allocate palette buffer */
1178         par->v_palette_base = dma_alloc_coherent(NULL,
1179                                                PALETTE_SIZE,
1180                                                (resource_size_t *)
1181                                                &par->p_palette_base,
1182                                                GFP_KERNEL | GFP_DMA);
1183         if (!par->v_palette_base) {
1184                 dev_err(&device->dev,
1185                         "GLCD: kmalloc for palette buffer failed\n");
1186                 ret = -EINVAL;
1187                 goto err_release_fb_mem;
1188         }
1189         memset(par->v_palette_base, 0, PALETTE_SIZE);
1191         par->irq = platform_get_irq(device, 0);
1192         if (par->irq < 0) {
1193                 ret = -ENOENT;
1194                 goto err_release_pl_mem;
1195         }
1197         /* Initialize par */
1198         da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
1200         da8xx_fb_var.xres = lcdc_info->width;
1201         da8xx_fb_var.xres_virtual = lcdc_info->width;
1203         da8xx_fb_var.yres         = lcdc_info->height;
1204         da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
1206         da8xx_fb_var.grayscale =
1207             lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
1208         da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1210         da8xx_fb_var.hsync_len = lcdc_info->hsw;
1211         da8xx_fb_var.vsync_len = lcdc_info->vsw;
1213         /* Initialize fbinfo */
1214         da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1215         da8xx_fb_info->fix = da8xx_fb_fix;
1216         da8xx_fb_info->var = da8xx_fb_var;
1217         da8xx_fb_info->fbops = &da8xx_fb_ops;
1218         da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1219         da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1220                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1222         ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1223         if (ret)
1224                 goto err_release_pl_mem;
1225         da8xx_fb_info->cmap.len = par->palette_sz;
1227         /* initialize var_screeninfo */
1228         da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1229         fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1231         dev_set_drvdata(&device->dev, da8xx_fb_info);
1233         /* initialize the vsync wait queue */
1234         init_waitqueue_head(&par->vsync_wait);
1235         par->vsync_timeout = HZ / 5;
1237         /* Register the Frame Buffer  */
1238         if (register_framebuffer(da8xx_fb_info) < 0) {
1239                 dev_err(&device->dev,
1240                         "GLCD: Frame Buffer Registration Failed!\n");
1241                 ret = -EINVAL;
1242                 goto err_dealloc_cmap;
1243         }
1245 #ifdef CONFIG_CPU_FREQ
1246         ret = lcd_da8xx_cpufreq_register(par);
1247         if (ret) {
1248                 dev_err(&device->dev, "failed to register cpufreq\n");
1249                 goto err_cpu_freq;
1250         }
1251 #endif
1253         if (lcd_revision == LCD_VERSION_1)
1254                 lcdc_irq_handler = lcdc_irq_handler_rev01;
1255         else
1256                 lcdc_irq_handler = lcdc_irq_handler_rev02;
1258         ret = request_irq(par->irq, lcdc_irq_handler, 0,
1259                         DRIVER_NAME, par);
1260         if (ret)
1261                 goto irq_freq;
1262         return 0;
1264 irq_freq:
1265 #ifdef CONFIG_CPU_FREQ
1266         lcd_da8xx_cpufreq_deregister(par);
1267 #endif
1268 err_cpu_freq:
1269         unregister_framebuffer(da8xx_fb_info);
1271 err_dealloc_cmap:
1272         fb_dealloc_cmap(&da8xx_fb_info->cmap);
1274 err_release_pl_mem:
1275         dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1276                           par->p_palette_base);
1278 err_release_fb_mem:
1279         dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1281 err_release_fb:
1282         framebuffer_release(da8xx_fb_info);
1284 err_clk_disable:
1285         clk_disable(fb_clk);
1287 err_clk_put:
1288         clk_put(fb_clk);
1290 err_ioremap:
1291         iounmap((void __iomem *)da8xx_fb_reg_base);
1293 err_request_mem:
1294         release_mem_region(lcdc_regs->start, len);
1296         return ret;
1299 #ifdef CONFIG_PM
1300 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1302         struct fb_info *info = platform_get_drvdata(dev);
1303         struct da8xx_fb_par *par = info->par;
1305         console_lock();
1306         if (par->panel_power_ctrl)
1307                 par->panel_power_ctrl(0);
1309         fb_set_suspend(info, 1);
1310         lcd_disable_raster();
1311         clk_disable(par->lcdc_clk);
1312         console_unlock();
1314         return 0;
1316 static int fb_resume(struct platform_device *dev)
1318         struct fb_info *info = platform_get_drvdata(dev);
1319         struct da8xx_fb_par *par = info->par;
1321         console_lock();
1322         if (par->panel_power_ctrl)
1323                 par->panel_power_ctrl(1);
1325         clk_enable(par->lcdc_clk);
1326         lcd_enable_raster();
1327         fb_set_suspend(info, 0);
1328         console_unlock();
1330         return 0;
1332 #else
1333 #define fb_suspend NULL
1334 #define fb_resume NULL
1335 #endif
1337 static struct platform_driver da8xx_fb_driver = {
1338         .probe = fb_probe,
1339         .remove = __devexit_p(fb_remove),
1340         .suspend = fb_suspend,
1341         .resume = fb_resume,
1342         .driver = {
1343                    .name = DRIVER_NAME,
1344                    .owner = THIS_MODULE,
1345                    },
1346 };
1348 static int __init da8xx_fb_init(void)
1350         return platform_driver_register(&da8xx_fb_driver);
1353 static void __exit da8xx_fb_cleanup(void)
1355         platform_driver_unregister(&da8xx_fb_driver);
1358 module_init(da8xx_fb_init);
1359 module_exit(da8xx_fb_cleanup);
1361 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1362 MODULE_AUTHOR("Texas Instruments");
1363 MODULE_LICENSE("GPL");