video: da8xx-fb: Increased resolution configuration of revised LCDC IP
[sitara-epos/sitara-epos-kernel.git] / drivers / video / da8xx-fb.c
1 /*
2  * Copyright (C) 2008-2009 MontaVista Software Inc.
3  * Copyright (C) 2008-2009 Texas Instruments Inc
4  *
5  * Based on the LCD driver for TI Avalanche processors written by
6  * Ajay Singh and Shalom Hai.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option)any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21  */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/fb.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/interrupt.h>
30 #include <linux/clk.h>
31 #include <linux/cpufreq.h>
32 #include <linux/console.h>
33 #include <linux/slab.h>
34 #include <video/da8xx-fb.h>
36 #define DRIVER_NAME "da8xx_lcdc"
38 #define LCD_VERSION_1   1
39 #define LCD_VERSION_2   2
41 /* LCD Status Register */
42 #define LCD_END_OF_FRAME1               BIT(9)
43 #define LCD_END_OF_FRAME0               BIT(8)
44 #define LCD_PL_LOAD_DONE                BIT(6)
45 #define LCD_FIFO_UNDERFLOW              BIT(5)
46 #define LCD_SYNC_LOST                   BIT(2)
48 /* LCD DMA Control Register */
49 #define LCD_DMA_BURST_SIZE(x)           ((x) << 4)
50 #define LCD_DMA_BURST_1                 0x0
51 #define LCD_DMA_BURST_2                 0x1
52 #define LCD_DMA_BURST_4                 0x2
53 #define LCD_DMA_BURST_8                 0x3
54 #define LCD_DMA_BURST_16                0x4
55 #define LCD_V1_END_OF_FRAME_INT_ENA     BIT(2)
56 #define LCD_V2_END_OF_FRAME0_INT_ENA    BIT(8)
57 #define LCD_V2_END_OF_FRAME1_INT_ENA    BIT(9)
58 #define LCD_DUAL_FRAME_BUFFER_ENABLE    BIT(0)
60 /* LCD Control Register */
61 #define LCD_CLK_DIVISOR(x)              ((x) << 8)
62 #define LCD_RASTER_MODE                 0x01
64 /* LCD Raster Control Register */
65 #define LCD_PALETTE_LOAD_MODE(x)        ((x) << 20)
66 #define PALETTE_AND_DATA                0x00
67 #define PALETTE_ONLY                    0x01
68 #define DATA_ONLY                       0x02
70 #define LCD_MONO_8BIT_MODE              BIT(9)
71 #define LCD_RASTER_ORDER                BIT(8)
72 #define LCD_TFT_MODE                    BIT(7)
73 #define LCD_V1_UNDERFLOW_INT_ENA        BIT(6)
74 #define LCD_V2_UNDERFLOW_INT_ENA        BIT(5)
75 #define LCD_V1_PL_INT_ENA               BIT(4)
76 #define LCD_V2_PL_INT_ENA               BIT(6)
77 #define LCD_MONOCHROME_MODE             BIT(1)
78 #define LCD_RASTER_ENABLE               BIT(0)
79 #define LCD_TFT_ALT_ENABLE              BIT(23)
80 #define LCD_STN_565_ENABLE              BIT(24)
81 #define LCD_V2_DMA_CLK_EN               BIT(2)
82 #define LCD_V2_LIDD_CLK_EN              BIT(1)
83 #define LCD_V2_CORE_CLK_EN              BIT(0)
84 #define LCD_V2_LPP_B10                  26
86 /* LCD Raster Timing 2 Register */
87 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
88 #define LCD_AC_BIAS_FREQUENCY(x)                ((x) << 8)
89 #define LCD_SYNC_CTRL                           BIT(25)
90 #define LCD_SYNC_EDGE                           BIT(24)
91 #define LCD_INVERT_PIXEL_CLOCK                  BIT(22)
92 #define LCD_INVERT_LINE_CLOCK                   BIT(21)
93 #define LCD_INVERT_FRAME_CLOCK                  BIT(20)
95 /* LCD Block */
96 #define  LCD_PID_REG                            0x0
97 #define  LCD_CTRL_REG                           0x4
98 #define  LCD_STAT_REG                           0x8
99 #define  LCD_RASTER_CTRL_REG                    0x28
100 #define  LCD_RASTER_TIMING_0_REG                0x2C
101 #define  LCD_RASTER_TIMING_1_REG                0x30
102 #define  LCD_RASTER_TIMING_2_REG                0x34
103 #define  LCD_DMA_CTRL_REG                       0x40
104 #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG        0x44
105 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG     0x48
106 #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG        0x4C
107 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG     0x50
109 /* Interrupt Registers available only in Version 2 */
110 #define  LCD_RAW_STAT_REG                       0x58
111 #define  LCD_MASKED_STAT_REG                    0x5c
112 #define  LCD_INT_ENABLE_SET_REG                 0x60
113 #define  LCD_INT_ENABLE_CLR_REG                 0x64
114 #define  LCD_END_OF_INT_IND_REG                 0x68
116 /* Clock registers available only on Version 2 */
117 #define  LCD_CLK_ENABLE_REG                     0x6c
118 #define  LCD_CLK_RESET_REG                      0x70
120 #define LCD_NUM_BUFFERS 2
122 #define WSI_TIMEOUT     50
123 #define PALETTE_SIZE    256
124 #define LEFT_MARGIN     64
125 #define RIGHT_MARGIN    64
126 #define UPPER_MARGIN    32
127 #define LOWER_MARGIN    32
129 static resource_size_t da8xx_fb_reg_base;
130 static struct resource *lcdc_regs;
131 static unsigned int lcd_revision;
132 static irq_handler_t lcdc_irq_handler;
134 static inline unsigned int lcdc_read(unsigned int addr)
136         return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
139 static inline void lcdc_write(unsigned int val, unsigned int addr)
141         __raw_writel(val, da8xx_fb_reg_base + (addr));
144 struct da8xx_fb_par {
145         resource_size_t p_palette_base;
146         unsigned char *v_palette_base;
147         dma_addr_t              vram_phys;
148         unsigned long           vram_size;
149         void                    *vram_virt;
150         unsigned int            dma_start;
151         unsigned int            dma_end;
152         struct clk *lcdc_clk;
153         int irq;
154         unsigned short pseudo_palette[16];
155         unsigned int palette_sz;
156         unsigned int pxl_clk;
157         int blank;
158         wait_queue_head_t       vsync_wait;
159         int                     vsync_flag;
160         int                     vsync_timeout;
161 #ifdef CONFIG_CPU_FREQ
162         struct notifier_block   freq_transition;
163 #endif
164         void (*panel_power_ctrl)(int);
165 };
167 /* Variable Screen Information */
168 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
169         .xoffset = 0,
170         .yoffset = 0,
171         .transp = {0, 0, 0},
172         .nonstd = 0,
173         .activate = 0,
174         .height = -1,
175         .width = -1,
176         .pixclock = 46666,      /* 46us - AUO display */
177         .accel_flags = 0,
178         .left_margin = LEFT_MARGIN,
179         .right_margin = RIGHT_MARGIN,
180         .upper_margin = UPPER_MARGIN,
181         .lower_margin = LOWER_MARGIN,
182         .sync = 0,
183         .vmode = FB_VMODE_NONINTERLACED
184 };
186 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
187         .id = "DA8xx FB Drv",
188         .type = FB_TYPE_PACKED_PIXELS,
189         .type_aux = 0,
190         .visual = FB_VISUAL_PSEUDOCOLOR,
191         .xpanstep = 0,
192         .ypanstep = 1,
193         .ywrapstep = 0,
194         .accel = FB_ACCEL_NONE
195 };
197 struct da8xx_panel {
198         const char      name[25];       /* Full name <vendor>_<model> */
199         unsigned short  width;
200         unsigned short  height;
201         int             hfp;            /* Horizontal front porch */
202         int             hbp;            /* Horizontal back porch */
203         int             hsw;            /* Horizontal Sync Pulse Width */
204         int             vfp;            /* Vertical front porch */
205         int             vbp;            /* Vertical back porch */
206         int             vsw;            /* Vertical Sync Pulse Width */
207         unsigned int    pxl_clk;        /* Pixel clock */
208         unsigned char   invert_pxl_clk; /* Invert Pixel clock */
209 };
211 static struct da8xx_panel known_lcd_panels[] = {
212         /* Sharp LCD035Q3DG01 */
213         [0] = {
214                 .name = "Sharp_LCD035Q3DG01",
215                 .width = 320,
216                 .height = 240,
217                 .hfp = 8,
218                 .hbp = 6,
219                 .hsw = 0,
220                 .vfp = 2,
221                 .vbp = 2,
222                 .vsw = 0,
223                 .pxl_clk = 4608000,
224                 .invert_pxl_clk = 1,
225         },
226         /* Sharp LK043T1DG01 */
227         [1] = {
228                 .name = "Sharp_LK043T1DG01",
229                 .width = 480,
230                 .height = 272,
231                 .hfp = 2,
232                 .hbp = 2,
233                 .hsw = 41,
234                 .vfp = 2,
235                 .vbp = 2,
236                 .vsw = 10,
237                 .pxl_clk = 7833600,
238                 .invert_pxl_clk = 0,
239         },
240 };
242 /* Enable the Raster Engine of the LCD Controller */
243 static inline void lcd_enable_raster(void)
245         u32 reg;
247         reg = lcdc_read(LCD_RASTER_CTRL_REG);
248         if (!(reg & LCD_RASTER_ENABLE))
249                 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
252 /* Disable the Raster Engine of the LCD Controller */
253 static inline void lcd_disable_raster(void)
255         u32 reg;
257         reg = lcdc_read(LCD_RASTER_CTRL_REG);
258         if (reg & LCD_RASTER_ENABLE)
259                 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
262 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
264         u32 start;
265         u32 end;
266         u32 reg_ras;
267         u32 reg_dma;
268         u32 reg_int;
270         /* init reg to clear PLM (loading mode) fields */
271         reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
272         reg_ras &= ~(3 << 20);
274         reg_dma  = lcdc_read(LCD_DMA_CTRL_REG);
276         if (load_mode == LOAD_DATA) {
277                 start    = par->dma_start;
278                 end      = par->dma_end;
280                 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
281                 if (lcd_revision == LCD_VERSION_1) {
282                         reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
283                 } else {
284                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
285                                 LCD_V2_END_OF_FRAME0_INT_ENA |
286                                 LCD_V2_END_OF_FRAME1_INT_ENA;
287                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
288                 }
289                 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
291                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
292                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
293                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
294                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
295         } else if (load_mode == LOAD_PALETTE) {
296                 start    = par->p_palette_base;
297                 end      = start + par->palette_sz - 1;
299                 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
301                 if (lcd_revision == LCD_VERSION_1) {
302                         reg_ras |= LCD_V1_PL_INT_ENA;
303                 } else {
304                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
305                                 LCD_V2_PL_INT_ENA;
306                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
307                 }
309                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
310                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
311         }
313         lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
314         lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
316         /*
317          * The Raster enable bit must be set after all other control fields are
318          * set.
319          */
320         lcd_enable_raster();
323 /* Configure the Burst Size of DMA */
324 static int lcd_cfg_dma(int burst_size)
326         u32 reg;
328         reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
329         switch (burst_size) {
330         case 1:
331                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
332                 break;
333         case 2:
334                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
335                 break;
336         case 4:
337                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
338                 break;
339         case 8:
340                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
341                 break;
342         case 16:
343                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
344                 break;
345         default:
346                 return -EINVAL;
347         }
348         lcdc_write(reg, LCD_DMA_CTRL_REG);
350         return 0;
353 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
355         u32 reg;
357         /* Set the AC Bias Period and Number of Transisitons per Interrupt */
358         reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
359         reg |= LCD_AC_BIAS_FREQUENCY(period) |
360                 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
361         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
364 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
365                 int front_porch)
367         u32 reg;
369         reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
370         reg |= ((back_porch & 0xff) << 24)
371             | ((front_porch & 0xff) << 16)
372             | ((pulse_width & 0x3f) << 10);
373         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
376 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
377                 int front_porch)
379         u32 reg;
381         reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
382         reg |= ((back_porch & 0xff) << 24)
383             | ((front_porch & 0xff) << 16)
384             | ((pulse_width & 0x3f) << 10);
385         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
388 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
390         u32 reg;
391         u32 reg_int;
393         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
394                                                 LCD_MONO_8BIT_MODE |
395                                                 LCD_MONOCHROME_MODE);
397         switch (cfg->p_disp_panel->panel_shade) {
398         case MONOCHROME:
399                 reg |= LCD_MONOCHROME_MODE;
400                 if (cfg->mono_8bit_mode)
401                         reg |= LCD_MONO_8BIT_MODE;
402                 break;
403         case COLOR_ACTIVE:
404                 reg |= LCD_TFT_MODE;
405                 if (cfg->tft_alt_mode)
406                         reg |= LCD_TFT_ALT_ENABLE;
407                 break;
409         case COLOR_PASSIVE:
410                 if (cfg->stn_565_mode)
411                         reg |= LCD_STN_565_ENABLE;
412                 break;
414         default:
415                 return -EINVAL;
416         }
418         /* enable additional interrupts here */
419         if (lcd_revision == LCD_VERSION_1) {
420                 reg |= LCD_V1_UNDERFLOW_INT_ENA;
421         } else {
422                 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
423                         LCD_V2_UNDERFLOW_INT_ENA;
424                 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
425         }
427         lcdc_write(reg, LCD_RASTER_CTRL_REG);
429         reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
431         if (cfg->sync_ctrl)
432                 reg |= LCD_SYNC_CTRL;
433         else
434                 reg &= ~LCD_SYNC_CTRL;
436         if (cfg->sync_edge)
437                 reg |= LCD_SYNC_EDGE;
438         else
439                 reg &= ~LCD_SYNC_EDGE;
441         if (cfg->invert_line_clock)
442                 reg |= LCD_INVERT_LINE_CLOCK;
443         else
444                 reg &= ~LCD_INVERT_LINE_CLOCK;
446         if (cfg->invert_frm_clock)
447                 reg |= LCD_INVERT_FRAME_CLOCK;
448         else
449                 reg &= ~LCD_INVERT_FRAME_CLOCK;
451         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
453         return 0;
456 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
457                 u32 bpp, u32 raster_order)
459         u32 reg;
461         /* Set the Panel Width */
462         /* Pixels per line = (PPL + 1)*16 */
463         if (lcd_revision == LCD_VERSION_1) {
464                 /*
465                  * 0x3F in bits 4..9 gives max horizontal resolution = 1024
466                  * pixels.
467                  */
468                 width &= 0x3f0;
469         } else {
470                 /*
471                  * 0x7F in bits 4..10 gives max horizontal resolution = 2048
472                  * pixels.
473                  */
474                 width &= 0x7f0;
475         }
477         reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
478         reg &= 0xfffffc00;
479         if (lcd_revision == LCD_VERSION_1) {
480                 reg |= ((width >> 4) - 1) << 4;
481         } else {
482                 width = (width >> 4) - 1;
483                 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
484         }
485         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
487         /* Set the Panel Height */
488         /* Set bits 9:0 of Lines Per Pixel */
489         reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
490         reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
491         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
493         /* Set bit 10 of Lines Per Pixel */
494         if (lcd_revision == LCD_VERSION_2) {
495                 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
496                 reg |= ((height - 1) & 0x400) << 16;
497                 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
498         }
500         /* Set the Raster Order of the Frame Buffer */
501         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
502         if (raster_order)
503                 reg |= LCD_RASTER_ORDER;
504         lcdc_write(reg, LCD_RASTER_CTRL_REG);
506         switch (bpp) {
507         case 1:
508         case 2:
509         case 4:
510         case 16:
511                 par->palette_sz = 16 * 2;
512                 break;
514         case 8:
515                 par->palette_sz = 256 * 2;
516                 break;
518         default:
519                 return -EINVAL;
520         }
522         return 0;
525 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
526                               unsigned blue, unsigned transp,
527                               struct fb_info *info)
529         struct da8xx_fb_par *par = info->par;
530         unsigned short *palette = (unsigned short *) par->v_palette_base;
531         u_short pal;
532         int update_hw = 0;
534         if (regno > 255)
535                 return 1;
537         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
538                 return 1;
540         if (info->var.bits_per_pixel == 8) {
541                 red >>= 4;
542                 green >>= 8;
543                 blue >>= 12;
545                 pal = (red & 0x0f00);
546                 pal |= (green & 0x00f0);
547                 pal |= (blue & 0x000f);
549                 if (palette[regno] != pal) {
550                         update_hw = 1;
551                         palette[regno] = pal;
552                 }
553         } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
554                 red >>= (16 - info->var.red.length);
555                 red <<= info->var.red.offset;
557                 green >>= (16 - info->var.green.length);
558                 green <<= info->var.green.offset;
560                 blue >>= (16 - info->var.blue.length);
561                 blue <<= info->var.blue.offset;
563                 par->pseudo_palette[regno] = red | green | blue;
565                 if (palette[0] != 0x4000) {
566                         update_hw = 1;
567                         palette[0] = 0x4000;
568                 }
569         }
571         /* Update the palette in the h/w as needed. */
572         if (update_hw)
573                 lcd_blit(LOAD_PALETTE, par);
575         return 0;
578 static void lcd_reset(struct da8xx_fb_par *par)
580         /* Disable the Raster if previously Enabled */
581         lcd_disable_raster();
583         /* DMA has to be disabled */
584         lcdc_write(0, LCD_DMA_CTRL_REG);
585         lcdc_write(0, LCD_RASTER_CTRL_REG);
587         if (lcd_revision == LCD_VERSION_2)
588                 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
591 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
593         unsigned int lcd_clk, div;
595         lcd_clk = clk_get_rate(par->lcdc_clk);
596         div = lcd_clk / par->pxl_clk;
598         /* Configure the LCD clock divisor. */
599         lcdc_write(LCD_CLK_DIVISOR(div) |
600                         (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
602         if (lcd_revision == LCD_VERSION_2)
603                 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
604                                 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
608 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
609                 struct da8xx_panel *panel)
611         u32 bpp;
612         int ret = 0;
614         lcd_reset(par);
616         /* Calculate the divider */
617         lcd_calc_clk_divider(par);
619         if (panel->invert_pxl_clk)
620                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
621                         LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
622         else
623                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
624                         ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
626         /* Configure the DMA burst size. */
627         ret = lcd_cfg_dma(cfg->dma_burst_sz);
628         if (ret < 0)
629                 return ret;
631         /* Configure the AC bias properties. */
632         lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
634         /* Configure the vertical and horizontal sync properties. */
635         lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
636         lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
638         /* Configure for disply */
639         ret = lcd_cfg_display(cfg);
640         if (ret < 0)
641                 return ret;
643         if (QVGA != cfg->p_disp_panel->panel_type)
644                 return -EINVAL;
646         if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
647             cfg->bpp >= cfg->p_disp_panel->min_bpp)
648                 bpp = cfg->bpp;
649         else
650                 bpp = cfg->p_disp_panel->max_bpp;
651         if (bpp == 12)
652                 bpp = 16;
653         ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
654                                 (unsigned int)panel->height, bpp,
655                                 cfg->raster_order);
656         if (ret < 0)
657                 return ret;
659         /* Configure FDD */
660         lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
661                        (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
663         return 0;
666 /* IRQ handler for version 2 of LCDC */
667 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
669         struct da8xx_fb_par *par = arg;
670         u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
671         u32 reg_int;
673         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
674                 lcd_disable_raster();
675                 lcdc_write(stat, LCD_MASKED_STAT_REG);
676                 lcd_enable_raster();
677         } else if (stat & LCD_PL_LOAD_DONE) {
678                 /*
679                  * Must disable raster before changing state of any control bit.
680                  * And also must be disabled before clearing the PL loading
681                  * interrupt via the following write to the status register. If
682                  * this is done after then one gets multiple PL done interrupts.
683                  */
684                 lcd_disable_raster();
686                 lcdc_write(stat, LCD_MASKED_STAT_REG);
688                 /* Disable PL completion inerrupt */
689                 reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |
690                        (LCD_V2_PL_INT_ENA);
691                 lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);
693                 /* Setup and start data loading mode */
694                 lcd_blit(LOAD_DATA, par);
695         } else {
696                 lcdc_write(stat, LCD_MASKED_STAT_REG);
698                 if (stat & LCD_END_OF_FRAME0) {
699                         lcdc_write(par->dma_start,
700                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
701                         lcdc_write(par->dma_end,
702                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
703                         par->vsync_flag = 1;
704                         wake_up_interruptible(&par->vsync_wait);
705                 }
707                 if (stat & LCD_END_OF_FRAME1) {
708                         lcdc_write(par->dma_start,
709                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
710                         lcdc_write(par->dma_end,
711                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
712                         par->vsync_flag = 1;
713                         wake_up_interruptible(&par->vsync_wait);
714                 }
715         }
717         lcdc_write(0, LCD_END_OF_INT_IND_REG);
718         return IRQ_HANDLED;
721 /* IRQ handler for version 1 LCDC */
722 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
724         struct da8xx_fb_par *par = arg;
725         u32 stat = lcdc_read(LCD_STAT_REG);
726         u32 reg_ras;
728         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
729                 lcd_disable_raster();
730                 lcdc_write(stat, LCD_STAT_REG);
731                 lcd_enable_raster();
732         } else if (stat & LCD_PL_LOAD_DONE) {
733                 /*
734                  * Must disable raster before changing state of any control bit.
735                  * And also must be disabled before clearing the PL loading
736                  * interrupt via the following write to the status register. If
737                  * this is done after then one gets multiple PL done interrupts.
738                  */
739                 lcd_disable_raster();
741                 lcdc_write(stat, LCD_STAT_REG);
743                 /* Disable PL completion inerrupt */
744                 reg_ras  = lcdc_read(LCD_RASTER_CTRL_REG);
745                 reg_ras &= ~LCD_V1_PL_INT_ENA;
746                 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
748                 /* Setup and start data loading mode */
749                 lcd_blit(LOAD_DATA, par);
750         } else {
751                 lcdc_write(stat, LCD_STAT_REG);
753                 if (stat & LCD_END_OF_FRAME0) {
754                         lcdc_write(par->dma_start,
755                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
756                         lcdc_write(par->dma_end,
757                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
758                         par->vsync_flag = 1;
759                         wake_up_interruptible(&par->vsync_wait);
760                 }
762                 if (stat & LCD_END_OF_FRAME1) {
763                         lcdc_write(par->dma_start,
764                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
765                         lcdc_write(par->dma_end,
766                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
767                         par->vsync_flag = 1;
768                         wake_up_interruptible(&par->vsync_wait);
769                 }
770         }
772         return IRQ_HANDLED;
775 static int fb_check_var(struct fb_var_screeninfo *var,
776                         struct fb_info *info)
778         int err = 0;
780         switch (var->bits_per_pixel) {
781         case 1:
782         case 8:
783                 var->red.offset = 0;
784                 var->red.length = 8;
785                 var->green.offset = 0;
786                 var->green.length = 8;
787                 var->blue.offset = 0;
788                 var->blue.length = 8;
789                 var->transp.offset = 0;
790                 var->transp.length = 0;
791                 break;
792         case 4:
793                 var->red.offset = 0;
794                 var->red.length = 4;
795                 var->green.offset = 0;
796                 var->green.length = 4;
797                 var->blue.offset = 0;
798                 var->blue.length = 4;
799                 var->transp.offset = 0;
800                 var->transp.length = 0;
801                 break;
802         case 16:                /* RGB 565 */
803                 var->red.offset = 11;
804                 var->red.length = 5;
805                 var->green.offset = 5;
806                 var->green.length = 6;
807                 var->blue.offset = 0;
808                 var->blue.length = 5;
809                 var->transp.offset = 0;
810                 var->transp.length = 0;
811                 break;
812         default:
813                 err = -EINVAL;
814         }
816         var->red.msb_right = 0;
817         var->green.msb_right = 0;
818         var->blue.msb_right = 0;
819         var->transp.msb_right = 0;
820         return err;
823 #ifdef CONFIG_CPU_FREQ
824 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
825                                      unsigned long val, void *data)
827         struct da8xx_fb_par *par;
829         par = container_of(nb, struct da8xx_fb_par, freq_transition);
830         if (val == CPUFREQ_PRECHANGE) {
831                 lcd_disable_raster();
832         } else if (val == CPUFREQ_POSTCHANGE) {
833                 lcd_calc_clk_divider(par);
834                 lcd_enable_raster();
835         }
837         return 0;
840 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
842         par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
844         return cpufreq_register_notifier(&par->freq_transition,
845                                          CPUFREQ_TRANSITION_NOTIFIER);
848 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
850         cpufreq_unregister_notifier(&par->freq_transition,
851                                     CPUFREQ_TRANSITION_NOTIFIER);
853 #endif
855 static int __devexit fb_remove(struct platform_device *dev)
857         struct fb_info *info = dev_get_drvdata(&dev->dev);
859         if (info) {
860                 struct da8xx_fb_par *par = info->par;
862 #ifdef CONFIG_CPU_FREQ
863                 lcd_da8xx_cpufreq_deregister(par);
864 #endif
865                 if (par->panel_power_ctrl)
866                         par->panel_power_ctrl(0);
868                 lcd_disable_raster();
869                 lcdc_write(0, LCD_RASTER_CTRL_REG);
871                 /* disable DMA  */
872                 lcdc_write(0, LCD_DMA_CTRL_REG);
874                 unregister_framebuffer(info);
875                 fb_dealloc_cmap(&info->cmap);
876                 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
877                                   par->p_palette_base);
878                 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
879                                   par->vram_phys);
880                 free_irq(par->irq, par);
881                 clk_disable(par->lcdc_clk);
882                 clk_put(par->lcdc_clk);
883                 framebuffer_release(info);
884                 iounmap((void __iomem *)da8xx_fb_reg_base);
885                 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
887         }
888         return 0;
891 /*
892  * Function to wait for vertical sync which for this LCD peripheral
893  * translates into waiting for the current raster frame to complete.
894  */
895 static int fb_wait_for_vsync(struct fb_info *info)
897         struct da8xx_fb_par *par = info->par;
898         int ret;
900         /*
901          * Set flag to 0 and wait for isr to set to 1. It would seem there is a
902          * race condition here where the ISR could have occurred just before or
903          * just after this set. But since we are just coarsely waiting for
904          * a frame to complete then that's OK. i.e. if the frame completed
905          * just before this code executed then we have to wait another full
906          * frame time but there is no way to avoid such a situation. On the
907          * other hand if the frame completed just after then we don't need
908          * to wait long at all. Either way we are guaranteed to return to the
909          * user immediately after a frame completion which is all that is
910          * required.
911          */
912         par->vsync_flag = 0;
913         ret = wait_event_interruptible_timeout(par->vsync_wait,
914                                                par->vsync_flag != 0,
915                                                par->vsync_timeout);
916         if (ret < 0)
917                 return ret;
918         if (ret == 0)
919                 return -ETIMEDOUT;
921         return 0;
924 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
925                           unsigned long arg)
927         struct lcd_sync_arg sync_arg;
929         switch (cmd) {
930         case FBIOGET_CONTRAST:
931         case FBIOPUT_CONTRAST:
932         case FBIGET_BRIGHTNESS:
933         case FBIPUT_BRIGHTNESS:
934         case FBIGET_COLOR:
935         case FBIPUT_COLOR:
936                 return -ENOTTY;
937         case FBIPUT_HSYNC:
938                 if (copy_from_user(&sync_arg, (char *)arg,
939                                 sizeof(struct lcd_sync_arg)))
940                         return -EFAULT;
941                 lcd_cfg_horizontal_sync(sync_arg.back_porch,
942                                         sync_arg.pulse_width,
943                                         sync_arg.front_porch);
944                 break;
945         case FBIPUT_VSYNC:
946                 if (copy_from_user(&sync_arg, (char *)arg,
947                                 sizeof(struct lcd_sync_arg)))
948                         return -EFAULT;
949                 lcd_cfg_vertical_sync(sync_arg.back_porch,
950                                         sync_arg.pulse_width,
951                                         sync_arg.front_porch);
952                 break;
953         case FBIO_WAITFORVSYNC:
954                 return fb_wait_for_vsync(info);
955         default:
956                 return -EINVAL;
957         }
958         return 0;
961 static int cfb_blank(int blank, struct fb_info *info)
963         struct da8xx_fb_par *par = info->par;
964         int ret = 0;
966         if (par->blank == blank)
967                 return 0;
969         par->blank = blank;
970         switch (blank) {
971         case FB_BLANK_UNBLANK:
972                 if (par->panel_power_ctrl)
973                         par->panel_power_ctrl(1);
975                 lcd_enable_raster();
976                 break;
977         case FB_BLANK_POWERDOWN:
978                 if (par->panel_power_ctrl)
979                         par->panel_power_ctrl(0);
981                 lcd_disable_raster();
982                 break;
983         default:
984                 ret = -EINVAL;
985         }
987         return ret;
990 /*
991  * Set new x,y offsets in the virtual display for the visible area and switch
992  * to the new mode.
993  */
994 static int da8xx_pan_display(struct fb_var_screeninfo *var,
995                              struct fb_info *fbi)
997         int ret = 0;
998         struct fb_var_screeninfo new_var;
999         struct da8xx_fb_par         *par = fbi->par;
1000         struct fb_fix_screeninfo    *fix = &fbi->fix;
1001         unsigned int end;
1002         unsigned int start;
1004         if (var->xoffset != fbi->var.xoffset ||
1005                         var->yoffset != fbi->var.yoffset) {
1006                 memcpy(&new_var, &fbi->var, sizeof(new_var));
1007                 new_var.xoffset = var->xoffset;
1008                 new_var.yoffset = var->yoffset;
1009                 if (fb_check_var(&new_var, fbi))
1010                         ret = -EINVAL;
1011                 else {
1012                         memcpy(&fbi->var, &new_var, sizeof(new_var));
1014                         start   = fix->smem_start +
1015                                 new_var.yoffset * fix->line_length +
1016                                 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1017                         end     = start + fbi->var.yres * fix->line_length - 1;
1018                         par->dma_start  = start;
1019                         par->dma_end    = end;
1020                 }
1021         }
1023         return ret;
1026 static struct fb_ops da8xx_fb_ops = {
1027         .owner = THIS_MODULE,
1028         .fb_check_var = fb_check_var,
1029         .fb_setcolreg = fb_setcolreg,
1030         .fb_pan_display = da8xx_pan_display,
1031         .fb_ioctl = fb_ioctl,
1032         .fb_fillrect = cfb_fillrect,
1033         .fb_copyarea = cfb_copyarea,
1034         .fb_imageblit = cfb_imageblit,
1035         .fb_blank = cfb_blank,
1036 };
1038 static int __devinit fb_probe(struct platform_device *device)
1040         struct da8xx_lcdc_platform_data *fb_pdata =
1041                                                 device->dev.platform_data;
1042         struct lcd_ctrl_config *lcd_cfg;
1043         struct da8xx_panel *lcdc_info;
1044         struct fb_info *da8xx_fb_info;
1045         struct clk *fb_clk = NULL;
1046         struct da8xx_fb_par *par;
1047         resource_size_t len;
1048         int ret, i;
1050         if (fb_pdata == NULL) {
1051                 dev_err(&device->dev, "Can not get platform data\n");
1052                 return -ENOENT;
1053         }
1055         lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1056         if (!lcdc_regs) {
1057                 dev_err(&device->dev,
1058                         "Can not get memory resource for LCD controller\n");
1059                 return -ENOENT;
1060         }
1062         len = resource_size(lcdc_regs);
1064         lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
1065         if (!lcdc_regs)
1066                 return -EBUSY;
1068         da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
1069         if (!da8xx_fb_reg_base) {
1070                 ret = -EBUSY;
1071                 goto err_request_mem;
1072         }
1074         fb_clk = clk_get(&device->dev, NULL);
1075         if (IS_ERR(fb_clk)) {
1076                 dev_err(&device->dev, "Can not get device clock\n");
1077                 ret = -ENODEV;
1078                 goto err_ioremap;
1079         }
1080         ret = clk_enable(fb_clk);
1081         if (ret)
1082                 goto err_clk_put;
1084         /* Determine LCD IP Version */
1085         switch (lcdc_read(LCD_PID_REG)) {
1086         case 0x4C100102:
1087                 lcd_revision = LCD_VERSION_1;
1088                 break;
1089         case 0x4F200800:
1090                 lcd_revision = LCD_VERSION_2;
1091                 break;
1092         default:
1093                 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1094                                 "defaulting to LCD revision 1\n",
1095                                 lcdc_read(LCD_PID_REG));
1096                 lcd_revision = LCD_VERSION_1;
1097                 break;
1098         }
1100         for (i = 0, lcdc_info = known_lcd_panels;
1101                 i < ARRAY_SIZE(known_lcd_panels);
1102                 i++, lcdc_info++) {
1103                 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1104                         break;
1105         }
1107         if (i == ARRAY_SIZE(known_lcd_panels)) {
1108                 dev_err(&device->dev, "GLCD: No valid panel found\n");
1109                 ret = -ENODEV;
1110                 goto err_clk_disable;
1111         } else
1112                 dev_info(&device->dev, "GLCD: Found %s panel\n",
1113                                         fb_pdata->type);
1115         lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1117         da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1118                                         &device->dev);
1119         if (!da8xx_fb_info) {
1120                 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1121                 ret = -ENOMEM;
1122                 goto err_clk_disable;
1123         }
1125         par = da8xx_fb_info->par;
1126         par->lcdc_clk = fb_clk;
1127         par->pxl_clk = lcdc_info->pxl_clk;
1128         if (fb_pdata->panel_power_ctrl) {
1129                 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1130                 par->panel_power_ctrl(1);
1131         }
1133         if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
1134                 dev_err(&device->dev, "lcd_init failed\n");
1135                 ret = -EFAULT;
1136                 goto err_release_fb;
1137         }
1139         /* allocate frame buffer */
1140         par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
1141         par->vram_size = PAGE_ALIGN(par->vram_size/8);
1142         par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1144         par->vram_virt = dma_alloc_coherent(NULL,
1145                                             par->vram_size,
1146                                             (resource_size_t *) &par->vram_phys,
1147                                             GFP_KERNEL | GFP_DMA);
1148         if (!par->vram_virt) {
1149                 dev_err(&device->dev,
1150                         "GLCD: kmalloc for frame buffer failed\n");
1151                 ret = -EINVAL;
1152                 goto err_release_fb;
1153         }
1155         da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1156         da8xx_fb_fix.smem_start    = par->vram_phys;
1157         da8xx_fb_fix.smem_len      = par->vram_size;
1158         da8xx_fb_fix.line_length   = (lcdc_info->width * lcd_cfg->bpp) / 8;
1160         par->dma_start = par->vram_phys;
1161         par->dma_end   = par->dma_start + lcdc_info->height *
1162                 da8xx_fb_fix.line_length - 1;
1164         /* allocate palette buffer */
1165         par->v_palette_base = dma_alloc_coherent(NULL,
1166                                                PALETTE_SIZE,
1167                                                (resource_size_t *)
1168                                                &par->p_palette_base,
1169                                                GFP_KERNEL | GFP_DMA);
1170         if (!par->v_palette_base) {
1171                 dev_err(&device->dev,
1172                         "GLCD: kmalloc for palette buffer failed\n");
1173                 ret = -EINVAL;
1174                 goto err_release_fb_mem;
1175         }
1176         memset(par->v_palette_base, 0, PALETTE_SIZE);
1178         par->irq = platform_get_irq(device, 0);
1179         if (par->irq < 0) {
1180                 ret = -ENOENT;
1181                 goto err_release_pl_mem;
1182         }
1184         /* Initialize par */
1185         da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
1187         da8xx_fb_var.xres = lcdc_info->width;
1188         da8xx_fb_var.xres_virtual = lcdc_info->width;
1190         da8xx_fb_var.yres         = lcdc_info->height;
1191         da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
1193         da8xx_fb_var.grayscale =
1194             lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
1195         da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1197         da8xx_fb_var.hsync_len = lcdc_info->hsw;
1198         da8xx_fb_var.vsync_len = lcdc_info->vsw;
1200         /* Initialize fbinfo */
1201         da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1202         da8xx_fb_info->fix = da8xx_fb_fix;
1203         da8xx_fb_info->var = da8xx_fb_var;
1204         da8xx_fb_info->fbops = &da8xx_fb_ops;
1205         da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1206         da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1207                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1209         ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1210         if (ret)
1211                 goto err_release_pl_mem;
1212         da8xx_fb_info->cmap.len = par->palette_sz;
1214         /* initialize var_screeninfo */
1215         da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1216         fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1218         dev_set_drvdata(&device->dev, da8xx_fb_info);
1220         /* initialize the vsync wait queue */
1221         init_waitqueue_head(&par->vsync_wait);
1222         par->vsync_timeout = HZ / 5;
1224         /* Register the Frame Buffer  */
1225         if (register_framebuffer(da8xx_fb_info) < 0) {
1226                 dev_err(&device->dev,
1227                         "GLCD: Frame Buffer Registration Failed!\n");
1228                 ret = -EINVAL;
1229                 goto err_dealloc_cmap;
1230         }
1232 #ifdef CONFIG_CPU_FREQ
1233         ret = lcd_da8xx_cpufreq_register(par);
1234         if (ret) {
1235                 dev_err(&device->dev, "failed to register cpufreq\n");
1236                 goto err_cpu_freq;
1237         }
1238 #endif
1240         if (lcd_revision == LCD_VERSION_1)
1241                 lcdc_irq_handler = lcdc_irq_handler_rev01;
1242         else
1243                 lcdc_irq_handler = lcdc_irq_handler_rev02;
1245         ret = request_irq(par->irq, lcdc_irq_handler, 0,
1246                         DRIVER_NAME, par);
1247         if (ret)
1248                 goto irq_freq;
1249         return 0;
1251 irq_freq:
1252 #ifdef CONFIG_CPU_FREQ
1253         lcd_da8xx_cpufreq_deregister(par);
1254 #endif
1255 err_cpu_freq:
1256         unregister_framebuffer(da8xx_fb_info);
1258 err_dealloc_cmap:
1259         fb_dealloc_cmap(&da8xx_fb_info->cmap);
1261 err_release_pl_mem:
1262         dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1263                           par->p_palette_base);
1265 err_release_fb_mem:
1266         dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1268 err_release_fb:
1269         framebuffer_release(da8xx_fb_info);
1271 err_clk_disable:
1272         clk_disable(fb_clk);
1274 err_clk_put:
1275         clk_put(fb_clk);
1277 err_ioremap:
1278         iounmap((void __iomem *)da8xx_fb_reg_base);
1280 err_request_mem:
1281         release_mem_region(lcdc_regs->start, len);
1283         return ret;
1286 #ifdef CONFIG_PM
1287 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1289         struct fb_info *info = platform_get_drvdata(dev);
1290         struct da8xx_fb_par *par = info->par;
1292         console_lock();
1293         if (par->panel_power_ctrl)
1294                 par->panel_power_ctrl(0);
1296         fb_set_suspend(info, 1);
1297         lcd_disable_raster();
1298         clk_disable(par->lcdc_clk);
1299         console_unlock();
1301         return 0;
1303 static int fb_resume(struct platform_device *dev)
1305         struct fb_info *info = platform_get_drvdata(dev);
1306         struct da8xx_fb_par *par = info->par;
1308         console_lock();
1309         if (par->panel_power_ctrl)
1310                 par->panel_power_ctrl(1);
1312         clk_enable(par->lcdc_clk);
1313         lcd_enable_raster();
1314         fb_set_suspend(info, 0);
1315         console_unlock();
1317         return 0;
1319 #else
1320 #define fb_suspend NULL
1321 #define fb_resume NULL
1322 #endif
1324 static struct platform_driver da8xx_fb_driver = {
1325         .probe = fb_probe,
1326         .remove = __devexit_p(fb_remove),
1327         .suspend = fb_suspend,
1328         .resume = fb_resume,
1329         .driver = {
1330                    .name = DRIVER_NAME,
1331                    .owner = THIS_MODULE,
1332                    },
1333 };
1335 static int __init da8xx_fb_init(void)
1337         return platform_driver_register(&da8xx_fb_driver);
1340 static void __exit da8xx_fb_cleanup(void)
1342         platform_driver_unregister(&da8xx_fb_driver);
1345 module_init(da8xx_fb_init);
1346 module_exit(da8xx_fb_cleanup);
1348 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1349 MODULE_AUTHOR("Texas Instruments");
1350 MODULE_LICENSE("GPL");