56badc0ecac689952ede99f5a674b71bdea593b1
1 /*
2 * Copyright (C) 2008-2009 MontaVista Software Inc.
3 * Copyright (C) 2008-2009 Texas Instruments Inc
4 *
5 * Based on the LCD driver for TI Avalanche processors written by
6 * Ajay Singh and Shalom Hai.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option)any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/fb.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/interrupt.h>
30 #include <linux/clk.h>
31 #include <linux/cpufreq.h>
32 #include <linux/console.h>
33 #include <linux/slab.h>
34 #include <video/da8xx-fb.h>
35 #include <asm/mach-types.h>
37 #define DRIVER_NAME "da8xx_lcdc"
39 #define LCD_VERSION_1 1
40 #define LCD_VERSION_2 2
42 /* LCD Status Register */
43 #define LCD_END_OF_FRAME1 BIT(9)
44 #define LCD_END_OF_FRAME0 BIT(8)
45 #define LCD_PL_LOAD_DONE BIT(6)
46 #define LCD_FIFO_UNDERFLOW BIT(5)
47 #define LCD_SYNC_LOST BIT(2)
49 /* LCD DMA Control Register */
50 #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
51 #define LCD_DMA_BURST_1 0x0
52 #define LCD_DMA_BURST_2 0x1
53 #define LCD_DMA_BURST_4 0x2
54 #define LCD_DMA_BURST_8 0x3
55 #define LCD_DMA_BURST_16 0x4
56 #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)
57 #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8)
58 #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9)
59 #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
61 /* LCD Control Register */
62 #define LCD_CLK_DIVISOR(x) ((x) << 8)
63 #define LCD_RASTER_MODE 0x01
65 /* LCD Raster Control Register */
66 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
67 #define PALETTE_AND_DATA 0x00
68 #define PALETTE_ONLY 0x01
69 #define DATA_ONLY 0x02
71 #define LCD_MONO_8BIT_MODE BIT(9)
72 #define LCD_RASTER_ORDER BIT(8)
73 #define LCD_TFT_MODE BIT(7)
74 #define LCD_V1_UNDERFLOW_INT_ENA BIT(6)
75 #define LCD_V2_UNDERFLOW_INT_ENA BIT(5)
76 #define LCD_V1_PL_INT_ENA BIT(4)
77 #define LCD_V2_PL_INT_ENA BIT(6)
78 #define LCD_MONOCHROME_MODE BIT(1)
79 #define LCD_RASTER_ENABLE BIT(0)
80 #define LCD_TFT_ALT_ENABLE BIT(23)
81 #define LCD_STN_565_ENABLE BIT(24)
82 #define LCD_V2_DMA_CLK_EN BIT(2)
83 #define LCD_V2_LIDD_CLK_EN BIT(1)
84 #define LCD_V2_CORE_CLK_EN BIT(0)
85 #define LCD_V2_LPP_B10 26
86 #define LCD_V2_TFT_24BPP_MODE BIT(25)
87 #define LCD_V2_TFT_24BPP_UNPACK BIT(26)
89 /* LCD Raster Timing 2 Register */
90 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
91 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
92 #define LCD_SYNC_CTRL BIT(25)
93 #define LCD_SYNC_EDGE BIT(24)
94 #define LCD_INVERT_PIXEL_CLOCK BIT(22)
95 #define LCD_INVERT_LINE_CLOCK BIT(21)
96 #define LCD_INVERT_FRAME_CLOCK BIT(20)
98 /* LCD Block */
99 #define LCD_PID_REG 0x0
100 #define LCD_CTRL_REG 0x4
101 #define LCD_STAT_REG 0x8
102 #define LCD_RASTER_CTRL_REG 0x28
103 #define LCD_RASTER_TIMING_0_REG 0x2C
104 #define LCD_RASTER_TIMING_1_REG 0x30
105 #define LCD_RASTER_TIMING_2_REG 0x34
106 #define LCD_DMA_CTRL_REG 0x40
107 #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44
108 #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
109 #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C
110 #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50
112 /* Interrupt Registers available only in Version 2 */
113 #define LCD_RAW_STAT_REG 0x58
114 #define LCD_MASKED_STAT_REG 0x5c
115 #define LCD_INT_ENABLE_SET_REG 0x60
116 #define LCD_INT_ENABLE_CLR_REG 0x64
117 #define LCD_END_OF_INT_IND_REG 0x68
119 /* Clock registers available only on Version 2 */
120 #define LCD_CLK_ENABLE_REG 0x6c
121 #define LCD_CLK_RESET_REG 0x70
122 #define LCD_CLK_MAIN_RESET BIT(3)
124 #define LCD_NUM_BUFFERS 2
126 #define WSI_TIMEOUT 50
127 #define PALETTE_SIZE 256
128 #define LEFT_MARGIN 64
129 #define RIGHT_MARGIN 64
130 #define UPPER_MARGIN 32
131 #define LOWER_MARGIN 32
133 static resource_size_t da8xx_fb_reg_base;
134 static struct resource *lcdc_regs;
135 static unsigned int lcd_revision;
136 static irq_handler_t lcdc_irq_handler;
138 static inline unsigned int lcdc_read(unsigned int addr)
139 {
140 return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
141 }
143 static inline void lcdc_write(unsigned int val, unsigned int addr)
144 {
145 __raw_writel(val, da8xx_fb_reg_base + (addr));
146 }
148 struct da8xx_fb_par {
149 resource_size_t p_palette_base;
150 unsigned char *v_palette_base;
151 dma_addr_t vram_phys;
152 unsigned long vram_size;
153 void *vram_virt;
154 unsigned int dma_start;
155 unsigned int dma_end;
156 struct clk *lcdc_clk;
157 int irq;
158 unsigned long pseudo_palette[32];
159 unsigned int palette_sz;
160 unsigned int pxl_clk;
161 int blank;
162 wait_queue_head_t vsync_wait;
163 int vsync_flag;
164 int vsync_timeout;
165 #ifdef CONFIG_CPU_FREQ
166 struct notifier_block freq_transition;
167 #endif
168 void (*panel_power_ctrl)(int);
169 };
171 /* Variable Screen Information */
172 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
173 .xoffset = 0,
174 .yoffset = 0,
175 .transp = {0, 0, 0},
176 .nonstd = 0,
177 .activate = 0,
178 .height = -1,
179 .width = -1,
180 .pixclock = 33333,/*Pico Sec*/
181 .accel_flags = 0,
182 .left_margin = LEFT_MARGIN,
183 .right_margin = RIGHT_MARGIN,
184 .upper_margin = UPPER_MARGIN,
185 .lower_margin = LOWER_MARGIN,
186 .sync = 0,
187 .vmode = FB_VMODE_NONINTERLACED
188 };
190 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
191 .id = "DA8xx FB Drv",
192 .type = FB_TYPE_PACKED_PIXELS,
193 .type_aux = 0,
194 .visual = FB_VISUAL_PSEUDOCOLOR,
195 .xpanstep = 0,
196 .ypanstep = 1,
197 .ywrapstep = 0,
198 .accel = FB_ACCEL_NONE
199 };
201 struct da8xx_panel {
202 const char name[25]; /* Full name <vendor>_<model> */
203 unsigned short width;
204 unsigned short height;
205 int hfp; /* Horizontal front porch */
206 int hbp; /* Horizontal back porch */
207 int hsw; /* Horizontal Sync Pulse Width */
208 int vfp; /* Vertical front porch */
209 int vbp; /* Vertical back porch */
210 int vsw; /* Vertical Sync Pulse Width */
211 unsigned int pxl_clk; /* Pixel clock */
212 unsigned char invert_pxl_clk; /* Invert Pixel clock */
213 };
215 static struct da8xx_panel known_lcd_panels[] = {
216 /* Sharp LCD035Q3DG01 */
217 [0] = {
218 .name = "Sharp_LCD035Q3DG01",
219 .width = 320,
220 .height = 240,
221 .hfp = 8,
222 .hbp = 6,
223 .hsw = 0,
224 .vfp = 2,
225 .vbp = 2,
226 .vsw = 0,
227 .pxl_clk = 4608000,
228 .invert_pxl_clk = 1,
229 },
230 /* Sharp LK043T1DG01 */
231 [1] = {
232 .name = "Sharp_LK043T1DG01",
233 .width = 480,
234 .height = 272,
235 .hfp = 2,
236 .hbp = 2,
237 .hsw = 41,
238 .vfp = 3,
239 .vbp = 3,
240 .vsw = 10,
241 .pxl_clk = 7833600,
242 .invert_pxl_clk = 0,
243 },
244 /* ThreeFive S9700RTWV35TR */
245 [2] = {
246 .name = "TFC_S9700RTWV35TR_01B",
247 .width = 800,
248 .height = 480,
249 .hfp = 39,
250 .hbp = 39,
251 .hsw = 47,
252 .vfp = 13,
253 .vbp = 29,
254 .vsw = 2,
255 .pxl_clk = 30000000,
256 .invert_pxl_clk = 0,
257 },
258 };
260 /* Enable the Raster Engine of the LCD Controller */
261 static inline void lcd_enable_raster(void)
262 {
263 u32 reg;
265 /* Bring LCDC out of reset */
266 if (lcd_revision == LCD_VERSION_2)
267 lcdc_write(0, LCD_CLK_RESET_REG);
269 reg = lcdc_read(LCD_RASTER_CTRL_REG);
270 if (!(reg & LCD_RASTER_ENABLE))
271 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
272 }
274 /* Disable the Raster Engine of the LCD Controller */
275 static inline void lcd_disable_raster(void)
276 {
277 u32 reg;
279 reg = lcdc_read(LCD_RASTER_CTRL_REG);
280 if (reg & LCD_RASTER_ENABLE)
281 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
283 if (lcd_revision == LCD_VERSION_2)
284 /* Write 1 to reset LCDC */
285 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
286 }
288 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
289 {
290 u32 start;
291 u32 end;
292 u32 reg_ras;
293 u32 reg_dma;
294 u32 reg_int;
296 /* init reg to clear PLM (loading mode) fields */
297 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
298 reg_ras &= ~(3 << 20);
300 reg_dma = lcdc_read(LCD_DMA_CTRL_REG);
302 if (load_mode == LOAD_DATA) {
303 start = par->dma_start;
304 end = par->dma_end;
306 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
307 if (lcd_revision == LCD_VERSION_1) {
308 reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
309 } else {
310 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
311 LCD_V2_END_OF_FRAME0_INT_ENA |
312 LCD_V2_END_OF_FRAME1_INT_ENA;
313 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
314 }
315 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
317 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
318 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
319 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
320 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
321 } else if (load_mode == LOAD_PALETTE) {
322 start = par->p_palette_base;
323 end = start + par->palette_sz - 1;
325 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
327 if (lcd_revision == LCD_VERSION_1) {
328 reg_ras |= LCD_V1_PL_INT_ENA;
329 } else {
330 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
331 LCD_V2_PL_INT_ENA;
332 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
333 }
335 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
336 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
337 }
339 lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
340 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
342 /*
343 * The Raster enable bit must be set after all other control fields are
344 * set.
345 */
346 lcd_enable_raster();
347 }
349 /* Configure the Burst Size and fifo threhold of DMA */
350 static int lcd_cfg_dma(int burst_size, int fifo_th)
351 {
352 u32 reg;
354 reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
355 switch (burst_size) {
356 case 1:
357 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
358 break;
359 case 2:
360 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
361 break;
362 case 4:
363 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
364 break;
365 case 8:
366 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
367 break;
368 case 16:
369 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
370 break;
371 default:
372 return -EINVAL;
373 }
375 reg |= (fifo_th << 8);
377 lcdc_write(reg, LCD_DMA_CTRL_REG);
379 return 0;
380 }
382 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
383 {
384 u32 reg;
386 /* Set the AC Bias Period and Number of Transisitons per Interrupt */
387 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
388 reg |= LCD_AC_BIAS_FREQUENCY(period) |
389 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
390 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
391 }
393 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
394 int front_porch)
395 {
396 u32 reg;
398 reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
399 reg |= ((back_porch & 0xff) << 24)
400 | ((front_porch & 0xff) << 16)
401 | ((pulse_width & 0x3f) << 10);
402 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
403 }
405 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
406 int front_porch)
407 {
408 u32 reg;
410 reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
411 reg |= ((back_porch & 0xff) << 24)
412 | ((front_porch & 0xff) << 16)
413 | ((pulse_width & 0x3f) << 10);
414 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
415 }
417 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
418 {
419 u32 reg;
420 u32 reg_int;
422 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
423 LCD_MONO_8BIT_MODE |
424 LCD_MONOCHROME_MODE);
426 switch (cfg->p_disp_panel->panel_shade) {
427 case MONOCHROME:
428 reg |= LCD_MONOCHROME_MODE;
429 if (cfg->mono_8bit_mode)
430 reg |= LCD_MONO_8BIT_MODE;
431 break;
432 case COLOR_ACTIVE:
433 reg |= LCD_TFT_MODE;
434 if (cfg->tft_alt_mode)
435 reg |= LCD_TFT_ALT_ENABLE;
436 break;
438 case COLOR_PASSIVE:
439 if (cfg->stn_565_mode)
440 reg |= LCD_STN_565_ENABLE;
441 break;
443 default:
444 return -EINVAL;
445 }
447 /* enable additional interrupts here */
448 if (lcd_revision == LCD_VERSION_1) {
449 reg |= LCD_V1_UNDERFLOW_INT_ENA;
450 } else {
451 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
452 LCD_V2_UNDERFLOW_INT_ENA;
453 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
454 }
456 lcdc_write(reg, LCD_RASTER_CTRL_REG);
458 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
460 if (cfg->sync_ctrl)
461 reg |= LCD_SYNC_CTRL;
462 else
463 reg &= ~LCD_SYNC_CTRL;
465 if (cfg->sync_edge)
466 reg |= LCD_SYNC_EDGE;
467 else
468 reg &= ~LCD_SYNC_EDGE;
470 if (cfg->invert_line_clock)
471 reg |= LCD_INVERT_LINE_CLOCK;
472 else
473 reg &= ~LCD_INVERT_LINE_CLOCK;
475 if (cfg->invert_frm_clock)
476 reg |= LCD_INVERT_FRAME_CLOCK;
477 else
478 reg &= ~LCD_INVERT_FRAME_CLOCK;
480 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
482 return 0;
483 }
485 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
486 u32 bpp, u32 raster_order)
487 {
488 u32 reg;
490 /* Set the Panel Width */
491 /* Pixels per line = (PPL + 1)*16 */
492 if (lcd_revision == LCD_VERSION_1) {
493 /*
494 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
495 * pixels.
496 */
497 width &= 0x3f0;
498 } else {
499 /*
500 * 0x7F in bits 4..10 gives max horizontal resolution = 2048
501 * pixels.
502 */
503 width &= 0x7f0;
504 }
506 reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
507 reg &= 0xfffffc00;
508 if (lcd_revision == LCD_VERSION_1) {
509 reg |= ((width >> 4) - 1) << 4;
510 } else {
511 width = (width >> 4) - 1;
512 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
513 }
514 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
516 /* Set the Panel Height */
517 /* Set bits 9:0 of Lines Per Pixel */
518 reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
519 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
520 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
522 /* Set bit 10 of Lines Per Pixel */
523 if (lcd_revision == LCD_VERSION_2) {
524 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
525 reg |= ((height - 1) & 0x400) << 16;
526 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
527 }
529 /* Set the Raster Order of the Frame Buffer */
530 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
531 if (raster_order)
532 reg |= LCD_RASTER_ORDER;
534 if (bpp == 24)
535 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
536 else if (bpp == 32)
537 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
538 | LCD_V2_TFT_24BPP_UNPACK);
540 lcdc_write(reg, LCD_RASTER_CTRL_REG);
542 switch (bpp) {
543 case 1:
544 case 2:
545 case 4:
546 case 16:
547 case 24:
548 case 32:
549 par->palette_sz = 16 * 2;
550 break;
552 case 8:
553 par->palette_sz = 256 * 2;
554 break;
556 default:
557 return -EINVAL;
558 }
560 return 0;
561 }
563 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
564 unsigned blue, unsigned transp,
565 struct fb_info *info)
566 {
567 struct da8xx_fb_par *par = info->par;
568 unsigned short *palette = (unsigned short *) par->v_palette_base;
569 u_short pal;
570 int update_hw = 0;
572 if (regno > 255)
573 return 1;
575 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
576 return 1;
578 if (info->var.bits_per_pixel == 8) {
579 red >>= 4;
580 green >>= 8;
581 blue >>= 12;
583 pal = (red & 0x0f00);
584 pal |= (green & 0x00f0);
585 pal |= (blue & 0x000f);
587 if (palette[regno] != pal) {
588 update_hw = 1;
589 palette[regno] = pal;
590 }
591 } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
592 red >>= (16 - info->var.red.length);
593 red <<= info->var.red.offset;
595 green >>= (16 - info->var.green.length);
596 green <<= info->var.green.offset;
598 blue >>= (16 - info->var.blue.length);
599 blue <<= info->var.blue.offset;
601 par->pseudo_palette[regno] = red | green | blue;
603 if (palette[0] != 0x4000) {
604 update_hw = 1;
605 palette[0] = 0x4000;
606 }
607 } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
608 ((info->var.bits_per_pixel == 24) && regno < 24)) {
609 red >>= (24 - info->var.red.length);
610 red <<= info->var.red.offset;
612 green >>= (24 - info->var.green.length);
613 green <<= info->var.green.offset;
615 blue >>= (24 - info->var.blue.length);
616 blue <<= info->var.blue.offset;
618 par->pseudo_palette[regno] = red | green | blue;
620 if (palette[0] != 0x4000) {
621 update_hw = 1;
622 palette[0] = 0x4000;
623 }
624 }
626 /* Update the palette in the h/w as needed. */
627 if (update_hw)
628 lcd_blit(LOAD_PALETTE, par);
630 return 0;
631 }
633 static void lcd_reset(struct da8xx_fb_par *par)
634 {
635 /* Disable the Raster if previously Enabled */
636 lcd_disable_raster();
638 /* DMA has to be disabled */
639 lcdc_write(0, LCD_DMA_CTRL_REG);
640 lcdc_write(0, LCD_RASTER_CTRL_REG);
642 if (lcd_revision == LCD_VERSION_2) {
643 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
644 /* Write 1 to reset */
645 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
646 lcdc_write(0, LCD_CLK_RESET_REG);
647 }
648 }
650 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
651 {
652 unsigned int lcd_clk, div;
654 lcd_clk = clk_get_rate(par->lcdc_clk);
655 div = lcd_clk / par->pxl_clk;
657 /* Configure the LCD clock divisor. */
658 lcdc_write(LCD_CLK_DIVISOR(div) |
659 (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
661 if (lcd_revision == LCD_VERSION_2)
662 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
663 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
665 }
667 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
668 struct da8xx_panel *panel)
669 {
670 u32 bpp;
671 int ret = 0;
673 lcd_reset(par);
675 /* Calculate the divider */
676 lcd_calc_clk_divider(par);
678 if (panel->invert_pxl_clk)
679 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
680 LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
681 else
682 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
683 ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
685 /* Configure the DMA burst size and fifo threshold. */
686 ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
687 if (ret < 0)
688 return ret;
690 /* Configure the AC bias properties. */
691 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
693 /* Configure the vertical and horizontal sync properties. */
694 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
695 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
697 /* Configure for disply */
698 ret = lcd_cfg_display(cfg);
699 if (ret < 0)
700 return ret;
703 if ((QVGA != cfg->p_disp_panel->panel_type) &&
704 (WVGA != cfg->p_disp_panel->panel_type))
705 return -EINVAL;
707 if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
708 cfg->bpp >= cfg->p_disp_panel->min_bpp)
709 bpp = cfg->bpp;
710 else
711 bpp = cfg->p_disp_panel->max_bpp;
712 if (bpp == 12)
713 bpp = 16;
714 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
715 (unsigned int)panel->height, bpp,
716 cfg->raster_order);
717 if (ret < 0)
718 return ret;
720 /* Configure FDD */
721 lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
722 (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
724 return 0;
725 }
727 /* IRQ handler for version 2 of LCDC */
728 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
729 {
730 struct da8xx_fb_par *par = arg;
731 u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
732 u32 reg_int;
734 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
735 lcd_disable_raster();
736 clk_disable(par->lcdc_clk);
737 lcdc_write(stat, LCD_MASKED_STAT_REG);
738 lcd_enable_raster();
739 clk_enable(par->lcdc_clk);
740 } else if (stat & LCD_PL_LOAD_DONE) {
741 /*
742 * Must disable raster before changing state of any control bit.
743 * And also must be disabled before clearing the PL loading
744 * interrupt via the following write to the status register. If
745 * this is done after then one gets multiple PL done interrupts.
746 */
747 lcd_disable_raster();
749 lcdc_write(stat, LCD_MASKED_STAT_REG);
751 /* Disable PL completion inerrupt */
752 reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |
753 (LCD_V2_PL_INT_ENA);
754 lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);
756 /* Setup and start data loading mode */
757 lcd_blit(LOAD_DATA, par);
758 } else {
759 lcdc_write(stat, LCD_MASKED_STAT_REG);
761 if (stat & LCD_END_OF_FRAME0) {
762 lcdc_write(par->dma_start,
763 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
764 lcdc_write(par->dma_end,
765 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
766 par->vsync_flag = 1;
767 wake_up_interruptible(&par->vsync_wait);
768 }
770 if (stat & LCD_END_OF_FRAME1) {
771 lcdc_write(par->dma_start,
772 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
773 lcdc_write(par->dma_end,
774 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
775 par->vsync_flag = 1;
776 wake_up_interruptible(&par->vsync_wait);
777 }
778 }
780 lcdc_write(0, LCD_END_OF_INT_IND_REG);
781 return IRQ_HANDLED;
782 }
784 /* IRQ handler for version 1 LCDC */
785 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
786 {
787 struct da8xx_fb_par *par = arg;
788 u32 stat = lcdc_read(LCD_STAT_REG);
789 u32 reg_ras;
791 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
792 lcd_disable_raster();
793 clk_disable(par->lcdc_clk);
794 lcdc_write(stat, LCD_STAT_REG);
795 lcd_enable_raster();
796 clk_enable(par->lcdc_clk);
797 } else if (stat & LCD_PL_LOAD_DONE) {
798 /*
799 * Must disable raster before changing state of any control bit.
800 * And also must be disabled before clearing the PL loading
801 * interrupt via the following write to the status register. If
802 * this is done after then one gets multiple PL done interrupts.
803 */
804 lcd_disable_raster();
806 lcdc_write(stat, LCD_STAT_REG);
808 /* Disable PL completion inerrupt */
809 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
810 reg_ras &= ~LCD_V1_PL_INT_ENA;
811 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
813 /* Setup and start data loading mode */
814 lcd_blit(LOAD_DATA, par);
815 } else {
816 lcdc_write(stat, LCD_STAT_REG);
818 if (stat & LCD_END_OF_FRAME0) {
819 lcdc_write(par->dma_start,
820 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
821 lcdc_write(par->dma_end,
822 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
823 par->vsync_flag = 1;
824 wake_up_interruptible(&par->vsync_wait);
825 }
827 if (stat & LCD_END_OF_FRAME1) {
828 lcdc_write(par->dma_start,
829 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
830 lcdc_write(par->dma_end,
831 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
832 par->vsync_flag = 1;
833 wake_up_interruptible(&par->vsync_wait);
834 }
835 }
837 return IRQ_HANDLED;
838 }
840 static int fb_check_var(struct fb_var_screeninfo *var,
841 struct fb_info *info)
842 {
843 int err = 0;
845 switch (var->bits_per_pixel) {
846 case 1:
847 case 8:
848 var->red.offset = 0;
849 var->red.length = 8;
850 var->green.offset = 0;
851 var->green.length = 8;
852 var->blue.offset = 0;
853 var->blue.length = 8;
854 var->transp.offset = 0;
855 var->transp.length = 0;
856 break;
857 case 4:
858 var->red.offset = 0;
859 var->red.length = 4;
860 var->green.offset = 0;
861 var->green.length = 4;
862 var->blue.offset = 0;
863 var->blue.length = 4;
864 var->transp.offset = 0;
865 var->transp.length = 0;
866 break;
867 case 16: /* RGB 565 */
868 var->red.offset = 11;
869 var->red.length = 5;
870 var->green.offset = 5;
871 var->green.length = 6;
872 var->blue.offset = 0;
873 var->blue.length = 5;
874 var->transp.offset = 0;
875 var->transp.length = 0;
876 break;
877 case 24:
878 var->red.offset = 16;
879 var->red.length = 8;
880 var->green.offset = 8;
881 var->green.length = 8;
882 var->blue.offset = 0;
883 var->blue.length = 8;
884 break;
885 case 32:
886 var->transp.offset = 24;
887 var->transp.length = 8;
888 var->red.offset = 16;
889 var->red.length = 8;
890 var->green.offset = 8;
891 var->green.length = 8;
892 var->blue.offset = 0;
893 var->blue.length = 8;
894 break;
895 default:
896 err = -EINVAL;
897 }
899 var->red.msb_right = 0;
900 var->green.msb_right = 0;
901 var->blue.msb_right = 0;
902 var->transp.msb_right = 0;
903 return err;
904 }
906 #ifdef CONFIG_CPU_FREQ
907 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
908 unsigned long val, void *data)
909 {
910 struct da8xx_fb_par *par;
912 par = container_of(nb, struct da8xx_fb_par, freq_transition);
913 if (val == CPUFREQ_PRECHANGE) {
914 lcd_disable_raster();
915 } else if (val == CPUFREQ_POSTCHANGE) {
916 lcd_calc_clk_divider(par);
917 lcd_enable_raster();
918 }
920 return 0;
921 }
923 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
924 {
925 par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
927 return cpufreq_register_notifier(&par->freq_transition,
928 CPUFREQ_TRANSITION_NOTIFIER);
929 }
931 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
932 {
933 cpufreq_unregister_notifier(&par->freq_transition,
934 CPUFREQ_TRANSITION_NOTIFIER);
935 }
936 #endif
938 static int __devexit fb_remove(struct platform_device *dev)
939 {
940 struct fb_info *info = dev_get_drvdata(&dev->dev);
942 if (info) {
943 struct da8xx_fb_par *par = info->par;
945 #ifdef CONFIG_CPU_FREQ
946 lcd_da8xx_cpufreq_deregister(par);
947 #endif
948 if (par->panel_power_ctrl)
949 par->panel_power_ctrl(0);
951 lcd_disable_raster();
952 lcdc_write(0, LCD_RASTER_CTRL_REG);
954 /* disable DMA */
955 lcdc_write(0, LCD_DMA_CTRL_REG);
957 unregister_framebuffer(info);
958 fb_dealloc_cmap(&info->cmap);
959 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
960 par->p_palette_base);
961 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
962 par->vram_phys);
963 free_irq(par->irq, par);
964 clk_disable(par->lcdc_clk);
965 clk_put(par->lcdc_clk);
966 framebuffer_release(info);
967 iounmap((void __iomem *)da8xx_fb_reg_base);
968 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
970 }
971 return 0;
972 }
974 /*
975 * Function to wait for vertical sync which for this LCD peripheral
976 * translates into waiting for the current raster frame to complete.
977 */
978 static int fb_wait_for_vsync(struct fb_info *info)
979 {
980 struct da8xx_fb_par *par = info->par;
981 int ret;
983 /*
984 * Set flag to 0 and wait for isr to set to 1. It would seem there is a
985 * race condition here where the ISR could have occurred just before or
986 * just after this set. But since we are just coarsely waiting for
987 * a frame to complete then that's OK. i.e. if the frame completed
988 * just before this code executed then we have to wait another full
989 * frame time but there is no way to avoid such a situation. On the
990 * other hand if the frame completed just after then we don't need
991 * to wait long at all. Either way we are guaranteed to return to the
992 * user immediately after a frame completion which is all that is
993 * required.
994 */
995 par->vsync_flag = 0;
996 ret = wait_event_interruptible_timeout(par->vsync_wait,
997 par->vsync_flag != 0,
998 par->vsync_timeout);
999 if (ret < 0)
1000 return ret;
1001 if (ret == 0)
1002 return -ETIMEDOUT;
1004 if (par->panel_power_ctrl) {
1005 /* Switch off panel power and backlight */
1006 par->panel_power_ctrl(0);
1008 /* Switch on panel power and backlight */
1009 par->panel_power_ctrl(1);
1010 }
1012 return 0;
1013 }
1015 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
1016 unsigned long arg)
1017 {
1018 struct lcd_sync_arg sync_arg;
1020 switch (cmd) {
1021 case FBIOGET_CONTRAST:
1022 case FBIOPUT_CONTRAST:
1023 case FBIGET_BRIGHTNESS:
1024 case FBIPUT_BRIGHTNESS:
1025 case FBIGET_COLOR:
1026 case FBIPUT_COLOR:
1027 return -ENOTTY;
1028 case FBIPUT_HSYNC:
1029 if (copy_from_user(&sync_arg, (char *)arg,
1030 sizeof(struct lcd_sync_arg)))
1031 return -EFAULT;
1032 lcd_cfg_horizontal_sync(sync_arg.back_porch,
1033 sync_arg.pulse_width,
1034 sync_arg.front_porch);
1035 break;
1036 case FBIPUT_VSYNC:
1037 if (copy_from_user(&sync_arg, (char *)arg,
1038 sizeof(struct lcd_sync_arg)))
1039 return -EFAULT;
1040 lcd_cfg_vertical_sync(sync_arg.back_porch,
1041 sync_arg.pulse_width,
1042 sync_arg.front_porch);
1043 break;
1044 case FBIO_WAITFORVSYNC:
1045 return fb_wait_for_vsync(info);
1046 default:
1047 return -EINVAL;
1048 }
1049 return 0;
1050 }
1052 static int cfb_blank(int blank, struct fb_info *info)
1053 {
1054 struct da8xx_fb_par *par = info->par;
1055 int ret = 0;
1057 if (par->blank == blank)
1058 return 0;
1060 par->blank = blank;
1061 switch (blank) {
1062 case FB_BLANK_UNBLANK:
1063 if (par->panel_power_ctrl)
1064 par->panel_power_ctrl(1);
1066 lcd_enable_raster();
1067 break;
1068 case FB_BLANK_POWERDOWN:
1069 if (par->panel_power_ctrl)
1070 par->panel_power_ctrl(0);
1072 lcd_disable_raster();
1073 break;
1074 default:
1075 ret = -EINVAL;
1076 }
1078 return ret;
1079 }
1081 /*
1082 * Set new x,y offsets in the virtual display for the visible area and switch
1083 * to the new mode.
1084 */
1085 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1086 struct fb_info *fbi)
1087 {
1088 int ret = 0;
1089 struct fb_var_screeninfo new_var;
1090 struct da8xx_fb_par *par = fbi->par;
1091 struct fb_fix_screeninfo *fix = &fbi->fix;
1092 unsigned int end;
1093 unsigned int start;
1095 if (var->xoffset != fbi->var.xoffset ||
1096 var->yoffset != fbi->var.yoffset) {
1097 memcpy(&new_var, &fbi->var, sizeof(new_var));
1098 new_var.xoffset = var->xoffset;
1099 new_var.yoffset = var->yoffset;
1100 if (fb_check_var(&new_var, fbi))
1101 ret = -EINVAL;
1102 else {
1103 memcpy(&fbi->var, &new_var, sizeof(new_var));
1105 start = fix->smem_start +
1106 new_var.yoffset * fix->line_length +
1107 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1108 end = start + fbi->var.yres * fix->line_length - 1;
1109 par->dma_start = start;
1110 par->dma_end = end;
1111 }
1112 }
1114 return ret;
1115 }
1117 static struct fb_ops da8xx_fb_ops = {
1118 .owner = THIS_MODULE,
1119 .fb_check_var = fb_check_var,
1120 .fb_setcolreg = fb_setcolreg,
1121 .fb_pan_display = da8xx_pan_display,
1122 .fb_ioctl = fb_ioctl,
1123 .fb_fillrect = cfb_fillrect,
1124 .fb_copyarea = cfb_copyarea,
1125 .fb_imageblit = cfb_imageblit,
1126 .fb_blank = cfb_blank,
1127 };
1129 static int __devinit fb_probe(struct platform_device *device)
1130 {
1131 struct da8xx_lcdc_platform_data *fb_pdata =
1132 device->dev.platform_data;
1133 struct lcd_ctrl_config *lcd_cfg;
1134 struct da8xx_panel *lcdc_info;
1135 struct fb_info *da8xx_fb_info;
1136 struct clk *fb_clk = NULL;
1137 struct clk *lcdc_ick = NULL;
1138 struct da8xx_fb_par *par;
1139 resource_size_t len;
1140 int ret, i;
1142 if (fb_pdata == NULL) {
1143 dev_err(&device->dev, "Can not get platform data\n");
1144 return -ENOENT;
1145 }
1147 lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1148 if (!lcdc_regs) {
1149 dev_err(&device->dev,
1150 "Can not get memory resource for LCD controller\n");
1151 return -ENOENT;
1152 }
1154 len = resource_size(lcdc_regs);
1156 lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
1157 if (!lcdc_regs)
1158 return -EBUSY;
1160 da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
1161 if (!da8xx_fb_reg_base) {
1162 ret = -EBUSY;
1163 goto err_request_mem;
1164 }
1166 /*
1167 * Some SoC will not have seperate interface clock,
1168 * so make lazy check here
1169 */
1170 lcdc_ick = clk_get(&device->dev, "lcdc_ick");
1171 if (IS_ERR(lcdc_ick))
1172 dev_err(&device->dev, "Can not get lcdc_ick\n");
1174 ret = clk_enable(lcdc_ick);
1175 if (ret)
1176 dev_err(&device->dev, "failed to enable lcdc_ick\n");
1178 fb_clk = clk_get(&device->dev, NULL);
1179 if (IS_ERR(fb_clk)) {
1180 dev_err(&device->dev, "Can not get device clock\n");
1181 ret = -ENODEV;
1182 goto err_ioremap;
1183 }
1184 ret = clk_enable(fb_clk);
1185 if (ret)
1186 goto err_clk_put;
1188 /* Determine LCD IP Version */
1189 switch (lcdc_read(LCD_PID_REG)) {
1190 case 0x4C100102:
1191 lcd_revision = LCD_VERSION_1;
1192 break;
1193 case 0x4F200800:
1194 case 0x4F201000:
1195 lcd_revision = LCD_VERSION_2;
1196 break;
1197 default:
1198 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1199 "defaulting to LCD revision 1\n",
1200 lcdc_read(LCD_PID_REG));
1201 lcd_revision = LCD_VERSION_1;
1202 break;
1203 }
1205 for (i = 0, lcdc_info = known_lcd_panels;
1206 i < ARRAY_SIZE(known_lcd_panels);
1207 i++, lcdc_info++) {
1208 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1209 break;
1210 }
1212 if (i == ARRAY_SIZE(known_lcd_panels)) {
1213 dev_err(&device->dev, "GLCD: No valid panel found\n");
1214 ret = -ENODEV;
1215 goto err_clk_disable;
1216 } else
1217 dev_info(&device->dev, "GLCD: Found %s panel\n",
1218 fb_pdata->type);
1220 lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1222 da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1223 &device->dev);
1224 if (!da8xx_fb_info) {
1225 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1226 ret = -ENOMEM;
1227 goto err_clk_disable;
1228 }
1230 par = da8xx_fb_info->par;
1231 par->lcdc_clk = fb_clk;
1232 par->pxl_clk = lcdc_info->pxl_clk;
1233 if (fb_pdata->panel_power_ctrl) {
1234 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1235 par->panel_power_ctrl(1);
1236 }
1238 if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
1239 dev_err(&device->dev, "lcd_init failed\n");
1240 ret = -EFAULT;
1241 goto err_release_fb;
1242 }
1244 /* allocate frame buffer */
1245 par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
1246 par->vram_size = PAGE_ALIGN(par->vram_size/8);
1247 par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1249 par->vram_virt = dma_alloc_coherent(NULL,
1250 par->vram_size,
1251 (resource_size_t *) &par->vram_phys,
1252 GFP_KERNEL | GFP_DMA);
1253 if (!par->vram_virt) {
1254 dev_err(&device->dev,
1255 "GLCD: kmalloc for frame buffer failed\n");
1256 ret = -EINVAL;
1257 goto err_release_fb;
1258 }
1260 da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1261 da8xx_fb_fix.smem_start = par->vram_phys;
1262 da8xx_fb_fix.smem_len = par->vram_size;
1263 da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8;
1265 par->dma_start = par->vram_phys;
1266 par->dma_end = par->dma_start + lcdc_info->height *
1267 da8xx_fb_fix.line_length - 1;
1269 /* allocate palette buffer */
1270 par->v_palette_base = dma_alloc_coherent(NULL,
1271 PALETTE_SIZE,
1272 (resource_size_t *)
1273 &par->p_palette_base,
1274 GFP_KERNEL | GFP_DMA);
1275 if (!par->v_palette_base) {
1276 dev_err(&device->dev,
1277 "GLCD: kmalloc for palette buffer failed\n");
1278 ret = -EINVAL;
1279 goto err_release_fb_mem;
1280 }
1281 memset(par->v_palette_base, 0, PALETTE_SIZE);
1283 par->irq = platform_get_irq(device, 0);
1284 if (par->irq < 0) {
1285 ret = -ENOENT;
1286 goto err_release_pl_mem;
1287 }
1289 /* Initialize par */
1290 da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
1292 da8xx_fb_var.xres = lcdc_info->width;
1293 da8xx_fb_var.xres_virtual = lcdc_info->width;
1295 da8xx_fb_var.yres = lcdc_info->height;
1296 da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
1298 da8xx_fb_var.grayscale =
1299 lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
1300 da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1302 da8xx_fb_var.hsync_len = lcdc_info->hsw;
1303 da8xx_fb_var.vsync_len = lcdc_info->vsw;
1305 da8xx_fb_var.right_margin = lcdc_info->hfp;
1306 da8xx_fb_var.left_margin = lcdc_info->hbp;
1307 da8xx_fb_var.lower_margin = lcdc_info->vfp;
1308 da8xx_fb_var.upper_margin = lcdc_info->vbp;
1310 /* Initialize fbinfo */
1311 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1312 da8xx_fb_info->fix = da8xx_fb_fix;
1313 da8xx_fb_info->var = da8xx_fb_var;
1314 da8xx_fb_info->fbops = &da8xx_fb_ops;
1315 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1316 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1317 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1319 ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1320 if (ret)
1321 goto err_release_pl_mem;
1322 da8xx_fb_info->cmap.len = par->palette_sz;
1324 /* initialize var_screeninfo */
1325 da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1326 fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1328 dev_set_drvdata(&device->dev, da8xx_fb_info);
1330 /* initialize the vsync wait queue */
1331 init_waitqueue_head(&par->vsync_wait);
1332 par->vsync_timeout = HZ / 5;
1334 /* Register the Frame Buffer */
1335 if (register_framebuffer(da8xx_fb_info) < 0) {
1336 dev_err(&device->dev,
1337 "GLCD: Frame Buffer Registration Failed!\n");
1338 ret = -EINVAL;
1339 goto err_dealloc_cmap;
1340 }
1342 #ifdef CONFIG_CPU_FREQ
1343 ret = lcd_da8xx_cpufreq_register(par);
1344 if (ret) {
1345 dev_err(&device->dev, "failed to register cpufreq\n");
1346 goto err_cpu_freq;
1347 }
1348 #endif
1350 if (lcd_revision == LCD_VERSION_1)
1351 lcdc_irq_handler = lcdc_irq_handler_rev01;
1352 else
1353 lcdc_irq_handler = lcdc_irq_handler_rev02;
1355 ret = request_irq(par->irq, lcdc_irq_handler, 0,
1356 DRIVER_NAME, par);
1357 if (ret)
1358 goto irq_freq;
1359 return 0;
1361 irq_freq:
1362 #ifdef CONFIG_CPU_FREQ
1363 lcd_da8xx_cpufreq_deregister(par);
1364 #endif
1365 err_cpu_freq:
1366 unregister_framebuffer(da8xx_fb_info);
1368 err_dealloc_cmap:
1369 fb_dealloc_cmap(&da8xx_fb_info->cmap);
1371 err_release_pl_mem:
1372 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1373 par->p_palette_base);
1375 err_release_fb_mem:
1376 dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1378 err_release_fb:
1379 framebuffer_release(da8xx_fb_info);
1381 err_clk_disable:
1382 clk_disable(fb_clk);
1384 err_clk_put:
1385 clk_put(fb_clk);
1387 err_ioremap:
1388 iounmap((void __iomem *)da8xx_fb_reg_base);
1390 err_request_mem:
1391 release_mem_region(lcdc_regs->start, len);
1393 return ret;
1394 }
1396 #ifdef CONFIG_PM
1397 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1398 {
1399 struct fb_info *info = platform_get_drvdata(dev);
1400 struct da8xx_fb_par *par = info->par;
1401 unsigned long timeo = jiffies + msecs_to_jiffies(5000);
1402 u32 stat;
1404 console_lock();
1405 if (par->panel_power_ctrl)
1406 par->panel_power_ctrl(0);
1408 fb_set_suspend(info, 1);
1409 lcd_disable_raster();
1411 /* Wait for the current frame to complete */
1412 do {
1413 if (lcd_revision == LCD_VERSION_1)
1414 stat = lcdc_read(LCD_STAT_REG);
1415 else
1416 stat = lcdc_read(LCD_MASKED_STAT_REG);
1417 cpu_relax();
1418 } while (!(stat & BIT(0)) && time_before(jiffies, timeo));
1420 if (lcd_revision == LCD_VERSION_1)
1421 lcdc_write(stat, LCD_STAT_REG);
1422 else
1423 lcdc_write(stat, LCD_MASKED_STAT_REG);
1425 if (time_after_eq(jiffies, timeo)) {
1426 dev_err(&dev->dev, "controller timed out\n");
1427 return -ETIMEDOUT;
1428 }
1430 clk_disable(par->lcdc_clk);
1431 console_unlock();
1433 return 0;
1434 }
1435 static int fb_resume(struct platform_device *dev)
1436 {
1437 struct fb_info *info = platform_get_drvdata(dev);
1438 struct da8xx_fb_par *par = info->par;
1440 console_lock();
1441 if (par->panel_power_ctrl)
1442 par->panel_power_ctrl(1);
1444 clk_enable(par->lcdc_clk);
1446 lcd_enable_raster();
1448 if (par->panel_power_ctrl)
1449 par->panel_power_ctrl(1);
1451 fb_set_suspend(info, 0);
1452 console_unlock();
1454 return 0;
1455 }
1456 #else
1457 #define fb_suspend NULL
1458 #define fb_resume NULL
1459 #endif
1461 static struct platform_driver da8xx_fb_driver = {
1462 .probe = fb_probe,
1463 .remove = __devexit_p(fb_remove),
1464 .suspend = fb_suspend,
1465 .resume = fb_resume,
1466 .driver = {
1467 .name = DRIVER_NAME,
1468 .owner = THIS_MODULE,
1469 },
1470 };
1472 static int __init da8xx_fb_init(void)
1473 {
1474 return platform_driver_register(&da8xx_fb_driver);
1475 }
1477 static void __exit da8xx_fb_cleanup(void)
1478 {
1479 platform_driver_unregister(&da8xx_fb_driver);
1480 }
1482 module_init(da8xx_fb_init);
1483 module_exit(da8xx_fb_cleanup);
1485 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1486 MODULE_AUTHOR("Texas Instruments");
1487 MODULE_LICENSE("GPL");