video: da8xx-fb: correct suspend/resume sequence
[sitara-epos/sitara-epos-kernel.git] / drivers / video / da8xx-fb.c
1 /*
2  * Copyright (C) 2008-2009 MontaVista Software Inc.
3  * Copyright (C) 2008-2009 Texas Instruments Inc
4  *
5  * Based on the LCD driver for TI Avalanche processors written by
6  * Ajay Singh and Shalom Hai.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option)any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21  */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/fb.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/interrupt.h>
30 #include <linux/clk.h>
31 #include <linux/cpufreq.h>
32 #include <linux/console.h>
33 #include <linux/spinlock.h>
34 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/pm_runtime.h>
37 #include <video/da8xx-fb.h>
38 #include <asm/mach-types.h>
40 #define DRIVER_NAME "da8xx_lcdc"
42 #define LCD_VERSION_1   1
43 #define LCD_VERSION_2   2
45 /* LCD Status Register */
46 #define LCD_END_OF_FRAME1               BIT(9)
47 #define LCD_END_OF_FRAME0               BIT(8)
48 #define LCD_PL_LOAD_DONE                BIT(6)
49 #define LCD_FIFO_UNDERFLOW              BIT(5)
50 #define LCD_SYNC_LOST                   BIT(2)
52 /* LCD DMA Control Register */
53 #define LCD_DMA_BURST_SIZE(x)           ((x) << 4)
54 #define LCD_DMA_BURST_1                 0x0
55 #define LCD_DMA_BURST_2                 0x1
56 #define LCD_DMA_BURST_4                 0x2
57 #define LCD_DMA_BURST_8                 0x3
58 #define LCD_DMA_BURST_16                0x4
59 #define LCD_V1_END_OF_FRAME_INT_ENA     BIT(2)
60 #define LCD_V2_END_OF_FRAME0_INT_ENA    BIT(8)
61 #define LCD_V2_END_OF_FRAME1_INT_ENA    BIT(9)
62 #define LCD_DUAL_FRAME_BUFFER_ENABLE    BIT(0)
64 /* LCD Control Register */
65 #define LCD_CLK_DIVISOR(x)              ((x) << 8)
66 #define LCD_RASTER_MODE                 0x01
68 /* LCD Raster Control Register */
69 #define LCD_PALETTE_LOAD_MODE(x)        ((x) << 20)
70 #define PALETTE_AND_DATA                0x00
71 #define PALETTE_ONLY                    0x01
72 #define DATA_ONLY                       0x02
74 #define LCD_MONO_8BIT_MODE              BIT(9)
75 #define LCD_RASTER_ORDER                BIT(8)
76 #define LCD_TFT_MODE                    BIT(7)
77 #define LCD_V1_UNDERFLOW_INT_ENA        BIT(6)
78 #define LCD_V2_UNDERFLOW_INT_ENA        BIT(5)
79 #define LCD_V1_PL_INT_ENA               BIT(4)
80 #define LCD_V2_PL_INT_ENA               BIT(6)
81 #define LCD_MONOCHROME_MODE             BIT(1)
82 #define LCD_RASTER_ENABLE               BIT(0)
83 #define LCD_TFT_ALT_ENABLE              BIT(23)
84 #define LCD_STN_565_ENABLE              BIT(24)
85 #define LCD_V2_DMA_CLK_EN               BIT(2)
86 #define LCD_V2_LIDD_CLK_EN              BIT(1)
87 #define LCD_V2_CORE_CLK_EN              BIT(0)
88 #define LCD_V2_LPP_B10                  26
89 #define LCD_V2_TFT_24BPP_MODE           BIT(25)
90 #define LCD_V2_TFT_24BPP_UNPACK         BIT(26)
92 /* LCD Raster Timing 2 Register */
93 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
94 #define LCD_AC_BIAS_FREQUENCY(x)                ((x) << 8)
95 #define LCD_SYNC_CTRL                           BIT(25)
96 #define LCD_SYNC_EDGE                           BIT(24)
97 #define LCD_INVERT_PIXEL_CLOCK                  BIT(22)
98 #define LCD_INVERT_LINE_CLOCK                   BIT(21)
99 #define LCD_INVERT_FRAME_CLOCK                  BIT(20)
101 /* LCD Block */
102 #define  LCD_PID_REG                            0x0
103 #define  LCD_CTRL_REG                           0x4
104 #define  LCD_STAT_REG                           0x8
105 #define  LCD_RASTER_CTRL_REG                    0x28
106 #define  LCD_RASTER_TIMING_0_REG                0x2C
107 #define  LCD_RASTER_TIMING_1_REG                0x30
108 #define  LCD_RASTER_TIMING_2_REG                0x34
109 #define  LCD_DMA_CTRL_REG                       0x40
110 #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG        0x44
111 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG     0x48
112 #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG        0x4C
113 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG     0x50
115 /* Interrupt Registers available only in Version 2 */
116 #define  LCD_RAW_STAT_REG                       0x58
117 #define  LCD_MASKED_STAT_REG                    0x5c
118 #define  LCD_INT_ENABLE_SET_REG                 0x60
119 #define  LCD_INT_ENABLE_CLR_REG                 0x64
120 #define  LCD_END_OF_INT_IND_REG                 0x68
122 /* Clock registers available only on Version 2 */
123 #define  LCD_CLK_ENABLE_REG                     0x6c
124 #define  LCD_CLK_RESET_REG                      0x70
125 #define  LCD_CLK_MAIN_RESET                     BIT(3)
127 #define LCD_NUM_BUFFERS 2
129 #define WSI_TIMEOUT     50
130 #define PALETTE_SIZE    256
131 #define LEFT_MARGIN     64
132 #define RIGHT_MARGIN    64
133 #define UPPER_MARGIN    32
134 #define LOWER_MARGIN    32
135 #define WAIT_FOR_FRAME_DONE     true
136 #define NO_WAIT_FOR_FRAME_DONE  false
138 static resource_size_t da8xx_fb_reg_base;
139 static struct resource *lcdc_regs;
140 static unsigned int lcd_revision;
141 static irq_handler_t lcdc_irq_handler;
143 static inline unsigned int lcdc_read(unsigned int addr)
145         return (unsigned int)readl(da8xx_fb_reg_base + (addr));
148 static inline void lcdc_write(unsigned int val, unsigned int addr)
150         writel(val, da8xx_fb_reg_base + (addr));
153 struct da8xx_fb_par {
154         struct device *dev;
155         resource_size_t p_palette_base;
156         unsigned char *v_palette_base;
157         dma_addr_t              vram_phys;
158         unsigned long           vram_size;
159         void                    *vram_virt;
160         unsigned int            dma_start;
161         unsigned int            dma_end;
162         struct clk *lcdc_clk;
163         int irq;
164         unsigned long pseudo_palette[32];
165         unsigned int palette_sz;
166         unsigned int pxl_clk;
167         int blank;
168         wait_queue_head_t       vsync_wait;
169         int                     vsync_flag;
170         int                     vsync_timeout;
171         spinlock_t              lock_for_chan_update;
173         /*
174          * LCDC has 2 ping pong DMA channels, channel 0
175          * and channel 1.
176          */
177         unsigned int            which_dma_channel_done;
178 #ifdef CONFIG_CPU_FREQ
179         struct notifier_block   freq_transition;
180         unsigned int            lcd_fck_rate;
181 #endif
182         void (*panel_power_ctrl)(int);
183 };
185 /* Variable Screen Information */
186 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
187         .xoffset = 0,
188         .yoffset = 0,
189         .transp = {0, 0, 0},
190         .nonstd = 0,
191         .activate = 0,
192         .height = -1,
193         .width = -1,
194         .pixclock = 33333,/*Pico Sec*/
195         .accel_flags = 0,
196         .left_margin = LEFT_MARGIN,
197         .right_margin = RIGHT_MARGIN,
198         .upper_margin = UPPER_MARGIN,
199         .lower_margin = LOWER_MARGIN,
200         .sync = 0,
201         .vmode = FB_VMODE_NONINTERLACED
202 };
204 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
205         .id = "DA8xx FB Drv",
206         .type = FB_TYPE_PACKED_PIXELS,
207         .type_aux = 0,
208         .visual = FB_VISUAL_PSEUDOCOLOR,
209         .xpanstep = 0,
210         .ypanstep = 1,
211         .ywrapstep = 0,
212         .accel = FB_ACCEL_NONE
213 };
215 struct da8xx_panel {
216         const char      name[25];       /* Full name <vendor>_<model> */
217         unsigned short  width;
218         unsigned short  height;
219         int             hfp;            /* Horizontal front porch */
220         int             hbp;            /* Horizontal back porch */
221         int             hsw;            /* Horizontal Sync Pulse Width */
222         int             vfp;            /* Vertical front porch */
223         int             vbp;            /* Vertical back porch */
224         int             vsw;            /* Vertical Sync Pulse Width */
225         unsigned int    pxl_clk;        /* Pixel clock */
226         unsigned char   invert_pxl_clk; /* Invert Pixel clock */
227 };
229 static vsync_callback_t vsync_cb_handler;
230 static void *vsync_cb_arg;
232 static struct da8xx_panel known_lcd_panels[] = {
233         /* Sharp LCD035Q3DG01 */
234         [0] = {
235                 .name = "Sharp_LCD035Q3DG01",
236                 .width = 320,
237                 .height = 240,
238                 .hfp = 8,
239                 .hbp = 6,
240                 .hsw = 0,
241                 .vfp = 2,
242                 .vbp = 2,
243                 .vsw = 0,
244                 .pxl_clk = 4608000,
245                 .invert_pxl_clk = 1,
246         },
247         /* Sharp LK043T1DG01 */
248         [1] = {
249                 .name = "Sharp_LK043T1DG01",
250                 .width = 480,
251                 .height = 272,
252                 .hfp = 2,
253                 .hbp = 2,
254                 .hsw = 41,
255                 .vfp = 3,
256                 .vbp = 3,
257                 .vsw = 10,
258                 .pxl_clk = 7833600,
259                 .invert_pxl_clk = 0,
260         },
261         /* ThreeFive S9700RTWV35TR */
262         [2] = {
263                 .name = "TFC_S9700RTWV35TR_01B",
264                 .width = 800,
265                 .height = 480,
266                 .hfp = 39,
267                 .hbp = 39,
268                 .hsw = 47,
269                 .vfp = 13,
270                 .vbp = 29,
271                 .vsw = 2,
272                 .pxl_clk = 30000000,
273                 .invert_pxl_clk = 0,
274         },
275 };
277 /* Enable the Raster Engine of the LCD Controller */
278 static inline void lcd_enable_raster(void)
280         u32 reg;
282         /* Bring LCDC out of reset */
283         if (lcd_revision == LCD_VERSION_2)
284                 lcdc_write(0, LCD_CLK_RESET_REG);
286         reg = lcdc_read(LCD_RASTER_CTRL_REG);
287         if (!(reg & LCD_RASTER_ENABLE))
288                 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
291 /* Disable the Raster Engine of the LCD Controller */
292 static inline void lcd_disable_raster(bool wait_for_frame_done)
294         u32 reg;
295         u32 loop_cnt = 0;
296         u32 stat;
297         u32 i = 0;
299         if (wait_for_frame_done)
300                 loop_cnt = 5000;
302         reg = lcdc_read(LCD_RASTER_CTRL_REG);
303         if (reg & LCD_RASTER_ENABLE)
304                 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
306         /* Wait for the current frame to complete */
307         do {
308                 if (lcd_revision == LCD_VERSION_1)
309                         stat = lcdc_read(LCD_STAT_REG);
310                 else
311                         stat = lcdc_read(LCD_RAW_STAT_REG);
313                 mdelay(1);
314         } while (!(stat & BIT(0)) && (i++ < loop_cnt));
316         if (lcd_revision == LCD_VERSION_1)
317                 lcdc_write(stat, LCD_STAT_REG);
318         else
319                 lcdc_write(stat, LCD_MASKED_STAT_REG);
321         if ((loop_cnt != 0) && (i >= loop_cnt)) {
322                 printk(KERN_ERR "LCD Controller timed out\n");
323                 return;
324         }
327 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
329         u32 start;
330         u32 end;
331         u32 reg_ras;
332         u32 reg_dma;
333         u32 reg_int;
335         /* init reg to clear PLM (loading mode) fields */
336         reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
337         reg_ras &= ~(3 << 20);
339         reg_dma  = lcdc_read(LCD_DMA_CTRL_REG);
341         if (load_mode == LOAD_DATA) {
342                 start    = par->dma_start;
343                 end      = par->dma_end;
345                 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
346                 if (lcd_revision == LCD_VERSION_1) {
347                         reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
348                 } else {
349                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
350                                 LCD_V2_END_OF_FRAME0_INT_ENA |
351                                 LCD_V2_END_OF_FRAME1_INT_ENA |
352                                 LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
353                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
354                 }
355                 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
357                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
358                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
359                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
360                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
361         } else if (load_mode == LOAD_PALETTE) {
362                 start    = par->p_palette_base;
363                 end      = start + par->palette_sz - 1;
365                 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
367                 if (lcd_revision == LCD_VERSION_1) {
368                         reg_ras |= LCD_V1_PL_INT_ENA;
369                 } else {
370                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
371                                 LCD_V2_PL_INT_ENA;
372                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
373                 }
375                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
376                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
377         }
379         lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
380         lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
382         /*
383          * The Raster enable bit must be set after all other control fields are
384          * set.
385          */
386         lcd_enable_raster();
389 /* Configure the Burst Size and fifo threhold of DMA */
390 static int lcd_cfg_dma(int burst_size,  int fifo_th)
392         u32 reg;
394         reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
395         switch (burst_size) {
396         case 1:
397                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
398                 break;
399         case 2:
400                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
401                 break;
402         case 4:
403                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
404                 break;
405         case 8:
406                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
407                 break;
408         case 16:
409                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
410                 break;
411         default:
412                 return -EINVAL;
413         }
415         reg |= (fifo_th << 8);
417         lcdc_write(reg, LCD_DMA_CTRL_REG);
419         return 0;
422 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
424         u32 reg;
426         /* Set the AC Bias Period and Number of Transisitons per Interrupt */
427         reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
428         reg |= LCD_AC_BIAS_FREQUENCY(period) |
429                 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
430         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
433 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
434                 int front_porch)
436         u32 reg;
438         reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
439         reg |= ((back_porch & 0xff) << 24)
440             | ((front_porch & 0xff) << 16)
441             | ((pulse_width & 0x3f) << 10);
442         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
445 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
446                 int front_porch)
448         u32 reg;
450         reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
451         reg |= ((back_porch & 0xff) << 24)
452             | ((front_porch & 0xff) << 16)
453             | ((pulse_width & 0x3f) << 10);
454         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
457 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
459         u32 reg;
460         u32 reg_int;
462         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
463                                                 LCD_MONO_8BIT_MODE |
464                                                 LCD_MONOCHROME_MODE);
466         switch (cfg->p_disp_panel->panel_shade) {
467         case MONOCHROME:
468                 reg |= LCD_MONOCHROME_MODE;
469                 if (cfg->mono_8bit_mode)
470                         reg |= LCD_MONO_8BIT_MODE;
471                 break;
472         case COLOR_ACTIVE:
473                 reg |= LCD_TFT_MODE;
474                 if (cfg->tft_alt_mode)
475                         reg |= LCD_TFT_ALT_ENABLE;
476                 break;
478         case COLOR_PASSIVE:
479                 if (cfg->stn_565_mode)
480                         reg |= LCD_STN_565_ENABLE;
481                 break;
483         default:
484                 return -EINVAL;
485         }
487         /* enable additional interrupts here */
488         if (lcd_revision == LCD_VERSION_1) {
489                 reg |= LCD_V1_UNDERFLOW_INT_ENA;
490         } else {
491                 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
492                         LCD_V2_UNDERFLOW_INT_ENA;
493                 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
494         }
496         lcdc_write(reg, LCD_RASTER_CTRL_REG);
498         reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
500         if (cfg->sync_ctrl)
501                 reg |= LCD_SYNC_CTRL;
502         else
503                 reg &= ~LCD_SYNC_CTRL;
505         if (cfg->sync_edge)
506                 reg |= LCD_SYNC_EDGE;
507         else
508                 reg &= ~LCD_SYNC_EDGE;
510         if (cfg->invert_line_clock)
511                 reg |= LCD_INVERT_LINE_CLOCK;
512         else
513                 reg &= ~LCD_INVERT_LINE_CLOCK;
515         if (cfg->invert_frm_clock)
516                 reg |= LCD_INVERT_FRAME_CLOCK;
517         else
518                 reg &= ~LCD_INVERT_FRAME_CLOCK;
520         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
522         return 0;
525 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
526                 u32 bpp, u32 raster_order)
528         u32 reg;
530         /* Set the Panel Width */
531         /* Pixels per line = (PPL + 1)*16 */
532         if (lcd_revision == LCD_VERSION_1) {
533                 /*
534                  * 0x3F in bits 4..9 gives max horizontal resolution = 1024
535                  * pixels.
536                  */
537                 width &= 0x3f0;
538         } else {
539                 /*
540                  * 0x7F in bits 4..10 gives max horizontal resolution = 2048
541                  * pixels.
542                  */
543                 width &= 0x7f0;
544         }
546         reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
547         reg &= 0xfffffc00;
548         if (lcd_revision == LCD_VERSION_1) {
549                 reg |= ((width >> 4) - 1) << 4;
550         } else {
551                 width = (width >> 4) - 1;
552                 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
553         }
554         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
556         /* Set the Panel Height */
557         /* Set bits 9:0 of Lines Per Pixel */
558         reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
559         reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
560         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
562         /* Set bit 10 of Lines Per Pixel */
563         if (lcd_revision == LCD_VERSION_2) {
564                 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
565                 reg |= ((height - 1) & 0x400) << 16;
566                 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
567         }
569         /* Set the Raster Order of the Frame Buffer */
570         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
571         if (raster_order)
572                 reg |= LCD_RASTER_ORDER;
574         if (bpp == 24)
575                 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
576         else if (bpp == 32)
577                 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
578                                 | LCD_V2_TFT_24BPP_UNPACK);
580         lcdc_write(reg, LCD_RASTER_CTRL_REG);
582         switch (bpp) {
583         case 1:
584         case 2:
585         case 4:
586         case 16:
587         case 24:
588         case 32:
589                 par->palette_sz = 16 * 2;
590                 break;
592         case 8:
593                 par->palette_sz = 256 * 2;
594                 break;
596         default:
597                 return -EINVAL;
598         }
600         return 0;
603 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
604                               unsigned blue, unsigned transp,
605                               struct fb_info *info)
607         struct da8xx_fb_par *par = info->par;
608         unsigned short *palette = (unsigned short *) par->v_palette_base;
609         u_short pal;
610         int update_hw = 0;
612         if (regno > 255)
613                 return 1;
615         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
616                 return 1;
618         if (info->var.bits_per_pixel == 8) {
619                 red >>= 4;
620                 green >>= 8;
621                 blue >>= 12;
623                 pal = (red & 0x0f00);
624                 pal |= (green & 0x00f0);
625                 pal |= (blue & 0x000f);
627                 if (palette[regno] != pal) {
628                         update_hw = 1;
629                         palette[regno] = pal;
630                 }
631         } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
632                 red >>= (16 - info->var.red.length);
633                 red <<= info->var.red.offset;
635                 green >>= (16 - info->var.green.length);
636                 green <<= info->var.green.offset;
638                 blue >>= (16 - info->var.blue.length);
639                 blue <<= info->var.blue.offset;
641                 par->pseudo_palette[regno] = red | green | blue;
643                 if (palette[0] != 0x4000) {
644                         update_hw = 1;
645                         palette[0] = 0x4000;
646                 }
647         } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
648                     ((info->var.bits_per_pixel == 24) && regno < 24)) {
649                 red >>= (24 - info->var.red.length);
650                 red <<= info->var.red.offset;
652                 green >>= (24 - info->var.green.length);
653                 green <<= info->var.green.offset;
655                 blue >>= (24 - info->var.blue.length);
656                 blue <<= info->var.blue.offset;
658                 par->pseudo_palette[regno] = red | green | blue;
660                 if (palette[0] != 0x4000) {
661                         update_hw = 1;
662                         palette[0] = 0x4000;
663                 }
664         }
666         /* Update the palette in the h/w as needed. */
667         if (update_hw)
668                 lcd_blit(LOAD_PALETTE, par);
670         return 0;
673 static void lcd_reset(struct da8xx_fb_par *par)
675         /* Disable the Raster if previously Enabled */
676         lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
678         /* DMA has to be disabled */
679         lcdc_write(0, LCD_DMA_CTRL_REG);
680         lcdc_write(0, LCD_RASTER_CTRL_REG);
682         if (lcd_revision == LCD_VERSION_2) {
683                 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
684                 /* Write 1 to reset */
685                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
686                 lcdc_write(0, LCD_CLK_RESET_REG);
687         }
690 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
692         unsigned int lcd_clk, div;
694         lcd_clk = clk_get_rate(par->lcdc_clk);
695         div = lcd_clk / par->pxl_clk;
697         /* Configure the LCD clock divisor. */
698         lcdc_write(LCD_CLK_DIVISOR(div) |
699                         (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
701         if (lcd_revision == LCD_VERSION_2)
702                 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
703                                 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
707 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
708                 struct da8xx_panel *panel)
710         u32 bpp;
711         int ret = 0;
713         lcd_reset(par);
715         /* Calculate the divider */
716         lcd_calc_clk_divider(par);
718         if (panel->invert_pxl_clk)
719                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
720                         LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
721         else
722                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
723                         ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
725         /* Configure the DMA burst size and fifo threshold. */
726         ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
727         if (ret < 0)
728                 return ret;
730         /* Configure the AC bias properties. */
731         lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
733         /* Configure the vertical and horizontal sync properties. */
734         lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
735         lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
737         /* Configure for disply */
738         ret = lcd_cfg_display(cfg);
739         if (ret < 0)
740                 return ret;
743         if ((QVGA != cfg->p_disp_panel->panel_type) &&
744                         (WVGA != cfg->p_disp_panel->panel_type))
745                 return -EINVAL;
747         if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
748             cfg->bpp >= cfg->p_disp_panel->min_bpp)
749                 bpp = cfg->bpp;
750         else
751                 bpp = cfg->p_disp_panel->max_bpp;
752         if (bpp == 12)
753                 bpp = 16;
754         ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
755                                 (unsigned int)panel->height, bpp,
756                                 cfg->raster_order);
757         if (ret < 0)
758                 return ret;
760         /* Configure FDD */
761         lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
762                        (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
764         return 0;
767 int register_vsync_cb(vsync_callback_t handler, void *arg, int idx)
769         if ((vsync_cb_handler == NULL) && (vsync_cb_arg == NULL)) {
770                 vsync_cb_handler = handler;
771                 vsync_cb_arg = arg;
772         } else {
773                 return -EEXIST;
774         }
776         return 0;
778 EXPORT_SYMBOL(register_vsync_cb);
780 int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx)
782         if ((vsync_cb_handler == handler) && (vsync_cb_arg == arg)) {
783                 vsync_cb_handler = NULL;
784                 vsync_cb_arg = NULL;
785         } else {
786                 return -ENXIO;
787         }
789         return 0;
791 EXPORT_SYMBOL(unregister_vsync_cb);
793 /* IRQ handler for version 2 of LCDC */
794 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
796         struct da8xx_fb_par *par = arg;
797         u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
798         struct device *dev = par->dev;
799         u32 reg_int;
801         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
802                 printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
803                 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
804                 lcdc_write(stat, LCD_MASKED_STAT_REG);
805                 lcd_enable_raster();
806         } else if (stat & LCD_PL_LOAD_DONE) {
807                 /*
808                  * Must disable raster before changing state of any control bit.
809                  * And also must be disabled before clearing the PL loading
810                  * interrupt via the following write to the status register. If
811                  * this is done after then one gets multiple PL done interrupts.
812                  */
813                 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
815                 lcdc_write(stat, LCD_MASKED_STAT_REG);
817                 /* Disable PL completion inerrupt */
818                 reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |
819                        (LCD_V2_PL_INT_ENA);
820                 lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);
822                 /* Setup and start data loading mode */
823                 lcd_blit(LOAD_DATA, par);
824         } else {
825                 lcdc_write(stat, LCD_MASKED_STAT_REG);
827                 if (stat & LCD_END_OF_FRAME0) {
828                         par->which_dma_channel_done = 0;
829                         lcdc_write(par->dma_start,
830                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
831                         lcdc_write(par->dma_end,
832                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
833                         par->vsync_flag = 1;
834                         wake_up_interruptible(&par->vsync_wait);
835                         if (vsync_cb_handler)
836                                 vsync_cb_handler(vsync_cb_arg);
837                 }
839                 if (stat & LCD_END_OF_FRAME1) {
840                         par->which_dma_channel_done = 1;
841                         lcdc_write(par->dma_start,
842                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
843                         lcdc_write(par->dma_end,
844                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
845                         par->vsync_flag = 1;
846                         wake_up_interruptible(&par->vsync_wait);
847                         if (vsync_cb_handler)
848                                 vsync_cb_handler(vsync_cb_arg);
849                 }
850         }
852         lcdc_write(0, LCD_END_OF_INT_IND_REG);
853         return IRQ_HANDLED;
856 /* IRQ handler for version 1 LCDC */
857 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
859         struct da8xx_fb_par *par = arg;
860         u32 stat = lcdc_read(LCD_STAT_REG);
861         u32 reg_ras;
863         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
864                 printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
865                 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
866                 clk_disable(par->lcdc_clk);
867                 lcdc_write(stat, LCD_STAT_REG);
868                 lcd_enable_raster();
869                 clk_enable(par->lcdc_clk);
870         } else if (stat & LCD_PL_LOAD_DONE) {
871                 /*
872                  * Must disable raster before changing state of any control bit.
873                  * And also must be disabled before clearing the PL loading
874                  * interrupt via the following write to the status register. If
875                  * this is done after then one gets multiple PL done interrupts.
876                  */
877                 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
879                 lcdc_write(stat, LCD_STAT_REG);
881                 /* Disable PL completion inerrupt */
882                 reg_ras  = lcdc_read(LCD_RASTER_CTRL_REG);
883                 reg_ras &= ~LCD_V1_PL_INT_ENA;
884                 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
886                 /* Setup and start data loading mode */
887                 lcd_blit(LOAD_DATA, par);
888         } else {
889                 lcdc_write(stat, LCD_STAT_REG);
891                 if (stat & LCD_END_OF_FRAME0) {
892                         lcdc_write(par->dma_start,
893                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
894                         lcdc_write(par->dma_end,
895                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
896                         par->vsync_flag = 1;
897                         wake_up_interruptible(&par->vsync_wait);
898                 }
900                 if (stat & LCD_END_OF_FRAME1) {
901                         lcdc_write(par->dma_start,
902                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
903                         lcdc_write(par->dma_end,
904                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
905                         par->vsync_flag = 1;
906                         wake_up_interruptible(&par->vsync_wait);
907                 }
908         }
910         return IRQ_HANDLED;
913 static int fb_check_var(struct fb_var_screeninfo *var,
914                         struct fb_info *info)
916         int err = 0;
918         switch (var->bits_per_pixel) {
919         case 1:
920         case 8:
921                 var->red.offset = 0;
922                 var->red.length = 8;
923                 var->green.offset = 0;
924                 var->green.length = 8;
925                 var->blue.offset = 0;
926                 var->blue.length = 8;
927                 var->transp.offset = 0;
928                 var->transp.length = 0;
929                 break;
930         case 4:
931                 var->red.offset = 0;
932                 var->red.length = 4;
933                 var->green.offset = 0;
934                 var->green.length = 4;
935                 var->blue.offset = 0;
936                 var->blue.length = 4;
937                 var->transp.offset = 0;
938                 var->transp.length = 0;
939                 break;
940         case 16:                /* RGB 565 */
941                 var->red.offset = 11;
942                 var->red.length = 5;
943                 var->green.offset = 5;
944                 var->green.length = 6;
945                 var->blue.offset = 0;
946                 var->blue.length = 5;
947                 var->transp.offset = 0;
948                 var->transp.length = 0;
949                 break;
950         case 24:
951                 var->red.offset = 16;
952                 var->red.length = 8;
953                 var->green.offset = 8;
954                 var->green.length = 8;
955                 var->blue.offset = 0;
956                 var->blue.length = 8;
957                 break;
958         case 32:
959                 var->transp.offset = 24;
960                 var->transp.length = 8;
961                 var->red.offset = 16;
962                 var->red.length = 8;
963                 var->green.offset = 8;
964                 var->green.length = 8;
965                 var->blue.offset = 0;
966                 var->blue.length = 8;
967                 break;
968         default:
969                 err = -EINVAL;
970         }
972         var->red.msb_right = 0;
973         var->green.msb_right = 0;
974         var->blue.msb_right = 0;
975         var->transp.msb_right = 0;
976         return err;
979 #ifdef CONFIG_CPU_FREQ
980 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
981                                      unsigned long val, void *data)
983         struct da8xx_fb_par *par;
985         par = container_of(nb, struct da8xx_fb_par, freq_transition);
986         if (val == CPUFREQ_POSTCHANGE) {
987                 if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) {
988                         lcd_disable_raster(WAIT_FOR_FRAME_DONE);
989                         lcd_calc_clk_divider(par);
990                         lcd_enable_raster();
991                 }
992         }
994         return 0;
997 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
999         par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
1001         return cpufreq_register_notifier(&par->freq_transition,
1002                                          CPUFREQ_TRANSITION_NOTIFIER);
1005 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
1007         cpufreq_unregister_notifier(&par->freq_transition,
1008                                     CPUFREQ_TRANSITION_NOTIFIER);
1010 #endif
1012 static int __devexit fb_remove(struct platform_device *dev)
1014         struct fb_info *info = dev_get_drvdata(&dev->dev);
1016         if (info) {
1017                 struct da8xx_fb_par *par = info->par;
1019 #ifdef CONFIG_CPU_FREQ
1020                 lcd_da8xx_cpufreq_deregister(par);
1021 #endif
1022                 if (par->panel_power_ctrl)
1023                         par->panel_power_ctrl(0);
1025                 lcd_disable_raster(WAIT_FOR_FRAME_DONE);
1026                 lcdc_write(0, LCD_RASTER_CTRL_REG);
1028                 /* disable DMA  */
1029                 lcdc_write(0, LCD_DMA_CTRL_REG);
1031                 unregister_framebuffer(info);
1032                 fb_dealloc_cmap(&info->cmap);
1033                 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1034                                   par->p_palette_base);
1035                 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
1036                                   par->vram_phys);
1037                 free_irq(par->irq, par);
1038                 pm_runtime_put_sync(&dev->dev);
1039                 pm_runtime_disable(&dev->dev);
1040                 framebuffer_release(info);
1041                 iounmap((void __iomem *)da8xx_fb_reg_base);
1042                 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
1044         }
1045         return 0;
1048 /*
1049  * Function to wait for vertical sync which for this LCD peripheral
1050  * translates into waiting for the current raster frame to complete.
1051  */
1052 static int fb_wait_for_vsync(struct fb_info *info)
1054         struct da8xx_fb_par *par = info->par;
1055         int ret;
1057         /*
1058          * Set flag to 0 and wait for isr to set to 1. It would seem there is a
1059          * race condition here where the ISR could have occurred just before or
1060          * just after this set. But since we are just coarsely waiting for
1061          * a frame to complete then that's OK. i.e. if the frame completed
1062          * just before this code executed then we have to wait another full
1063          * frame time but there is no way to avoid such a situation. On the
1064          * other hand if the frame completed just after then we don't need
1065          * to wait long at all. Either way we are guaranteed to return to the
1066          * user immediately after a frame completion which is all that is
1067          * required.
1068          */
1069         par->vsync_flag = 0;
1070         ret = wait_event_interruptible_timeout(par->vsync_wait,
1071                                                par->vsync_flag != 0,
1072                                                par->vsync_timeout);
1073         if (ret < 0)
1074                 return ret;
1075         if (ret == 0)
1076                 return -ETIMEDOUT;
1078         if (par->panel_power_ctrl) {
1079                 /* Switch off panel power and backlight */
1080                 par->panel_power_ctrl(0);
1082                 /* Switch on panel power and backlight */
1083                 par->panel_power_ctrl(1);
1084         }
1086         return 0;
1089 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
1090                           unsigned long arg)
1092         struct lcd_sync_arg sync_arg;
1094         switch (cmd) {
1095         case FBIOGET_CONTRAST:
1096         case FBIOPUT_CONTRAST:
1097         case FBIGET_BRIGHTNESS:
1098         case FBIPUT_BRIGHTNESS:
1099         case FBIGET_COLOR:
1100         case FBIPUT_COLOR:
1101                 return -ENOTTY;
1102         case FBIPUT_HSYNC:
1103                 if (copy_from_user(&sync_arg, (char *)arg,
1104                                 sizeof(struct lcd_sync_arg)))
1105                         return -EFAULT;
1106                 lcd_cfg_horizontal_sync(sync_arg.back_porch,
1107                                         sync_arg.pulse_width,
1108                                         sync_arg.front_porch);
1109                 break;
1110         case FBIPUT_VSYNC:
1111                 if (copy_from_user(&sync_arg, (char *)arg,
1112                                 sizeof(struct lcd_sync_arg)))
1113                         return -EFAULT;
1114                 lcd_cfg_vertical_sync(sync_arg.back_porch,
1115                                         sync_arg.pulse_width,
1116                                         sync_arg.front_porch);
1117                 break;
1118         case FBIO_WAITFORVSYNC:
1119                 return fb_wait_for_vsync(info);
1120         default:
1121                 return -EINVAL;
1122         }
1123         return 0;
1126 static int cfb_blank(int blank, struct fb_info *info)
1128         struct da8xx_fb_par *par = info->par;
1129         int ret = 0;
1131         if (par->blank == blank)
1132                 return 0;
1134         par->blank = blank;
1135         switch (blank) {
1136         case FB_BLANK_UNBLANK:
1137                 if (par->panel_power_ctrl)
1138                         par->panel_power_ctrl(1);
1140                 lcd_enable_raster();
1141                 break;
1142         case FB_BLANK_POWERDOWN:
1143                 if (par->panel_power_ctrl)
1144                         par->panel_power_ctrl(0);
1146                 lcd_disable_raster(WAIT_FOR_FRAME_DONE);
1147                 break;
1148         default:
1149                 ret = -EINVAL;
1150         }
1152         return ret;
1155 /*
1156  * Set new x,y offsets in the virtual display for the visible area and switch
1157  * to the new mode.
1158  */
1159 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1160                              struct fb_info *fbi)
1162         int ret = 0;
1163         struct fb_var_screeninfo new_var;
1164         struct da8xx_fb_par         *par = fbi->par;
1165         struct fb_fix_screeninfo    *fix = &fbi->fix;
1166         unsigned int end;
1167         unsigned int start;
1168         unsigned long irq_flags;
1170         if (var->xoffset != fbi->var.xoffset ||
1171                         var->yoffset != fbi->var.yoffset) {
1172                 memcpy(&new_var, &fbi->var, sizeof(new_var));
1173                 new_var.xoffset = var->xoffset;
1174                 new_var.yoffset = var->yoffset;
1175                 if (fb_check_var(&new_var, fbi))
1176                         ret = -EINVAL;
1177                 else {
1178                         memcpy(&fbi->var, &new_var, sizeof(new_var));
1180                         start   = fix->smem_start +
1181                                 new_var.yoffset * fix->line_length +
1182                                 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1183                         end     = start + fbi->var.yres * fix->line_length - 1;
1184                         par->dma_start  = start;
1185                         par->dma_end    = end;
1186                         spin_lock_irqsave(&par->lock_for_chan_update,
1187                                         irq_flags);
1188                         if (par->which_dma_channel_done == 0) {
1189                                 lcdc_write(par->dma_start,
1190                                            LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1191                                 lcdc_write(par->dma_end,
1192                                            LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1193                         } else if (par->which_dma_channel_done == 1) {
1194                                 lcdc_write(par->dma_start,
1195                                            LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1196                                 lcdc_write(par->dma_end,
1197                                            LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1198                         }
1199                         spin_unlock_irqrestore(&par->lock_for_chan_update,
1200                                         irq_flags);
1201                 }
1202         }
1204         return ret;
1207 static struct fb_ops da8xx_fb_ops = {
1208         .owner = THIS_MODULE,
1209         .fb_check_var = fb_check_var,
1210         .fb_setcolreg = fb_setcolreg,
1211         .fb_pan_display = da8xx_pan_display,
1212         .fb_ioctl = fb_ioctl,
1213         .fb_fillrect = cfb_fillrect,
1214         .fb_copyarea = cfb_copyarea,
1215         .fb_imageblit = cfb_imageblit,
1216         .fb_blank = cfb_blank,
1217 };
1219 static int __devinit fb_probe(struct platform_device *device)
1221         struct da8xx_lcdc_platform_data *fb_pdata =
1222                                                 device->dev.platform_data;
1223         struct lcd_ctrl_config *lcd_cfg;
1224         struct da8xx_panel *lcdc_info;
1225         struct fb_info *da8xx_fb_info;
1226         struct clk *fb_clk = NULL;
1227         struct da8xx_fb_par *par;
1228         resource_size_t len;
1229         int ret, i;
1231         if (fb_pdata == NULL) {
1232                 dev_err(&device->dev, "Can not get platform data\n");
1233                 return -ENOENT;
1234         }
1236         lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1237         if (!lcdc_regs) {
1238                 dev_err(&device->dev,
1239                         "Can not get memory resource for LCD controller\n");
1240                 return -ENOENT;
1241         }
1243         len = resource_size(lcdc_regs);
1245         lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
1246         if (!lcdc_regs)
1247                 return -EBUSY;
1249         da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
1250         if (!da8xx_fb_reg_base) {
1251                 ret = -EBUSY;
1252                 goto err_request_mem;
1253         }
1255         fb_clk = clk_get(&device->dev, NULL);
1256         if (IS_ERR(fb_clk)) {
1257                 dev_err(&device->dev, "Can not get device clock\n");
1258                 ret = -ENODEV;
1259                 goto err_ioremap;
1260         }
1262         pm_runtime_irq_safe(&device->dev);
1263         pm_runtime_enable(&device->dev);
1264         pm_runtime_get_sync(&device->dev);
1267         /* Determine LCD IP Version */
1268         switch (lcdc_read(LCD_PID_REG)) {
1269         case 0x4C100102:
1270                 lcd_revision = LCD_VERSION_1;
1271                 break;
1272         case 0x4F200800:
1273         case 0x4F201000:
1274                 lcd_revision = LCD_VERSION_2;
1275                 break;
1276         default:
1277                 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1278                                 "defaulting to LCD revision 1\n",
1279                                 lcdc_read(LCD_PID_REG));
1280                 lcd_revision = LCD_VERSION_1;
1281                 break;
1282         }
1284         for (i = 0, lcdc_info = known_lcd_panels;
1285                 i < ARRAY_SIZE(known_lcd_panels);
1286                 i++, lcdc_info++) {
1287                 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1288                         break;
1289         }
1291         if (i == ARRAY_SIZE(known_lcd_panels)) {
1292                 dev_err(&device->dev, "GLCD: No valid panel found\n");
1293                 ret = -ENODEV;
1294                 goto err_pm_runtime_disable;
1295         } else
1296                 dev_info(&device->dev, "GLCD: Found %s panel\n",
1297                                         fb_pdata->type);
1299         lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1301         da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1302                                         &device->dev);
1303         if (!da8xx_fb_info) {
1304                 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1305                 ret = -ENOMEM;
1306                 goto err_pm_runtime_disable;
1307         }
1309         par = da8xx_fb_info->par;
1310         par->dev = &device->dev;
1311         par->lcdc_clk = fb_clk;
1312 #ifdef CONFIG_CPU_FREQ
1313         par->lcd_fck_rate = clk_get_rate(fb_clk);
1314 #endif
1315         par->pxl_clk = lcdc_info->pxl_clk;
1316         if (fb_pdata->panel_power_ctrl) {
1317                 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1318                 par->panel_power_ctrl(1);
1319         }
1321         if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
1322                 dev_err(&device->dev, "lcd_init failed\n");
1323                 ret = -EFAULT;
1324                 goto err_release_fb;
1325         }
1327         /* allocate frame buffer */
1328         par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
1329         par->vram_size = PAGE_ALIGN(par->vram_size/8);
1330         par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1332         par->vram_virt = dma_alloc_coherent(NULL,
1333                                             par->vram_size,
1334                                             (resource_size_t *) &par->vram_phys,
1335                                             GFP_KERNEL | GFP_DMA);
1336         if (!par->vram_virt) {
1337                 dev_err(&device->dev,
1338                         "GLCD: kmalloc for frame buffer failed\n");
1339                 ret = -EINVAL;
1340                 goto err_release_fb;
1341         }
1343         da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1344         da8xx_fb_fix.smem_start    = par->vram_phys;
1345         da8xx_fb_fix.smem_len      = par->vram_size;
1346         da8xx_fb_fix.line_length   = (lcdc_info->width * lcd_cfg->bpp) / 8;
1348         par->dma_start = par->vram_phys;
1349         par->dma_end   = par->dma_start + lcdc_info->height *
1350                 da8xx_fb_fix.line_length - 1;
1352         /* allocate palette buffer */
1353         par->v_palette_base = dma_alloc_coherent(NULL,
1354                                                PALETTE_SIZE,
1355                                                (resource_size_t *)
1356                                                &par->p_palette_base,
1357                                                GFP_KERNEL | GFP_DMA);
1358         if (!par->v_palette_base) {
1359                 dev_err(&device->dev,
1360                         "GLCD: kmalloc for palette buffer failed\n");
1361                 ret = -EINVAL;
1362                 goto err_release_fb_mem;
1363         }
1364         memset(par->v_palette_base, 0, PALETTE_SIZE);
1366         par->irq = platform_get_irq(device, 0);
1367         if (par->irq < 0) {
1368                 ret = -ENOENT;
1369                 goto err_release_pl_mem;
1370         }
1372         /* Initialize par */
1373         da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
1375         da8xx_fb_var.xres = lcdc_info->width;
1376         da8xx_fb_var.xres_virtual = lcdc_info->width;
1378         da8xx_fb_var.yres         = lcdc_info->height;
1379         da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
1381         da8xx_fb_var.grayscale =
1382             lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
1383         da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1385         da8xx_fb_var.hsync_len = lcdc_info->hsw;
1386         da8xx_fb_var.vsync_len = lcdc_info->vsw;
1388         da8xx_fb_var.right_margin = lcdc_info->hfp;
1389         da8xx_fb_var.left_margin  = lcdc_info->hbp;
1390         da8xx_fb_var.lower_margin = lcdc_info->vfp;
1391         da8xx_fb_var.upper_margin = lcdc_info->vbp;
1393         /* Initialize fbinfo */
1394         da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1395         da8xx_fb_info->fix = da8xx_fb_fix;
1396         da8xx_fb_info->var = da8xx_fb_var;
1397         da8xx_fb_info->fbops = &da8xx_fb_ops;
1398         da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1399         da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1400                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1402         ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1403         if (ret)
1404                 goto err_release_pl_mem;
1405         da8xx_fb_info->cmap.len = par->palette_sz;
1407         /* initialize var_screeninfo */
1408         da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1409         fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1411         dev_set_drvdata(&device->dev, da8xx_fb_info);
1413         /* initialize the vsync wait queue */
1414         init_waitqueue_head(&par->vsync_wait);
1415         par->vsync_timeout = HZ / 5;
1416         par->which_dma_channel_done = -1;
1417         spin_lock_init(&par->lock_for_chan_update);
1419         /* Register the Frame Buffer  */
1420         if (register_framebuffer(da8xx_fb_info) < 0) {
1421                 dev_err(&device->dev,
1422                         "GLCD: Frame Buffer Registration Failed!\n");
1423                 ret = -EINVAL;
1424                 goto err_dealloc_cmap;
1425         }
1427 #ifdef CONFIG_CPU_FREQ
1428         ret = lcd_da8xx_cpufreq_register(par);
1429         if (ret) {
1430                 dev_err(&device->dev, "failed to register cpufreq\n");
1431                 goto err_cpu_freq;
1432         }
1433 #endif
1435         if (lcd_revision == LCD_VERSION_1)
1436                 lcdc_irq_handler = lcdc_irq_handler_rev01;
1437         else
1438                 lcdc_irq_handler = lcdc_irq_handler_rev02;
1440         ret = request_irq(par->irq, lcdc_irq_handler, 0,
1441                         DRIVER_NAME, par);
1442         if (ret)
1443                 goto irq_freq;
1444         return 0;
1446 irq_freq:
1447 #ifdef CONFIG_CPU_FREQ
1448         lcd_da8xx_cpufreq_deregister(par);
1449 err_cpu_freq:
1450 #endif
1451         unregister_framebuffer(da8xx_fb_info);
1453 err_dealloc_cmap:
1454         fb_dealloc_cmap(&da8xx_fb_info->cmap);
1456 err_release_pl_mem:
1457         dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1458                           par->p_palette_base);
1460 err_release_fb_mem:
1461         dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1463 err_release_fb:
1464         framebuffer_release(da8xx_fb_info);
1466 err_pm_runtime_disable:
1467         pm_runtime_put_sync(&device->dev);
1468         pm_runtime_disable(&device->dev);
1470 err_ioremap:
1472         iounmap((void __iomem *)da8xx_fb_reg_base);
1474 err_request_mem:
1475         release_mem_region(lcdc_regs->start, len);
1477         return ret;
1480 #ifdef CONFIG_PM
1482 struct lcdc_context {
1483         u32 clk_enable;
1484         u32 ctrl;
1485         u32 dma_ctrl;
1486         u32 raster_timing_0;
1487         u32 raster_timing_1;
1488         u32 raster_timing_2;
1489         u32 int_enable_set;
1490         u32 dma_frm_buf_base_addr_0;
1491         u32 dma_frm_buf_ceiling_addr_0;
1492         u32 dma_frm_buf_base_addr_1;
1493         u32 dma_frm_buf_ceiling_addr_1;
1494         u32 raster_ctrl;
1495 } reg_context;
1497 static void lcd_context_save(void)
1499         reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG);
1500         reg_context.ctrl = lcdc_read(LCD_CTRL_REG);
1501         reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG);
1502         reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG);
1503         reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG);
1504         reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG);
1505         reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG);
1506         reg_context.dma_frm_buf_base_addr_0 =
1507                 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1508         reg_context.dma_frm_buf_ceiling_addr_0 =
1509                 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1510         reg_context.dma_frm_buf_base_addr_1 =
1511                 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1512         reg_context.dma_frm_buf_ceiling_addr_1 =
1513                 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1514         reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG) &
1515                 ~LCD_RASTER_ENABLE;
1516         return;
1519 static void lcd_context_restore(void)
1521         lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG);
1522         lcdc_write(reg_context.ctrl, LCD_CTRL_REG);
1523         lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG);
1524         lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG);
1525         lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG);
1526         lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG);
1527         lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG);
1528         lcdc_write(reg_context.dma_frm_buf_base_addr_0,
1529                         LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1530         lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0,
1531                         LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1532         lcdc_write(reg_context.dma_frm_buf_base_addr_1,
1533                         LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1534         lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1,
1535                         LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1536         lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG);
1537         return;
1540 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1542         struct fb_info *info = platform_get_drvdata(dev);
1543         struct da8xx_fb_par *par = info->par;
1545         console_lock();
1546         if (par->panel_power_ctrl)
1547                 par->panel_power_ctrl(0);
1549         fb_set_suspend(info, 1);
1550         lcd_context_save();
1551         lcd_disable_raster(WAIT_FOR_FRAME_DONE);
1552         msleep(10);
1554         pm_runtime_put(&dev->dev);
1555         console_unlock();
1557         return 0;
1559 static int fb_resume(struct platform_device *dev)
1561         struct fb_info *info = platform_get_drvdata(dev);
1562         struct da8xx_fb_par *par = info->par;
1564         console_lock();
1566         pm_runtime_get_sync(&dev->dev);
1568         msleep(1);
1569         lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
1570         msleep(10);
1571         lcdc_write(0, LCD_CLK_RESET_REG);
1572         msleep(1);
1574         lcd_context_restore();
1575         lcd_enable_raster();
1577         if (par->panel_power_ctrl)
1578                 par->panel_power_ctrl(1);
1580         fb_set_suspend(info, 0);
1581         console_unlock();
1583         return 0;
1585 #else
1586 #define fb_suspend NULL
1587 #define fb_resume NULL
1588 #endif
1590 static struct platform_driver da8xx_fb_driver = {
1591         .probe = fb_probe,
1592         .remove = __devexit_p(fb_remove),
1593         .suspend = fb_suspend,
1594         .resume = fb_resume,
1595         .driver = {
1596                    .name = DRIVER_NAME,
1597                    .owner = THIS_MODULE,
1598                    },
1599 };
1601 static int __init da8xx_fb_init(void)
1603         return platform_driver_register(&da8xx_fb_driver);
1606 static void __exit da8xx_fb_cleanup(void)
1608         platform_driver_unregister(&da8xx_fb_driver);
1611 module_init(da8xx_fb_init);
1612 module_exit(da8xx_fb_cleanup);
1614 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1615 MODULE_AUTHOR("Texas Instruments");
1616 MODULE_LICENSE("GPL");