video: da8xx-fb: Add debug message on sync and underflow error
[sitara-epos/sitara-epos-kernel.git] / drivers / video / da8xx-fb.c
1 /*
2  * Copyright (C) 2008-2009 MontaVista Software Inc.
3  * Copyright (C) 2008-2009 Texas Instruments Inc
4  *
5  * Based on the LCD driver for TI Avalanche processors written by
6  * Ajay Singh and Shalom Hai.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option)any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21  */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/fb.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/interrupt.h>
30 #include <linux/clk.h>
31 #include <linux/cpufreq.h>
32 #include <linux/console.h>
33 #include <linux/spinlock.h>
34 #include <linux/slab.h>
35 #include <video/da8xx-fb.h>
36 #include <asm/mach-types.h>
38 #define DRIVER_NAME "da8xx_lcdc"
40 #define LCD_VERSION_1   1
41 #define LCD_VERSION_2   2
43 /* LCD Status Register */
44 #define LCD_END_OF_FRAME1               BIT(9)
45 #define LCD_END_OF_FRAME0               BIT(8)
46 #define LCD_PL_LOAD_DONE                BIT(6)
47 #define LCD_FIFO_UNDERFLOW              BIT(5)
48 #define LCD_SYNC_LOST                   BIT(2)
50 /* LCD DMA Control Register */
51 #define LCD_DMA_BURST_SIZE(x)           ((x) << 4)
52 #define LCD_DMA_BURST_1                 0x0
53 #define LCD_DMA_BURST_2                 0x1
54 #define LCD_DMA_BURST_4                 0x2
55 #define LCD_DMA_BURST_8                 0x3
56 #define LCD_DMA_BURST_16                0x4
57 #define LCD_V1_END_OF_FRAME_INT_ENA     BIT(2)
58 #define LCD_V2_END_OF_FRAME0_INT_ENA    BIT(8)
59 #define LCD_V2_END_OF_FRAME1_INT_ENA    BIT(9)
60 #define LCD_DUAL_FRAME_BUFFER_ENABLE    BIT(0)
62 /* LCD Control Register */
63 #define LCD_CLK_DIVISOR(x)              ((x) << 8)
64 #define LCD_RASTER_MODE                 0x01
66 /* LCD Raster Control Register */
67 #define LCD_PALETTE_LOAD_MODE(x)        ((x) << 20)
68 #define PALETTE_AND_DATA                0x00
69 #define PALETTE_ONLY                    0x01
70 #define DATA_ONLY                       0x02
72 #define LCD_MONO_8BIT_MODE              BIT(9)
73 #define LCD_RASTER_ORDER                BIT(8)
74 #define LCD_TFT_MODE                    BIT(7)
75 #define LCD_V1_UNDERFLOW_INT_ENA        BIT(6)
76 #define LCD_V2_UNDERFLOW_INT_ENA        BIT(5)
77 #define LCD_V1_PL_INT_ENA               BIT(4)
78 #define LCD_V2_PL_INT_ENA               BIT(6)
79 #define LCD_MONOCHROME_MODE             BIT(1)
80 #define LCD_RASTER_ENABLE               BIT(0)
81 #define LCD_TFT_ALT_ENABLE              BIT(23)
82 #define LCD_STN_565_ENABLE              BIT(24)
83 #define LCD_V2_DMA_CLK_EN               BIT(2)
84 #define LCD_V2_LIDD_CLK_EN              BIT(1)
85 #define LCD_V2_CORE_CLK_EN              BIT(0)
86 #define LCD_V2_LPP_B10                  26
87 #define LCD_V2_TFT_24BPP_MODE           BIT(25)
88 #define LCD_V2_TFT_24BPP_UNPACK         BIT(26)
90 /* LCD Raster Timing 2 Register */
91 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
92 #define LCD_AC_BIAS_FREQUENCY(x)                ((x) << 8)
93 #define LCD_SYNC_CTRL                           BIT(25)
94 #define LCD_SYNC_EDGE                           BIT(24)
95 #define LCD_INVERT_PIXEL_CLOCK                  BIT(22)
96 #define LCD_INVERT_LINE_CLOCK                   BIT(21)
97 #define LCD_INVERT_FRAME_CLOCK                  BIT(20)
99 /* LCD Block */
100 #define  LCD_PID_REG                            0x0
101 #define  LCD_CTRL_REG                           0x4
102 #define  LCD_STAT_REG                           0x8
103 #define  LCD_RASTER_CTRL_REG                    0x28
104 #define  LCD_RASTER_TIMING_0_REG                0x2C
105 #define  LCD_RASTER_TIMING_1_REG                0x30
106 #define  LCD_RASTER_TIMING_2_REG                0x34
107 #define  LCD_DMA_CTRL_REG                       0x40
108 #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG        0x44
109 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG     0x48
110 #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG        0x4C
111 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG     0x50
113 /* Interrupt Registers available only in Version 2 */
114 #define  LCD_RAW_STAT_REG                       0x58
115 #define  LCD_MASKED_STAT_REG                    0x5c
116 #define  LCD_INT_ENABLE_SET_REG                 0x60
117 #define  LCD_INT_ENABLE_CLR_REG                 0x64
118 #define  LCD_END_OF_INT_IND_REG                 0x68
120 /* Clock registers available only on Version 2 */
121 #define  LCD_CLK_ENABLE_REG                     0x6c
122 #define  LCD_CLK_RESET_REG                      0x70
123 #define  LCD_CLK_MAIN_RESET                     BIT(3)
125 #define LCD_NUM_BUFFERS 2
127 #define WSI_TIMEOUT     50
128 #define PALETTE_SIZE    256
129 #define LEFT_MARGIN     64
130 #define RIGHT_MARGIN    64
131 #define UPPER_MARGIN    32
132 #define LOWER_MARGIN    32
134 static resource_size_t da8xx_fb_reg_base;
135 static struct resource *lcdc_regs;
136 static unsigned int lcd_revision;
137 static irq_handler_t lcdc_irq_handler;
139 static inline unsigned int lcdc_read(unsigned int addr)
141         return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
144 static inline void lcdc_write(unsigned int val, unsigned int addr)
146         __raw_writel(val, da8xx_fb_reg_base + (addr));
149 struct da8xx_fb_par {
150         resource_size_t p_palette_base;
151         unsigned char *v_palette_base;
152         dma_addr_t              vram_phys;
153         unsigned long           vram_size;
154         void                    *vram_virt;
155         unsigned int            dma_start;
156         unsigned int            dma_end;
157         struct clk *lcdc_clk;
158         int irq;
159         unsigned long pseudo_palette[32];
160         unsigned int palette_sz;
161         unsigned int pxl_clk;
162         int blank;
163         wait_queue_head_t       vsync_wait;
164         int                     vsync_flag;
165         int                     vsync_timeout;
166         spinlock_t              lock_for_chan_update;
168         /*
169          * LCDC has 2 ping pong DMA channels, channel 0
170          * and channel 1.
171          */
172         unsigned int            which_dma_channel_done;
173 #ifdef CONFIG_CPU_FREQ
174         struct notifier_block   freq_transition;
175 #endif
176         void (*panel_power_ctrl)(int);
177 };
179 /* Variable Screen Information */
180 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
181         .xoffset = 0,
182         .yoffset = 0,
183         .transp = {0, 0, 0},
184         .nonstd = 0,
185         .activate = 0,
186         .height = -1,
187         .width = -1,
188         .pixclock = 33333,/*Pico Sec*/
189         .accel_flags = 0,
190         .left_margin = LEFT_MARGIN,
191         .right_margin = RIGHT_MARGIN,
192         .upper_margin = UPPER_MARGIN,
193         .lower_margin = LOWER_MARGIN,
194         .sync = 0,
195         .vmode = FB_VMODE_NONINTERLACED
196 };
198 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
199         .id = "DA8xx FB Drv",
200         .type = FB_TYPE_PACKED_PIXELS,
201         .type_aux = 0,
202         .visual = FB_VISUAL_PSEUDOCOLOR,
203         .xpanstep = 0,
204         .ypanstep = 1,
205         .ywrapstep = 0,
206         .accel = FB_ACCEL_NONE
207 };
209 struct da8xx_panel {
210         const char      name[25];       /* Full name <vendor>_<model> */
211         unsigned short  width;
212         unsigned short  height;
213         int             hfp;            /* Horizontal front porch */
214         int             hbp;            /* Horizontal back porch */
215         int             hsw;            /* Horizontal Sync Pulse Width */
216         int             vfp;            /* Vertical front porch */
217         int             vbp;            /* Vertical back porch */
218         int             vsw;            /* Vertical Sync Pulse Width */
219         unsigned int    pxl_clk;        /* Pixel clock */
220         unsigned char   invert_pxl_clk; /* Invert Pixel clock */
221 };
223 static vsync_callback_t vsync_cb_handler;
224 static void *vsync_cb_arg;
226 static struct da8xx_panel known_lcd_panels[] = {
227         /* Sharp LCD035Q3DG01 */
228         [0] = {
229                 .name = "Sharp_LCD035Q3DG01",
230                 .width = 320,
231                 .height = 240,
232                 .hfp = 8,
233                 .hbp = 6,
234                 .hsw = 0,
235                 .vfp = 2,
236                 .vbp = 2,
237                 .vsw = 0,
238                 .pxl_clk = 4608000,
239                 .invert_pxl_clk = 1,
240         },
241         /* Sharp LK043T1DG01 */
242         [1] = {
243                 .name = "Sharp_LK043T1DG01",
244                 .width = 480,
245                 .height = 272,
246                 .hfp = 2,
247                 .hbp = 2,
248                 .hsw = 41,
249                 .vfp = 3,
250                 .vbp = 3,
251                 .vsw = 10,
252                 .pxl_clk = 7833600,
253                 .invert_pxl_clk = 0,
254         },
255         /* ThreeFive S9700RTWV35TR */
256         [2] = {
257                 .name = "TFC_S9700RTWV35TR_01B",
258                 .width = 800,
259                 .height = 480,
260                 .hfp = 39,
261                 .hbp = 39,
262                 .hsw = 47,
263                 .vfp = 13,
264                 .vbp = 29,
265                 .vsw = 2,
266                 .pxl_clk = 30000000,
267                 .invert_pxl_clk = 0,
268         },
269 };
271 /* Enable the Raster Engine of the LCD Controller */
272 static inline void lcd_enable_raster(void)
274         u32 reg;
276         /* Bring LCDC out of reset */
277         if (lcd_revision == LCD_VERSION_2)
278                 lcdc_write(0, LCD_CLK_RESET_REG);
280         reg = lcdc_read(LCD_RASTER_CTRL_REG);
281         if (!(reg & LCD_RASTER_ENABLE))
282                 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
285 /* Disable the Raster Engine of the LCD Controller */
286 static inline void lcd_disable_raster(void)
288         u32 reg;
290         reg = lcdc_read(LCD_RASTER_CTRL_REG);
291         if (reg & LCD_RASTER_ENABLE)
292                 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
294         if (lcd_revision == LCD_VERSION_2)
295                 /* Write 1 to reset LCDC */
296                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
299 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
301         u32 start;
302         u32 end;
303         u32 reg_ras;
304         u32 reg_dma;
305         u32 reg_int;
307         /* init reg to clear PLM (loading mode) fields */
308         reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
309         reg_ras &= ~(3 << 20);
311         reg_dma  = lcdc_read(LCD_DMA_CTRL_REG);
313         if (load_mode == LOAD_DATA) {
314                 start    = par->dma_start;
315                 end      = par->dma_end;
317                 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
318                 if (lcd_revision == LCD_VERSION_1) {
319                         reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
320                 } else {
321                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
322                                 LCD_V2_END_OF_FRAME0_INT_ENA |
323                                 LCD_V2_END_OF_FRAME1_INT_ENA;
324                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
325                 }
326                 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
328                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
329                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
330                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
331                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
332         } else if (load_mode == LOAD_PALETTE) {
333                 start    = par->p_palette_base;
334                 end      = start + par->palette_sz - 1;
336                 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
338                 if (lcd_revision == LCD_VERSION_1) {
339                         reg_ras |= LCD_V1_PL_INT_ENA;
340                 } else {
341                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
342                                 LCD_V2_PL_INT_ENA;
343                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
344                 }
346                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
347                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
348         }
350         lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
351         lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
353         /*
354          * The Raster enable bit must be set after all other control fields are
355          * set.
356          */
357         lcd_enable_raster();
360 /* Configure the Burst Size and fifo threhold of DMA */
361 static int lcd_cfg_dma(int burst_size,  int fifo_th)
363         u32 reg;
365         reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
366         switch (burst_size) {
367         case 1:
368                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
369                 break;
370         case 2:
371                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
372                 break;
373         case 4:
374                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
375                 break;
376         case 8:
377                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
378                 break;
379         case 16:
380                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
381                 break;
382         default:
383                 return -EINVAL;
384         }
386         reg |= (fifo_th << 8);
388         lcdc_write(reg, LCD_DMA_CTRL_REG);
390         return 0;
393 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
395         u32 reg;
397         /* Set the AC Bias Period and Number of Transisitons per Interrupt */
398         reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
399         reg |= LCD_AC_BIAS_FREQUENCY(period) |
400                 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
401         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
404 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
405                 int front_porch)
407         u32 reg;
409         reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
410         reg |= ((back_porch & 0xff) << 24)
411             | ((front_porch & 0xff) << 16)
412             | ((pulse_width & 0x3f) << 10);
413         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
416 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
417                 int front_porch)
419         u32 reg;
421         reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
422         reg |= ((back_porch & 0xff) << 24)
423             | ((front_porch & 0xff) << 16)
424             | ((pulse_width & 0x3f) << 10);
425         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
428 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
430         u32 reg;
431         u32 reg_int;
433         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
434                                                 LCD_MONO_8BIT_MODE |
435                                                 LCD_MONOCHROME_MODE);
437         switch (cfg->p_disp_panel->panel_shade) {
438         case MONOCHROME:
439                 reg |= LCD_MONOCHROME_MODE;
440                 if (cfg->mono_8bit_mode)
441                         reg |= LCD_MONO_8BIT_MODE;
442                 break;
443         case COLOR_ACTIVE:
444                 reg |= LCD_TFT_MODE;
445                 if (cfg->tft_alt_mode)
446                         reg |= LCD_TFT_ALT_ENABLE;
447                 break;
449         case COLOR_PASSIVE:
450                 if (cfg->stn_565_mode)
451                         reg |= LCD_STN_565_ENABLE;
452                 break;
454         default:
455                 return -EINVAL;
456         }
458         /* enable additional interrupts here */
459         if (lcd_revision == LCD_VERSION_1) {
460                 reg |= LCD_V1_UNDERFLOW_INT_ENA;
461         } else {
462                 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
463                         LCD_V2_UNDERFLOW_INT_ENA;
464                 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
465         }
467         lcdc_write(reg, LCD_RASTER_CTRL_REG);
469         reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
471         if (cfg->sync_ctrl)
472                 reg |= LCD_SYNC_CTRL;
473         else
474                 reg &= ~LCD_SYNC_CTRL;
476         if (cfg->sync_edge)
477                 reg |= LCD_SYNC_EDGE;
478         else
479                 reg &= ~LCD_SYNC_EDGE;
481         if (cfg->invert_line_clock)
482                 reg |= LCD_INVERT_LINE_CLOCK;
483         else
484                 reg &= ~LCD_INVERT_LINE_CLOCK;
486         if (cfg->invert_frm_clock)
487                 reg |= LCD_INVERT_FRAME_CLOCK;
488         else
489                 reg &= ~LCD_INVERT_FRAME_CLOCK;
491         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
493         return 0;
496 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
497                 u32 bpp, u32 raster_order)
499         u32 reg;
501         /* Set the Panel Width */
502         /* Pixels per line = (PPL + 1)*16 */
503         if (lcd_revision == LCD_VERSION_1) {
504                 /*
505                  * 0x3F in bits 4..9 gives max horizontal resolution = 1024
506                  * pixels.
507                  */
508                 width &= 0x3f0;
509         } else {
510                 /*
511                  * 0x7F in bits 4..10 gives max horizontal resolution = 2048
512                  * pixels.
513                  */
514                 width &= 0x7f0;
515         }
517         reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
518         reg &= 0xfffffc00;
519         if (lcd_revision == LCD_VERSION_1) {
520                 reg |= ((width >> 4) - 1) << 4;
521         } else {
522                 width = (width >> 4) - 1;
523                 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
524         }
525         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
527         /* Set the Panel Height */
528         /* Set bits 9:0 of Lines Per Pixel */
529         reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
530         reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
531         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
533         /* Set bit 10 of Lines Per Pixel */
534         if (lcd_revision == LCD_VERSION_2) {
535                 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
536                 reg |= ((height - 1) & 0x400) << 16;
537                 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
538         }
540         /* Set the Raster Order of the Frame Buffer */
541         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
542         if (raster_order)
543                 reg |= LCD_RASTER_ORDER;
545         if (bpp == 24)
546                 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
547         else if (bpp == 32)
548                 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
549                                 | LCD_V2_TFT_24BPP_UNPACK);
551         lcdc_write(reg, LCD_RASTER_CTRL_REG);
553         switch (bpp) {
554         case 1:
555         case 2:
556         case 4:
557         case 16:
558         case 24:
559         case 32:
560                 par->palette_sz = 16 * 2;
561                 break;
563         case 8:
564                 par->palette_sz = 256 * 2;
565                 break;
567         default:
568                 return -EINVAL;
569         }
571         return 0;
574 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
575                               unsigned blue, unsigned transp,
576                               struct fb_info *info)
578         struct da8xx_fb_par *par = info->par;
579         unsigned short *palette = (unsigned short *) par->v_palette_base;
580         u_short pal;
581         int update_hw = 0;
583         if (regno > 255)
584                 return 1;
586         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
587                 return 1;
589         if (info->var.bits_per_pixel == 8) {
590                 red >>= 4;
591                 green >>= 8;
592                 blue >>= 12;
594                 pal = (red & 0x0f00);
595                 pal |= (green & 0x00f0);
596                 pal |= (blue & 0x000f);
598                 if (palette[regno] != pal) {
599                         update_hw = 1;
600                         palette[regno] = pal;
601                 }
602         } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
603                 red >>= (16 - info->var.red.length);
604                 red <<= info->var.red.offset;
606                 green >>= (16 - info->var.green.length);
607                 green <<= info->var.green.offset;
609                 blue >>= (16 - info->var.blue.length);
610                 blue <<= info->var.blue.offset;
612                 par->pseudo_palette[regno] = red | green | blue;
614                 if (palette[0] != 0x4000) {
615                         update_hw = 1;
616                         palette[0] = 0x4000;
617                 }
618         } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
619                     ((info->var.bits_per_pixel == 24) && regno < 24)) {
620                 red >>= (24 - info->var.red.length);
621                 red <<= info->var.red.offset;
623                 green >>= (24 - info->var.green.length);
624                 green <<= info->var.green.offset;
626                 blue >>= (24 - info->var.blue.length);
627                 blue <<= info->var.blue.offset;
629                 par->pseudo_palette[regno] = red | green | blue;
631                 if (palette[0] != 0x4000) {
632                         update_hw = 1;
633                         palette[0] = 0x4000;
634                 }
635         }
637         /* Update the palette in the h/w as needed. */
638         if (update_hw)
639                 lcd_blit(LOAD_PALETTE, par);
641         return 0;
644 static void lcd_reset(struct da8xx_fb_par *par)
646         /* Disable the Raster if previously Enabled */
647         lcd_disable_raster();
649         /* DMA has to be disabled */
650         lcdc_write(0, LCD_DMA_CTRL_REG);
651         lcdc_write(0, LCD_RASTER_CTRL_REG);
653         if (lcd_revision == LCD_VERSION_2) {
654                 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
655                 /* Write 1 to reset */
656                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
657                 lcdc_write(0, LCD_CLK_RESET_REG);
658         }
661 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
663         unsigned int lcd_clk, div;
665         lcd_clk = clk_get_rate(par->lcdc_clk);
666         div = lcd_clk / par->pxl_clk;
668         /* Configure the LCD clock divisor. */
669         lcdc_write(LCD_CLK_DIVISOR(div) |
670                         (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
672         if (lcd_revision == LCD_VERSION_2)
673                 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
674                                 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
678 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
679                 struct da8xx_panel *panel)
681         u32 bpp;
682         int ret = 0;
684         lcd_reset(par);
686         /* Calculate the divider */
687         lcd_calc_clk_divider(par);
689         if (panel->invert_pxl_clk)
690                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
691                         LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
692         else
693                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
694                         ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
696         /* Configure the DMA burst size and fifo threshold. */
697         ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
698         if (ret < 0)
699                 return ret;
701         /* Configure the AC bias properties. */
702         lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
704         /* Configure the vertical and horizontal sync properties. */
705         lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
706         lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
708         /* Configure for disply */
709         ret = lcd_cfg_display(cfg);
710         if (ret < 0)
711                 return ret;
714         if ((QVGA != cfg->p_disp_panel->panel_type) &&
715                         (WVGA != cfg->p_disp_panel->panel_type))
716                 return -EINVAL;
718         if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
719             cfg->bpp >= cfg->p_disp_panel->min_bpp)
720                 bpp = cfg->bpp;
721         else
722                 bpp = cfg->p_disp_panel->max_bpp;
723         if (bpp == 12)
724                 bpp = 16;
725         ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
726                                 (unsigned int)panel->height, bpp,
727                                 cfg->raster_order);
728         if (ret < 0)
729                 return ret;
731         /* Configure FDD */
732         lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
733                        (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
735         return 0;
738 int register_vsync_cb(vsync_callback_t handler, void *arg, int idx)
740         if ((vsync_cb_handler == NULL) && (vsync_cb_arg == NULL)) {
741                 vsync_cb_handler = handler;
742                 vsync_cb_arg = arg;
743         } else {
744                 return -EEXIST;
745         }
747         return 0;
749 EXPORT_SYMBOL(register_vsync_cb);
751 int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx)
753         if ((vsync_cb_handler == handler) && (vsync_cb_arg == arg)) {
754                 vsync_cb_handler = NULL;
755                 vsync_cb_arg = NULL;
756         } else {
757                 return -ENXIO;
758         }
760         return 0;
762 EXPORT_SYMBOL(unregister_vsync_cb);
764 /* IRQ handler for version 2 of LCDC */
765 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
767         struct da8xx_fb_par *par = arg;
768         u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
769         u32 reg_int;
771         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
772                 printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
773                 lcd_disable_raster();
774                 clk_disable(par->lcdc_clk);
775                 lcdc_write(stat, LCD_MASKED_STAT_REG);
776                 lcd_enable_raster();
777                 clk_enable(par->lcdc_clk);
778         } else if (stat & LCD_PL_LOAD_DONE) {
779                 /*
780                  * Must disable raster before changing state of any control bit.
781                  * And also must be disabled before clearing the PL loading
782                  * interrupt via the following write to the status register. If
783                  * this is done after then one gets multiple PL done interrupts.
784                  */
785                 lcd_disable_raster();
787                 lcdc_write(stat, LCD_MASKED_STAT_REG);
789                 /* Disable PL completion inerrupt */
790                 reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |
791                        (LCD_V2_PL_INT_ENA);
792                 lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);
794                 /* Setup and start data loading mode */
795                 lcd_blit(LOAD_DATA, par);
796         } else {
797                 lcdc_write(stat, LCD_MASKED_STAT_REG);
799                 if (stat & LCD_END_OF_FRAME0) {
800                         par->which_dma_channel_done = 0;
801                         lcdc_write(par->dma_start,
802                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
803                         lcdc_write(par->dma_end,
804                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
805                         par->vsync_flag = 1;
806                         wake_up_interruptible(&par->vsync_wait);
807                         if (vsync_cb_handler)
808                                 vsync_cb_handler(vsync_cb_arg);
809                 }
811                 if (stat & LCD_END_OF_FRAME1) {
812                         par->which_dma_channel_done = 1;
813                         lcdc_write(par->dma_start,
814                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
815                         lcdc_write(par->dma_end,
816                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
817                         par->vsync_flag = 1;
818                         wake_up_interruptible(&par->vsync_wait);
819                         if (vsync_cb_handler)
820                                 vsync_cb_handler(vsync_cb_arg);
821                 }
822         }
824         lcdc_write(0, LCD_END_OF_INT_IND_REG);
825         return IRQ_HANDLED;
828 /* IRQ handler for version 1 LCDC */
829 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
831         struct da8xx_fb_par *par = arg;
832         u32 stat = lcdc_read(LCD_STAT_REG);
833         u32 reg_ras;
835         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
836                 printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
837                 lcd_disable_raster();
838                 clk_disable(par->lcdc_clk);
839                 lcdc_write(stat, LCD_STAT_REG);
840                 lcd_enable_raster();
841                 clk_enable(par->lcdc_clk);
842         } else if (stat & LCD_PL_LOAD_DONE) {
843                 /*
844                  * Must disable raster before changing state of any control bit.
845                  * And also must be disabled before clearing the PL loading
846                  * interrupt via the following write to the status register. If
847                  * this is done after then one gets multiple PL done interrupts.
848                  */
849                 lcd_disable_raster();
851                 lcdc_write(stat, LCD_STAT_REG);
853                 /* Disable PL completion inerrupt */
854                 reg_ras  = lcdc_read(LCD_RASTER_CTRL_REG);
855                 reg_ras &= ~LCD_V1_PL_INT_ENA;
856                 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
858                 /* Setup and start data loading mode */
859                 lcd_blit(LOAD_DATA, par);
860         } else {
861                 lcdc_write(stat, LCD_STAT_REG);
863                 if (stat & LCD_END_OF_FRAME0) {
864                         lcdc_write(par->dma_start,
865                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
866                         lcdc_write(par->dma_end,
867                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
868                         par->vsync_flag = 1;
869                         wake_up_interruptible(&par->vsync_wait);
870                 }
872                 if (stat & LCD_END_OF_FRAME1) {
873                         lcdc_write(par->dma_start,
874                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
875                         lcdc_write(par->dma_end,
876                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
877                         par->vsync_flag = 1;
878                         wake_up_interruptible(&par->vsync_wait);
879                 }
880         }
882         return IRQ_HANDLED;
885 static int fb_check_var(struct fb_var_screeninfo *var,
886                         struct fb_info *info)
888         int err = 0;
890         switch (var->bits_per_pixel) {
891         case 1:
892         case 8:
893                 var->red.offset = 0;
894                 var->red.length = 8;
895                 var->green.offset = 0;
896                 var->green.length = 8;
897                 var->blue.offset = 0;
898                 var->blue.length = 8;
899                 var->transp.offset = 0;
900                 var->transp.length = 0;
901                 break;
902         case 4:
903                 var->red.offset = 0;
904                 var->red.length = 4;
905                 var->green.offset = 0;
906                 var->green.length = 4;
907                 var->blue.offset = 0;
908                 var->blue.length = 4;
909                 var->transp.offset = 0;
910                 var->transp.length = 0;
911                 break;
912         case 16:                /* RGB 565 */
913                 var->red.offset = 11;
914                 var->red.length = 5;
915                 var->green.offset = 5;
916                 var->green.length = 6;
917                 var->blue.offset = 0;
918                 var->blue.length = 5;
919                 var->transp.offset = 0;
920                 var->transp.length = 0;
921                 break;
922         case 24:
923                 var->red.offset = 16;
924                 var->red.length = 8;
925                 var->green.offset = 8;
926                 var->green.length = 8;
927                 var->blue.offset = 0;
928                 var->blue.length = 8;
929                 break;
930         case 32:
931                 var->transp.offset = 24;
932                 var->transp.length = 8;
933                 var->red.offset = 16;
934                 var->red.length = 8;
935                 var->green.offset = 8;
936                 var->green.length = 8;
937                 var->blue.offset = 0;
938                 var->blue.length = 8;
939                 break;
940         default:
941                 err = -EINVAL;
942         }
944         var->red.msb_right = 0;
945         var->green.msb_right = 0;
946         var->blue.msb_right = 0;
947         var->transp.msb_right = 0;
948         return err;
951 #ifdef CONFIG_CPU_FREQ
952 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
953                                      unsigned long val, void *data)
955         struct da8xx_fb_par *par;
957         par = container_of(nb, struct da8xx_fb_par, freq_transition);
958         if (val == CPUFREQ_PRECHANGE) {
959                 lcd_disable_raster();
960         } else if (val == CPUFREQ_POSTCHANGE) {
961                 lcd_calc_clk_divider(par);
962                 lcd_enable_raster();
963         }
965         return 0;
968 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
970         par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
972         return cpufreq_register_notifier(&par->freq_transition,
973                                          CPUFREQ_TRANSITION_NOTIFIER);
976 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
978         cpufreq_unregister_notifier(&par->freq_transition,
979                                     CPUFREQ_TRANSITION_NOTIFIER);
981 #endif
983 static int __devexit fb_remove(struct platform_device *dev)
985         struct fb_info *info = dev_get_drvdata(&dev->dev);
987         if (info) {
988                 struct da8xx_fb_par *par = info->par;
990 #ifdef CONFIG_CPU_FREQ
991                 lcd_da8xx_cpufreq_deregister(par);
992 #endif
993                 if (par->panel_power_ctrl)
994                         par->panel_power_ctrl(0);
996                 lcd_disable_raster();
997                 lcdc_write(0, LCD_RASTER_CTRL_REG);
999                 /* disable DMA  */
1000                 lcdc_write(0, LCD_DMA_CTRL_REG);
1002                 unregister_framebuffer(info);
1003                 fb_dealloc_cmap(&info->cmap);
1004                 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1005                                   par->p_palette_base);
1006                 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
1007                                   par->vram_phys);
1008                 free_irq(par->irq, par);
1009                 clk_disable(par->lcdc_clk);
1010                 clk_put(par->lcdc_clk);
1011                 framebuffer_release(info);
1012                 iounmap((void __iomem *)da8xx_fb_reg_base);
1013                 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
1015         }
1016         return 0;
1019 /*
1020  * Function to wait for vertical sync which for this LCD peripheral
1021  * translates into waiting for the current raster frame to complete.
1022  */
1023 static int fb_wait_for_vsync(struct fb_info *info)
1025         struct da8xx_fb_par *par = info->par;
1026         int ret;
1028         /*
1029          * Set flag to 0 and wait for isr to set to 1. It would seem there is a
1030          * race condition here where the ISR could have occurred just before or
1031          * just after this set. But since we are just coarsely waiting for
1032          * a frame to complete then that's OK. i.e. if the frame completed
1033          * just before this code executed then we have to wait another full
1034          * frame time but there is no way to avoid such a situation. On the
1035          * other hand if the frame completed just after then we don't need
1036          * to wait long at all. Either way we are guaranteed to return to the
1037          * user immediately after a frame completion which is all that is
1038          * required.
1039          */
1040         par->vsync_flag = 0;
1041         ret = wait_event_interruptible_timeout(par->vsync_wait,
1042                                                par->vsync_flag != 0,
1043                                                par->vsync_timeout);
1044         if (ret < 0)
1045                 return ret;
1046         if (ret == 0)
1047                 return -ETIMEDOUT;
1049         if (par->panel_power_ctrl) {
1050                 /* Switch off panel power and backlight */
1051                 par->panel_power_ctrl(0);
1053                 /* Switch on panel power and backlight */
1054                 par->panel_power_ctrl(1);
1055         }
1057         return 0;
1060 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
1061                           unsigned long arg)
1063         struct lcd_sync_arg sync_arg;
1065         switch (cmd) {
1066         case FBIOGET_CONTRAST:
1067         case FBIOPUT_CONTRAST:
1068         case FBIGET_BRIGHTNESS:
1069         case FBIPUT_BRIGHTNESS:
1070         case FBIGET_COLOR:
1071         case FBIPUT_COLOR:
1072                 return -ENOTTY;
1073         case FBIPUT_HSYNC:
1074                 if (copy_from_user(&sync_arg, (char *)arg,
1075                                 sizeof(struct lcd_sync_arg)))
1076                         return -EFAULT;
1077                 lcd_cfg_horizontal_sync(sync_arg.back_porch,
1078                                         sync_arg.pulse_width,
1079                                         sync_arg.front_porch);
1080                 break;
1081         case FBIPUT_VSYNC:
1082                 if (copy_from_user(&sync_arg, (char *)arg,
1083                                 sizeof(struct lcd_sync_arg)))
1084                         return -EFAULT;
1085                 lcd_cfg_vertical_sync(sync_arg.back_porch,
1086                                         sync_arg.pulse_width,
1087                                         sync_arg.front_porch);
1088                 break;
1089         case FBIO_WAITFORVSYNC:
1090                 return fb_wait_for_vsync(info);
1091         default:
1092                 return -EINVAL;
1093         }
1094         return 0;
1097 static int cfb_blank(int blank, struct fb_info *info)
1099         struct da8xx_fb_par *par = info->par;
1100         int ret = 0;
1102         if (par->blank == blank)
1103                 return 0;
1105         par->blank = blank;
1106         switch (blank) {
1107         case FB_BLANK_UNBLANK:
1108                 if (par->panel_power_ctrl)
1109                         par->panel_power_ctrl(1);
1111                 lcd_enable_raster();
1112                 break;
1113         case FB_BLANK_POWERDOWN:
1114                 if (par->panel_power_ctrl)
1115                         par->panel_power_ctrl(0);
1117                 lcd_disable_raster();
1118                 break;
1119         default:
1120                 ret = -EINVAL;
1121         }
1123         return ret;
1126 /*
1127  * Set new x,y offsets in the virtual display for the visible area and switch
1128  * to the new mode.
1129  */
1130 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1131                              struct fb_info *fbi)
1133         int ret = 0;
1134         struct fb_var_screeninfo new_var;
1135         struct da8xx_fb_par         *par = fbi->par;
1136         struct fb_fix_screeninfo    *fix = &fbi->fix;
1137         unsigned int end;
1138         unsigned int start;
1139         unsigned long irq_flags;
1141         if (var->xoffset != fbi->var.xoffset ||
1142                         var->yoffset != fbi->var.yoffset) {
1143                 memcpy(&new_var, &fbi->var, sizeof(new_var));
1144                 new_var.xoffset = var->xoffset;
1145                 new_var.yoffset = var->yoffset;
1146                 if (fb_check_var(&new_var, fbi))
1147                         ret = -EINVAL;
1148                 else {
1149                         memcpy(&fbi->var, &new_var, sizeof(new_var));
1151                         start   = fix->smem_start +
1152                                 new_var.yoffset * fix->line_length +
1153                                 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1154                         end     = start + fbi->var.yres * fix->line_length - 1;
1155                         par->dma_start  = start;
1156                         par->dma_end    = end;
1157                         spin_lock_irqsave(&par->lock_for_chan_update,
1158                                         irq_flags);
1159                         if (par->which_dma_channel_done == 0) {
1160                                 lcdc_write(par->dma_start,
1161                                            LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1162                                 lcdc_write(par->dma_end,
1163                                            LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1164                         } else if (par->which_dma_channel_done == 1) {
1165                                 lcdc_write(par->dma_start,
1166                                            LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1167                                 lcdc_write(par->dma_end,
1168                                            LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1169                         }
1170                         spin_unlock_irqrestore(&par->lock_for_chan_update,
1171                                         irq_flags);
1172                 }
1173         }
1175         return ret;
1178 static int alloc_fbmem(struct da8xx_fb_par *par)
1180         unsigned int order, size;
1181         unsigned long addr;
1183         size = PAGE_ALIGN(par->vram_size);
1184         order = get_order(size);
1185         par->vram_virt = (void*) __get_free_pages(GFP_KERNEL, order);
1186         addr = (unsigned long) par->vram_virt;
1187         if (addr) {
1188                 while (size > 0) {
1189                         SetPageReserved(virt_to_page(addr));
1190                         addr += PAGE_SIZE;
1191                         size -= PAGE_SIZE;
1192                 }
1193                 par->vram_phys = (u32) virt_to_phys((void *) par->vram_virt);
1194                 return 0;
1195         }
1196         return -ENOMEM;
1199 static struct fb_ops da8xx_fb_ops = {
1200         .owner = THIS_MODULE,
1201         .fb_check_var = fb_check_var,
1202         .fb_setcolreg = fb_setcolreg,
1203         .fb_pan_display = da8xx_pan_display,
1204         .fb_ioctl = fb_ioctl,
1205         .fb_fillrect = cfb_fillrect,
1206         .fb_copyarea = cfb_copyarea,
1207         .fb_imageblit = cfb_imageblit,
1208         .fb_blank = cfb_blank,
1209 };
1211 static int __devinit fb_probe(struct platform_device *device)
1213         struct da8xx_lcdc_platform_data *fb_pdata =
1214                                                 device->dev.platform_data;
1215         struct lcd_ctrl_config *lcd_cfg;
1216         struct da8xx_panel *lcdc_info;
1217         struct fb_info *da8xx_fb_info;
1218         struct clk *fb_clk = NULL;
1219         struct clk *lcdc_ick = NULL;
1220         struct da8xx_fb_par *par;
1221         resource_size_t len;
1222         int ret, i;
1224         if (fb_pdata == NULL) {
1225                 dev_err(&device->dev, "Can not get platform data\n");
1226                 return -ENOENT;
1227         }
1229         lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1230         if (!lcdc_regs) {
1231                 dev_err(&device->dev,
1232                         "Can not get memory resource for LCD controller\n");
1233                 return -ENOENT;
1234         }
1236         len = resource_size(lcdc_regs);
1238         lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
1239         if (!lcdc_regs)
1240                 return -EBUSY;
1242         da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
1243         if (!da8xx_fb_reg_base) {
1244                 ret = -EBUSY;
1245                 goto err_request_mem;
1246         }
1248         /*
1249          * Some SoC will not have seperate interface clock,
1250          * so make lazy check here
1251          */
1252         lcdc_ick = clk_get(&device->dev, "lcdc_ick");
1253         if (IS_ERR(lcdc_ick))
1254                 dev_err(&device->dev, "Can not get lcdc_ick\n");
1256         ret = clk_enable(lcdc_ick);
1257         if (ret)
1258                 dev_err(&device->dev, "failed to enable lcdc_ick\n");
1260         fb_clk = clk_get(&device->dev, NULL);
1261         if (IS_ERR(fb_clk)) {
1262                 dev_err(&device->dev, "Can not get device clock\n");
1263                 ret = -ENODEV;
1264                 goto err_ioremap;
1265         }
1266         ret = clk_enable(fb_clk);
1267         if (ret)
1268                 goto err_clk_put;
1270         /* Determine LCD IP Version */
1271         switch (lcdc_read(LCD_PID_REG)) {
1272         case 0x4C100102:
1273                 lcd_revision = LCD_VERSION_1;
1274                 break;
1275         case 0x4F200800:
1276         case 0x4F201000:
1277                 lcd_revision = LCD_VERSION_2;
1278                 break;
1279         default:
1280                 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1281                                 "defaulting to LCD revision 1\n",
1282                                 lcdc_read(LCD_PID_REG));
1283                 lcd_revision = LCD_VERSION_1;
1284                 break;
1285         }
1287         for (i = 0, lcdc_info = known_lcd_panels;
1288                 i < ARRAY_SIZE(known_lcd_panels);
1289                 i++, lcdc_info++) {
1290                 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1291                         break;
1292         }
1294         if (i == ARRAY_SIZE(known_lcd_panels)) {
1295                 dev_err(&device->dev, "GLCD: No valid panel found\n");
1296                 ret = -ENODEV;
1297                 goto err_clk_disable;
1298         } else
1299                 dev_info(&device->dev, "GLCD: Found %s panel\n",
1300                                         fb_pdata->type);
1302         lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1304         da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1305                                         &device->dev);
1306         if (!da8xx_fb_info) {
1307                 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1308                 ret = -ENOMEM;
1309                 goto err_clk_disable;
1310         }
1312         par = da8xx_fb_info->par;
1313         par->lcdc_clk = fb_clk;
1314         par->pxl_clk = lcdc_info->pxl_clk;
1315         if (fb_pdata->panel_power_ctrl) {
1316                 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1317                 par->panel_power_ctrl(1);
1318         }
1320         if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
1321                 dev_err(&device->dev, "lcd_init failed\n");
1322                 ret = -EFAULT;
1323                 goto err_release_fb;
1324         }
1326         /* allocate frame buffer */
1327         par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
1328         par->vram_size = PAGE_ALIGN(par->vram_size/8);
1329         par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1331         ret = alloc_fbmem(par);
1332         if (ret) {
1333                 dev_err(&device->dev,
1334                         "GLCD: kmalloc for frame buffer failed\n");
1335                 ret = -EINVAL;
1336                 goto err_release_fb;
1337         }
1339         da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1340         da8xx_fb_fix.smem_start    = par->vram_phys;
1341         da8xx_fb_fix.smem_len      = par->vram_size;
1342         da8xx_fb_fix.line_length   = (lcdc_info->width * lcd_cfg->bpp) / 8;
1344         par->dma_start = par->vram_phys;
1345         par->dma_end   = par->dma_start + lcdc_info->height *
1346                 da8xx_fb_fix.line_length - 1;
1348         /* allocate palette buffer */
1349         par->v_palette_base = dma_alloc_coherent(NULL,
1350                                                PALETTE_SIZE,
1351                                                (resource_size_t *)
1352                                                &par->p_palette_base,
1353                                                GFP_KERNEL | GFP_DMA);
1354         if (!par->v_palette_base) {
1355                 dev_err(&device->dev,
1356                         "GLCD: kmalloc for palette buffer failed\n");
1357                 ret = -EINVAL;
1358                 goto err_release_fb_mem;
1359         }
1360         memset(par->v_palette_base, 0, PALETTE_SIZE);
1362         par->irq = platform_get_irq(device, 0);
1363         if (par->irq < 0) {
1364                 ret = -ENOENT;
1365                 goto err_release_pl_mem;
1366         }
1368         /* Initialize par */
1369         da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
1371         da8xx_fb_var.xres = lcdc_info->width;
1372         da8xx_fb_var.xres_virtual = lcdc_info->width;
1374         da8xx_fb_var.yres         = lcdc_info->height;
1375         da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
1377         da8xx_fb_var.grayscale =
1378             lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
1379         da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1381         da8xx_fb_var.hsync_len = lcdc_info->hsw;
1382         da8xx_fb_var.vsync_len = lcdc_info->vsw;
1384         da8xx_fb_var.right_margin = lcdc_info->hfp;
1385         da8xx_fb_var.left_margin  = lcdc_info->hbp;
1386         da8xx_fb_var.lower_margin = lcdc_info->vfp;
1387         da8xx_fb_var.upper_margin = lcdc_info->vbp;
1389         /* Initialize fbinfo */
1390         da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1391         da8xx_fb_info->fix = da8xx_fb_fix;
1392         da8xx_fb_info->var = da8xx_fb_var;
1393         da8xx_fb_info->fbops = &da8xx_fb_ops;
1394         da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1395         da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1396                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1398         ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1399         if (ret)
1400                 goto err_release_pl_mem;
1401         da8xx_fb_info->cmap.len = par->palette_sz;
1403         /* initialize var_screeninfo */
1404         da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1405         fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1407         dev_set_drvdata(&device->dev, da8xx_fb_info);
1409         /* initialize the vsync wait queue */
1410         init_waitqueue_head(&par->vsync_wait);
1411         par->vsync_timeout = HZ / 5;
1412         par->which_dma_channel_done = -1;
1413         spin_lock_init(&par->lock_for_chan_update);
1415         /* Register the Frame Buffer  */
1416         if (register_framebuffer(da8xx_fb_info) < 0) {
1417                 dev_err(&device->dev,
1418                         "GLCD: Frame Buffer Registration Failed!\n");
1419                 ret = -EINVAL;
1420                 goto err_dealloc_cmap;
1421         }
1423 #ifdef CONFIG_CPU_FREQ
1424         ret = lcd_da8xx_cpufreq_register(par);
1425         if (ret) {
1426                 dev_err(&device->dev, "failed to register cpufreq\n");
1427                 goto err_cpu_freq;
1428         }
1429 #endif
1431         if (lcd_revision == LCD_VERSION_1)
1432                 lcdc_irq_handler = lcdc_irq_handler_rev01;
1433         else
1434                 lcdc_irq_handler = lcdc_irq_handler_rev02;
1436         ret = request_irq(par->irq, lcdc_irq_handler, 0,
1437                         DRIVER_NAME, par);
1438         if (ret)
1439                 goto irq_freq;
1440         return 0;
1442 irq_freq:
1443 #ifdef CONFIG_CPU_FREQ
1444         lcd_da8xx_cpufreq_deregister(par);
1445 err_cpu_freq:
1446 #endif
1447         unregister_framebuffer(da8xx_fb_info);
1449 err_dealloc_cmap:
1450         fb_dealloc_cmap(&da8xx_fb_info->cmap);
1452 err_release_pl_mem:
1453         dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1454                           par->p_palette_base);
1456 err_release_fb_mem:
1457         dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1459 err_release_fb:
1460         framebuffer_release(da8xx_fb_info);
1462 err_clk_disable:
1463         clk_disable(fb_clk);
1465 err_clk_put:
1466         clk_put(fb_clk);
1468 err_ioremap:
1469         iounmap((void __iomem *)da8xx_fb_reg_base);
1471 err_request_mem:
1472         release_mem_region(lcdc_regs->start, len);
1474         return ret;
1477 #ifdef CONFIG_PM
1478 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1480         struct fb_info *info = platform_get_drvdata(dev);
1481         struct da8xx_fb_par *par = info->par;
1482         unsigned long timeo = jiffies + msecs_to_jiffies(5000);
1483         u32 stat;
1485         console_lock();
1486         if (par->panel_power_ctrl)
1487                 par->panel_power_ctrl(0);
1489         fb_set_suspend(info, 1);
1490         lcd_disable_raster();
1492         /* Wait for the current frame to complete */
1493         do {
1494                 if (lcd_revision == LCD_VERSION_1)
1495                         stat = lcdc_read(LCD_STAT_REG);
1496                 else
1497                         stat = lcdc_read(LCD_MASKED_STAT_REG);
1498                 cpu_relax();
1499         } while (!(stat & BIT(0)) && time_before(jiffies, timeo));
1501         if (lcd_revision == LCD_VERSION_1)
1502                 lcdc_write(stat, LCD_STAT_REG);
1503         else
1504                 lcdc_write(stat, LCD_MASKED_STAT_REG);
1506         if (time_after_eq(jiffies, timeo)) {
1507                 dev_err(&dev->dev, "controller timed out\n");
1508                 return -ETIMEDOUT;
1509         }
1511         clk_disable(par->lcdc_clk);
1512         console_unlock();
1514         return 0;
1516 static int fb_resume(struct platform_device *dev)
1518         struct fb_info *info = platform_get_drvdata(dev);
1519         struct da8xx_fb_par *par = info->par;
1521         console_lock();
1522         if (par->panel_power_ctrl)
1523                 par->panel_power_ctrl(1);
1525         clk_enable(par->lcdc_clk);
1527         lcd_enable_raster();
1529         if (par->panel_power_ctrl)
1530                 par->panel_power_ctrl(1);
1532         fb_set_suspend(info, 0);
1533         console_unlock();
1535         return 0;
1537 #else
1538 #define fb_suspend NULL
1539 #define fb_resume NULL
1540 #endif
1542 static struct platform_driver da8xx_fb_driver = {
1543         .probe = fb_probe,
1544         .remove = __devexit_p(fb_remove),
1545         .suspend = fb_suspend,
1546         .resume = fb_resume,
1547         .driver = {
1548                    .name = DRIVER_NAME,
1549                    .owner = THIS_MODULE,
1550                    },
1551 };
1553 static int __init da8xx_fb_init(void)
1555         return platform_driver_register(&da8xx_fb_driver);
1558 static void __exit da8xx_fb_cleanup(void)
1560         platform_driver_unregister(&da8xx_fb_driver);
1563 module_init(da8xx_fb_init);
1564 module_exit(da8xx_fb_cleanup);
1566 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1567 MODULE_AUTHOR("Texas Instruments");
1568 MODULE_LICENSE("GPL");