video: da8xx-fb: enable sync and underflow error interrupts
[sitara-epos/sitara-epos-kernel.git] / drivers / video / da8xx-fb.c
1 /*
2  * Copyright (C) 2008-2009 MontaVista Software Inc.
3  * Copyright (C) 2008-2009 Texas Instruments Inc
4  *
5  * Based on the LCD driver for TI Avalanche processors written by
6  * Ajay Singh and Shalom Hai.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option)any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21  */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/fb.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/interrupt.h>
30 #include <linux/clk.h>
31 #include <linux/cpufreq.h>
32 #include <linux/console.h>
33 #include <linux/spinlock.h>
34 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/pm_runtime.h>
37 #include <video/da8xx-fb.h>
38 #include <asm/mach-types.h>
40 #define DRIVER_NAME "da8xx_lcdc"
42 #define LCD_VERSION_1   1
43 #define LCD_VERSION_2   2
45 /* LCD Status Register */
46 #define LCD_END_OF_FRAME1               BIT(9)
47 #define LCD_END_OF_FRAME0               BIT(8)
48 #define LCD_PL_LOAD_DONE                BIT(6)
49 #define LCD_FIFO_UNDERFLOW              BIT(5)
50 #define LCD_SYNC_LOST                   BIT(2)
52 /* LCD DMA Control Register */
53 #define LCD_DMA_BURST_SIZE(x)           ((x) << 4)
54 #define LCD_DMA_BURST_1                 0x0
55 #define LCD_DMA_BURST_2                 0x1
56 #define LCD_DMA_BURST_4                 0x2
57 #define LCD_DMA_BURST_8                 0x3
58 #define LCD_DMA_BURST_16                0x4
59 #define LCD_V1_END_OF_FRAME_INT_ENA     BIT(2)
60 #define LCD_V2_END_OF_FRAME0_INT_ENA    BIT(8)
61 #define LCD_V2_END_OF_FRAME1_INT_ENA    BIT(9)
62 #define LCD_DUAL_FRAME_BUFFER_ENABLE    BIT(0)
64 /* LCD Control Register */
65 #define LCD_CLK_DIVISOR(x)              ((x) << 8)
66 #define LCD_RASTER_MODE                 0x01
68 /* LCD Raster Control Register */
69 #define LCD_PALETTE_LOAD_MODE(x)        ((x) << 20)
70 #define PALETTE_AND_DATA                0x00
71 #define PALETTE_ONLY                    0x01
72 #define DATA_ONLY                       0x02
74 #define LCD_MONO_8BIT_MODE              BIT(9)
75 #define LCD_RASTER_ORDER                BIT(8)
76 #define LCD_TFT_MODE                    BIT(7)
77 #define LCD_V1_UNDERFLOW_INT_ENA        BIT(6)
78 #define LCD_V2_UNDERFLOW_INT_ENA        BIT(5)
79 #define LCD_V1_PL_INT_ENA               BIT(4)
80 #define LCD_V2_PL_INT_ENA               BIT(6)
81 #define LCD_MONOCHROME_MODE             BIT(1)
82 #define LCD_RASTER_ENABLE               BIT(0)
83 #define LCD_TFT_ALT_ENABLE              BIT(23)
84 #define LCD_STN_565_ENABLE              BIT(24)
85 #define LCD_V2_DMA_CLK_EN               BIT(2)
86 #define LCD_V2_LIDD_CLK_EN              BIT(1)
87 #define LCD_V2_CORE_CLK_EN              BIT(0)
88 #define LCD_V2_LPP_B10                  26
89 #define LCD_V2_TFT_24BPP_MODE           BIT(25)
90 #define LCD_V2_TFT_24BPP_UNPACK         BIT(26)
92 /* LCD Raster Timing 2 Register */
93 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
94 #define LCD_AC_BIAS_FREQUENCY(x)                ((x) << 8)
95 #define LCD_SYNC_CTRL                           BIT(25)
96 #define LCD_SYNC_EDGE                           BIT(24)
97 #define LCD_INVERT_PIXEL_CLOCK                  BIT(22)
98 #define LCD_INVERT_LINE_CLOCK                   BIT(21)
99 #define LCD_INVERT_FRAME_CLOCK                  BIT(20)
101 /* LCD Block */
102 #define  LCD_PID_REG                            0x0
103 #define  LCD_CTRL_REG                           0x4
104 #define  LCD_STAT_REG                           0x8
105 #define  LCD_RASTER_CTRL_REG                    0x28
106 #define  LCD_RASTER_TIMING_0_REG                0x2C
107 #define  LCD_RASTER_TIMING_1_REG                0x30
108 #define  LCD_RASTER_TIMING_2_REG                0x34
109 #define  LCD_DMA_CTRL_REG                       0x40
110 #define  LCD_DMA_FRM_BUF_BASE_ADDR_0_REG        0x44
111 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG     0x48
112 #define  LCD_DMA_FRM_BUF_BASE_ADDR_1_REG        0x4C
113 #define  LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG     0x50
115 /* Interrupt Registers available only in Version 2 */
116 #define  LCD_RAW_STAT_REG                       0x58
117 #define  LCD_MASKED_STAT_REG                    0x5c
118 #define  LCD_INT_ENABLE_SET_REG                 0x60
119 #define  LCD_INT_ENABLE_CLR_REG                 0x64
120 #define  LCD_END_OF_INT_IND_REG                 0x68
122 /* Clock registers available only on Version 2 */
123 #define  LCD_CLK_ENABLE_REG                     0x6c
124 #define  LCD_CLK_RESET_REG                      0x70
125 #define  LCD_CLK_MAIN_RESET                     BIT(3)
127 #define LCD_NUM_BUFFERS 2
129 #define WSI_TIMEOUT     50
130 #define PALETTE_SIZE    256
131 #define LEFT_MARGIN     64
132 #define RIGHT_MARGIN    64
133 #define UPPER_MARGIN    32
134 #define LOWER_MARGIN    32
135 #define WAIT_FOR_FRAME_DONE     true
136 #define NO_WAIT_FOR_FRAME_DONE  false
138 static resource_size_t da8xx_fb_reg_base;
139 static struct resource *lcdc_regs;
140 static unsigned int lcd_revision;
141 static irq_handler_t lcdc_irq_handler;
143 static inline unsigned int lcdc_read(unsigned int addr)
145         return (unsigned int)readl(da8xx_fb_reg_base + (addr));
148 static inline void lcdc_write(unsigned int val, unsigned int addr)
150         writel(val, da8xx_fb_reg_base + (addr));
153 struct da8xx_fb_par {
154         struct device *dev;
155         resource_size_t p_palette_base;
156         unsigned char *v_palette_base;
157         dma_addr_t              vram_phys;
158         unsigned long           vram_size;
159         void                    *vram_virt;
160         unsigned int            dma_start;
161         unsigned int            dma_end;
162         struct clk *lcdc_clk;
163         int irq;
164         unsigned long pseudo_palette[32];
165         unsigned int palette_sz;
166         unsigned int pxl_clk;
167         int blank;
168         wait_queue_head_t       vsync_wait;
169         int                     vsync_flag;
170         int                     vsync_timeout;
171         spinlock_t              lock_for_chan_update;
173         /*
174          * LCDC has 2 ping pong DMA channels, channel 0
175          * and channel 1.
176          */
177         unsigned int            which_dma_channel_done;
178 #ifdef CONFIG_CPU_FREQ
179         struct notifier_block   freq_transition;
180         unsigned int            lcd_fck_rate;
181 #endif
182         void (*panel_power_ctrl)(int);
183 };
185 /* Variable Screen Information */
186 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
187         .xoffset = 0,
188         .yoffset = 0,
189         .transp = {0, 0, 0},
190         .nonstd = 0,
191         .activate = 0,
192         .height = -1,
193         .width = -1,
194         .pixclock = 33333,/*Pico Sec*/
195         .accel_flags = 0,
196         .left_margin = LEFT_MARGIN,
197         .right_margin = RIGHT_MARGIN,
198         .upper_margin = UPPER_MARGIN,
199         .lower_margin = LOWER_MARGIN,
200         .sync = 0,
201         .vmode = FB_VMODE_NONINTERLACED
202 };
204 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
205         .id = "DA8xx FB Drv",
206         .type = FB_TYPE_PACKED_PIXELS,
207         .type_aux = 0,
208         .visual = FB_VISUAL_PSEUDOCOLOR,
209         .xpanstep = 0,
210         .ypanstep = 1,
211         .ywrapstep = 0,
212         .accel = FB_ACCEL_NONE
213 };
215 struct da8xx_panel {
216         const char      name[25];       /* Full name <vendor>_<model> */
217         unsigned short  width;
218         unsigned short  height;
219         int             hfp;            /* Horizontal front porch */
220         int             hbp;            /* Horizontal back porch */
221         int             hsw;            /* Horizontal Sync Pulse Width */
222         int             vfp;            /* Vertical front porch */
223         int             vbp;            /* Vertical back porch */
224         int             vsw;            /* Vertical Sync Pulse Width */
225         unsigned int    pxl_clk;        /* Pixel clock */
226         unsigned char   invert_pxl_clk; /* Invert Pixel clock */
227 };
229 static vsync_callback_t vsync_cb_handler;
230 static void *vsync_cb_arg;
232 static struct da8xx_panel known_lcd_panels[] = {
233         /* Sharp LCD035Q3DG01 */
234         [0] = {
235                 .name = "Sharp_LCD035Q3DG01",
236                 .width = 320,
237                 .height = 240,
238                 .hfp = 8,
239                 .hbp = 6,
240                 .hsw = 0,
241                 .vfp = 2,
242                 .vbp = 2,
243                 .vsw = 0,
244                 .pxl_clk = 4608000,
245                 .invert_pxl_clk = 1,
246         },
247         /* Sharp LK043T1DG01 */
248         [1] = {
249                 .name = "Sharp_LK043T1DG01",
250                 .width = 480,
251                 .height = 272,
252                 .hfp = 2,
253                 .hbp = 2,
254                 .hsw = 41,
255                 .vfp = 3,
256                 .vbp = 3,
257                 .vsw = 10,
258                 .pxl_clk = 7833600,
259                 .invert_pxl_clk = 0,
260         },
261         /* ThreeFive S9700RTWV35TR */
262         [2] = {
263                 .name = "TFC_S9700RTWV35TR_01B",
264                 .width = 800,
265                 .height = 480,
266                 .hfp = 39,
267                 .hbp = 39,
268                 .hsw = 47,
269                 .vfp = 13,
270                 .vbp = 29,
271                 .vsw = 2,
272                 .pxl_clk = 30000000,
273                 .invert_pxl_clk = 0,
274         },
275 };
277 /* Enable the Raster Engine of the LCD Controller */
278 static inline void lcd_enable_raster(void)
280         u32 reg;
282         /* Bring LCDC out of reset */
283         if (lcd_revision == LCD_VERSION_2)
284                 lcdc_write(0, LCD_CLK_RESET_REG);
286         reg = lcdc_read(LCD_RASTER_CTRL_REG);
287         if (!(reg & LCD_RASTER_ENABLE))
288                 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
291 /* Disable the Raster Engine of the LCD Controller */
292 static inline void lcd_disable_raster(bool wait_for_frame_done)
294         u32 reg;
295         u32 loop_cnt = 0;
296         u32 stat;
297         u32 i = 0;
299         if (wait_for_frame_done)
300                 loop_cnt = 5000;
302         reg = lcdc_read(LCD_RASTER_CTRL_REG);
303         if (reg & LCD_RASTER_ENABLE)
304                 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
306         /* Wait for the current frame to complete */
307         do {
308                 if (lcd_revision == LCD_VERSION_1)
309                         stat = lcdc_read(LCD_STAT_REG);
310                 else
311                         stat = lcdc_read(LCD_RAW_STAT_REG);
313                 mdelay(1);
314         } while (!(stat & BIT(0)) && (i++ < loop_cnt));
316         if (lcd_revision == LCD_VERSION_1)
317                 lcdc_write(stat, LCD_STAT_REG);
318         else
319                 lcdc_write(stat, LCD_MASKED_STAT_REG);
321         if ((loop_cnt != 0) && (i >= loop_cnt)) {
322                 printk(KERN_ERR "LCD Controller timed out\n");
323                 return;
324         }
326         if (lcd_revision == LCD_VERSION_2)
327                 /* Write 1 to reset LCDC */
328                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
331 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
333         u32 start;
334         u32 end;
335         u32 reg_ras;
336         u32 reg_dma;
337         u32 reg_int;
339         /* init reg to clear PLM (loading mode) fields */
340         reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
341         reg_ras &= ~(3 << 20);
343         reg_dma  = lcdc_read(LCD_DMA_CTRL_REG);
345         if (load_mode == LOAD_DATA) {
346                 start    = par->dma_start;
347                 end      = par->dma_end;
349                 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
350                 if (lcd_revision == LCD_VERSION_1) {
351                         reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
352                 } else {
353                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
354                                 LCD_V2_END_OF_FRAME0_INT_ENA |
355                                 LCD_V2_END_OF_FRAME1_INT_ENA |
356                                 LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
357                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
358                 }
359                 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
361                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
362                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
363                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
364                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
365         } else if (load_mode == LOAD_PALETTE) {
366                 start    = par->p_palette_base;
367                 end      = start + par->palette_sz - 1;
369                 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
371                 if (lcd_revision == LCD_VERSION_1) {
372                         reg_ras |= LCD_V1_PL_INT_ENA;
373                 } else {
374                         reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
375                                 LCD_V2_PL_INT_ENA;
376                         lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
377                 }
379                 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
380                 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
381         }
383         lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
384         lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
386         /*
387          * The Raster enable bit must be set after all other control fields are
388          * set.
389          */
390         lcd_enable_raster();
393 /* Configure the Burst Size and fifo threhold of DMA */
394 static int lcd_cfg_dma(int burst_size,  int fifo_th)
396         u32 reg;
398         reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
399         switch (burst_size) {
400         case 1:
401                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
402                 break;
403         case 2:
404                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
405                 break;
406         case 4:
407                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
408                 break;
409         case 8:
410                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
411                 break;
412         case 16:
413                 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
414                 break;
415         default:
416                 return -EINVAL;
417         }
419         reg |= (fifo_th << 8);
421         lcdc_write(reg, LCD_DMA_CTRL_REG);
423         return 0;
426 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
428         u32 reg;
430         /* Set the AC Bias Period and Number of Transisitons per Interrupt */
431         reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
432         reg |= LCD_AC_BIAS_FREQUENCY(period) |
433                 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
434         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
437 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
438                 int front_porch)
440         u32 reg;
442         reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
443         reg |= ((back_porch & 0xff) << 24)
444             | ((front_porch & 0xff) << 16)
445             | ((pulse_width & 0x3f) << 10);
446         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
449 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
450                 int front_porch)
452         u32 reg;
454         reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
455         reg |= ((back_porch & 0xff) << 24)
456             | ((front_porch & 0xff) << 16)
457             | ((pulse_width & 0x3f) << 10);
458         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
461 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
463         u32 reg;
464         u32 reg_int;
466         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
467                                                 LCD_MONO_8BIT_MODE |
468                                                 LCD_MONOCHROME_MODE);
470         switch (cfg->p_disp_panel->panel_shade) {
471         case MONOCHROME:
472                 reg |= LCD_MONOCHROME_MODE;
473                 if (cfg->mono_8bit_mode)
474                         reg |= LCD_MONO_8BIT_MODE;
475                 break;
476         case COLOR_ACTIVE:
477                 reg |= LCD_TFT_MODE;
478                 if (cfg->tft_alt_mode)
479                         reg |= LCD_TFT_ALT_ENABLE;
480                 break;
482         case COLOR_PASSIVE:
483                 if (cfg->stn_565_mode)
484                         reg |= LCD_STN_565_ENABLE;
485                 break;
487         default:
488                 return -EINVAL;
489         }
491         /* enable additional interrupts here */
492         if (lcd_revision == LCD_VERSION_1) {
493                 reg |= LCD_V1_UNDERFLOW_INT_ENA;
494         } else {
495                 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
496                         LCD_V2_UNDERFLOW_INT_ENA;
497                 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
498         }
500         lcdc_write(reg, LCD_RASTER_CTRL_REG);
502         reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
504         if (cfg->sync_ctrl)
505                 reg |= LCD_SYNC_CTRL;
506         else
507                 reg &= ~LCD_SYNC_CTRL;
509         if (cfg->sync_edge)
510                 reg |= LCD_SYNC_EDGE;
511         else
512                 reg &= ~LCD_SYNC_EDGE;
514         if (cfg->invert_line_clock)
515                 reg |= LCD_INVERT_LINE_CLOCK;
516         else
517                 reg &= ~LCD_INVERT_LINE_CLOCK;
519         if (cfg->invert_frm_clock)
520                 reg |= LCD_INVERT_FRAME_CLOCK;
521         else
522                 reg &= ~LCD_INVERT_FRAME_CLOCK;
524         lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
526         return 0;
529 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
530                 u32 bpp, u32 raster_order)
532         u32 reg;
534         /* Set the Panel Width */
535         /* Pixels per line = (PPL + 1)*16 */
536         if (lcd_revision == LCD_VERSION_1) {
537                 /*
538                  * 0x3F in bits 4..9 gives max horizontal resolution = 1024
539                  * pixels.
540                  */
541                 width &= 0x3f0;
542         } else {
543                 /*
544                  * 0x7F in bits 4..10 gives max horizontal resolution = 2048
545                  * pixels.
546                  */
547                 width &= 0x7f0;
548         }
550         reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
551         reg &= 0xfffffc00;
552         if (lcd_revision == LCD_VERSION_1) {
553                 reg |= ((width >> 4) - 1) << 4;
554         } else {
555                 width = (width >> 4) - 1;
556                 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
557         }
558         lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
560         /* Set the Panel Height */
561         /* Set bits 9:0 of Lines Per Pixel */
562         reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
563         reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
564         lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
566         /* Set bit 10 of Lines Per Pixel */
567         if (lcd_revision == LCD_VERSION_2) {
568                 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
569                 reg |= ((height - 1) & 0x400) << 16;
570                 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
571         }
573         /* Set the Raster Order of the Frame Buffer */
574         reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
575         if (raster_order)
576                 reg |= LCD_RASTER_ORDER;
578         if (bpp == 24)
579                 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
580         else if (bpp == 32)
581                 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
582                                 | LCD_V2_TFT_24BPP_UNPACK);
584         lcdc_write(reg, LCD_RASTER_CTRL_REG);
586         switch (bpp) {
587         case 1:
588         case 2:
589         case 4:
590         case 16:
591         case 24:
592         case 32:
593                 par->palette_sz = 16 * 2;
594                 break;
596         case 8:
597                 par->palette_sz = 256 * 2;
598                 break;
600         default:
601                 return -EINVAL;
602         }
604         return 0;
607 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
608                               unsigned blue, unsigned transp,
609                               struct fb_info *info)
611         struct da8xx_fb_par *par = info->par;
612         unsigned short *palette = (unsigned short *) par->v_palette_base;
613         u_short pal;
614         int update_hw = 0;
616         if (regno > 255)
617                 return 1;
619         if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
620                 return 1;
622         if (info->var.bits_per_pixel == 8) {
623                 red >>= 4;
624                 green >>= 8;
625                 blue >>= 12;
627                 pal = (red & 0x0f00);
628                 pal |= (green & 0x00f0);
629                 pal |= (blue & 0x000f);
631                 if (palette[regno] != pal) {
632                         update_hw = 1;
633                         palette[regno] = pal;
634                 }
635         } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
636                 red >>= (16 - info->var.red.length);
637                 red <<= info->var.red.offset;
639                 green >>= (16 - info->var.green.length);
640                 green <<= info->var.green.offset;
642                 blue >>= (16 - info->var.blue.length);
643                 blue <<= info->var.blue.offset;
645                 par->pseudo_palette[regno] = red | green | blue;
647                 if (palette[0] != 0x4000) {
648                         update_hw = 1;
649                         palette[0] = 0x4000;
650                 }
651         } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
652                     ((info->var.bits_per_pixel == 24) && regno < 24)) {
653                 red >>= (24 - info->var.red.length);
654                 red <<= info->var.red.offset;
656                 green >>= (24 - info->var.green.length);
657                 green <<= info->var.green.offset;
659                 blue >>= (24 - info->var.blue.length);
660                 blue <<= info->var.blue.offset;
662                 par->pseudo_palette[regno] = red | green | blue;
664                 if (palette[0] != 0x4000) {
665                         update_hw = 1;
666                         palette[0] = 0x4000;
667                 }
668         }
670         /* Update the palette in the h/w as needed. */
671         if (update_hw)
672                 lcd_blit(LOAD_PALETTE, par);
674         return 0;
677 static void lcd_reset(struct da8xx_fb_par *par)
679         /* Disable the Raster if previously Enabled */
680         lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
682         /* DMA has to be disabled */
683         lcdc_write(0, LCD_DMA_CTRL_REG);
684         lcdc_write(0, LCD_RASTER_CTRL_REG);
686         if (lcd_revision == LCD_VERSION_2) {
687                 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
688                 /* Write 1 to reset */
689                 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
690                 lcdc_write(0, LCD_CLK_RESET_REG);
691         }
694 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
696         unsigned int lcd_clk, div;
698         lcd_clk = clk_get_rate(par->lcdc_clk);
699         div = lcd_clk / par->pxl_clk;
701         /* Configure the LCD clock divisor. */
702         lcdc_write(LCD_CLK_DIVISOR(div) |
703                         (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
705         if (lcd_revision == LCD_VERSION_2)
706                 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
707                                 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
711 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
712                 struct da8xx_panel *panel)
714         u32 bpp;
715         int ret = 0;
717         lcd_reset(par);
719         /* Calculate the divider */
720         lcd_calc_clk_divider(par);
722         if (panel->invert_pxl_clk)
723                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
724                         LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
725         else
726                 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
727                         ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
729         /* Configure the DMA burst size and fifo threshold. */
730         ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
731         if (ret < 0)
732                 return ret;
734         /* Configure the AC bias properties. */
735         lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
737         /* Configure the vertical and horizontal sync properties. */
738         lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
739         lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
741         /* Configure for disply */
742         ret = lcd_cfg_display(cfg);
743         if (ret < 0)
744                 return ret;
747         if ((QVGA != cfg->p_disp_panel->panel_type) &&
748                         (WVGA != cfg->p_disp_panel->panel_type))
749                 return -EINVAL;
751         if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
752             cfg->bpp >= cfg->p_disp_panel->min_bpp)
753                 bpp = cfg->bpp;
754         else
755                 bpp = cfg->p_disp_panel->max_bpp;
756         if (bpp == 12)
757                 bpp = 16;
758         ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
759                                 (unsigned int)panel->height, bpp,
760                                 cfg->raster_order);
761         if (ret < 0)
762                 return ret;
764         /* Configure FDD */
765         lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
766                        (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
768         return 0;
771 int register_vsync_cb(vsync_callback_t handler, void *arg, int idx)
773         if ((vsync_cb_handler == NULL) && (vsync_cb_arg == NULL)) {
774                 vsync_cb_handler = handler;
775                 vsync_cb_arg = arg;
776         } else {
777                 return -EEXIST;
778         }
780         return 0;
782 EXPORT_SYMBOL(register_vsync_cb);
784 int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx)
786         if ((vsync_cb_handler == handler) && (vsync_cb_arg == arg)) {
787                 vsync_cb_handler = NULL;
788                 vsync_cb_arg = NULL;
789         } else {
790                 return -ENXIO;
791         }
793         return 0;
795 EXPORT_SYMBOL(unregister_vsync_cb);
797 /* IRQ handler for version 2 of LCDC */
798 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
800         struct da8xx_fb_par *par = arg;
801         u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
802         struct device *dev = par->dev;
803         u32 reg_int;
805         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
806                 printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
807                 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
808                 pm_runtime_put_sync(dev);
809                 lcdc_write(stat, LCD_MASKED_STAT_REG);
810                 lcd_enable_raster();
811                 pm_runtime_get_sync(dev);
812         } else if (stat & LCD_PL_LOAD_DONE) {
813                 /*
814                  * Must disable raster before changing state of any control bit.
815                  * And also must be disabled before clearing the PL loading
816                  * interrupt via the following write to the status register. If
817                  * this is done after then one gets multiple PL done interrupts.
818                  */
819                 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
821                 lcdc_write(stat, LCD_MASKED_STAT_REG);
823                 /* Disable PL completion inerrupt */
824                 reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |
825                        (LCD_V2_PL_INT_ENA);
826                 lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);
828                 /* Setup and start data loading mode */
829                 lcd_blit(LOAD_DATA, par);
830         } else {
831                 lcdc_write(stat, LCD_MASKED_STAT_REG);
833                 if (stat & LCD_END_OF_FRAME0) {
834                         par->which_dma_channel_done = 0;
835                         lcdc_write(par->dma_start,
836                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
837                         lcdc_write(par->dma_end,
838                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
839                         par->vsync_flag = 1;
840                         wake_up_interruptible(&par->vsync_wait);
841                         if (vsync_cb_handler)
842                                 vsync_cb_handler(vsync_cb_arg);
843                 }
845                 if (stat & LCD_END_OF_FRAME1) {
846                         par->which_dma_channel_done = 1;
847                         lcdc_write(par->dma_start,
848                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
849                         lcdc_write(par->dma_end,
850                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
851                         par->vsync_flag = 1;
852                         wake_up_interruptible(&par->vsync_wait);
853                         if (vsync_cb_handler)
854                                 vsync_cb_handler(vsync_cb_arg);
855                 }
856         }
858         lcdc_write(0, LCD_END_OF_INT_IND_REG);
859         return IRQ_HANDLED;
862 /* IRQ handler for version 1 LCDC */
863 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
865         struct da8xx_fb_par *par = arg;
866         u32 stat = lcdc_read(LCD_STAT_REG);
867         u32 reg_ras;
869         if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
870                 printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
871                 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
872                 clk_disable(par->lcdc_clk);
873                 lcdc_write(stat, LCD_STAT_REG);
874                 lcd_enable_raster();
875                 clk_enable(par->lcdc_clk);
876         } else if (stat & LCD_PL_LOAD_DONE) {
877                 /*
878                  * Must disable raster before changing state of any control bit.
879                  * And also must be disabled before clearing the PL loading
880                  * interrupt via the following write to the status register. If
881                  * this is done after then one gets multiple PL done interrupts.
882                  */
883                 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
885                 lcdc_write(stat, LCD_STAT_REG);
887                 /* Disable PL completion inerrupt */
888                 reg_ras  = lcdc_read(LCD_RASTER_CTRL_REG);
889                 reg_ras &= ~LCD_V1_PL_INT_ENA;
890                 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
892                 /* Setup and start data loading mode */
893                 lcd_blit(LOAD_DATA, par);
894         } else {
895                 lcdc_write(stat, LCD_STAT_REG);
897                 if (stat & LCD_END_OF_FRAME0) {
898                         lcdc_write(par->dma_start,
899                                    LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
900                         lcdc_write(par->dma_end,
901                                    LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
902                         par->vsync_flag = 1;
903                         wake_up_interruptible(&par->vsync_wait);
904                 }
906                 if (stat & LCD_END_OF_FRAME1) {
907                         lcdc_write(par->dma_start,
908                                    LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
909                         lcdc_write(par->dma_end,
910                                    LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
911                         par->vsync_flag = 1;
912                         wake_up_interruptible(&par->vsync_wait);
913                 }
914         }
916         return IRQ_HANDLED;
919 static int fb_check_var(struct fb_var_screeninfo *var,
920                         struct fb_info *info)
922         int err = 0;
924         switch (var->bits_per_pixel) {
925         case 1:
926         case 8:
927                 var->red.offset = 0;
928                 var->red.length = 8;
929                 var->green.offset = 0;
930                 var->green.length = 8;
931                 var->blue.offset = 0;
932                 var->blue.length = 8;
933                 var->transp.offset = 0;
934                 var->transp.length = 0;
935                 break;
936         case 4:
937                 var->red.offset = 0;
938                 var->red.length = 4;
939                 var->green.offset = 0;
940                 var->green.length = 4;
941                 var->blue.offset = 0;
942                 var->blue.length = 4;
943                 var->transp.offset = 0;
944                 var->transp.length = 0;
945                 break;
946         case 16:                /* RGB 565 */
947                 var->red.offset = 11;
948                 var->red.length = 5;
949                 var->green.offset = 5;
950                 var->green.length = 6;
951                 var->blue.offset = 0;
952                 var->blue.length = 5;
953                 var->transp.offset = 0;
954                 var->transp.length = 0;
955                 break;
956         case 24:
957                 var->red.offset = 16;
958                 var->red.length = 8;
959                 var->green.offset = 8;
960                 var->green.length = 8;
961                 var->blue.offset = 0;
962                 var->blue.length = 8;
963                 break;
964         case 32:
965                 var->transp.offset = 24;
966                 var->transp.length = 8;
967                 var->red.offset = 16;
968                 var->red.length = 8;
969                 var->green.offset = 8;
970                 var->green.length = 8;
971                 var->blue.offset = 0;
972                 var->blue.length = 8;
973                 break;
974         default:
975                 err = -EINVAL;
976         }
978         var->red.msb_right = 0;
979         var->green.msb_right = 0;
980         var->blue.msb_right = 0;
981         var->transp.msb_right = 0;
982         return err;
985 #ifdef CONFIG_CPU_FREQ
986 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
987                                      unsigned long val, void *data)
989         struct da8xx_fb_par *par;
991         par = container_of(nb, struct da8xx_fb_par, freq_transition);
992         if (val == CPUFREQ_POSTCHANGE) {
993                 if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) {
994                         lcd_disable_raster(WAIT_FOR_FRAME_DONE);
995                         lcd_calc_clk_divider(par);
996                         lcd_enable_raster();
997                 }
998         }
1000         return 0;
1003 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
1005         par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
1007         return cpufreq_register_notifier(&par->freq_transition,
1008                                          CPUFREQ_TRANSITION_NOTIFIER);
1011 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
1013         cpufreq_unregister_notifier(&par->freq_transition,
1014                                     CPUFREQ_TRANSITION_NOTIFIER);
1016 #endif
1018 static int __devexit fb_remove(struct platform_device *dev)
1020         struct fb_info *info = dev_get_drvdata(&dev->dev);
1022         if (info) {
1023                 struct da8xx_fb_par *par = info->par;
1025 #ifdef CONFIG_CPU_FREQ
1026                 lcd_da8xx_cpufreq_deregister(par);
1027 #endif
1028                 if (par->panel_power_ctrl)
1029                         par->panel_power_ctrl(0);
1031                 lcd_disable_raster(WAIT_FOR_FRAME_DONE);
1032                 lcdc_write(0, LCD_RASTER_CTRL_REG);
1034                 /* disable DMA  */
1035                 lcdc_write(0, LCD_DMA_CTRL_REG);
1037                 unregister_framebuffer(info);
1038                 fb_dealloc_cmap(&info->cmap);
1039                 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1040                                   par->p_palette_base);
1041                 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
1042                                   par->vram_phys);
1043                 free_irq(par->irq, par);
1044                 pm_runtime_put_sync(&dev->dev);
1045                 pm_runtime_disable(&dev->dev);
1046                 framebuffer_release(info);
1047                 iounmap((void __iomem *)da8xx_fb_reg_base);
1048                 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
1050         }
1051         return 0;
1054 /*
1055  * Function to wait for vertical sync which for this LCD peripheral
1056  * translates into waiting for the current raster frame to complete.
1057  */
1058 static int fb_wait_for_vsync(struct fb_info *info)
1060         struct da8xx_fb_par *par = info->par;
1061         int ret;
1063         /*
1064          * Set flag to 0 and wait for isr to set to 1. It would seem there is a
1065          * race condition here where the ISR could have occurred just before or
1066          * just after this set. But since we are just coarsely waiting for
1067          * a frame to complete then that's OK. i.e. if the frame completed
1068          * just before this code executed then we have to wait another full
1069          * frame time but there is no way to avoid such a situation. On the
1070          * other hand if the frame completed just after then we don't need
1071          * to wait long at all. Either way we are guaranteed to return to the
1072          * user immediately after a frame completion which is all that is
1073          * required.
1074          */
1075         par->vsync_flag = 0;
1076         ret = wait_event_interruptible_timeout(par->vsync_wait,
1077                                                par->vsync_flag != 0,
1078                                                par->vsync_timeout);
1079         if (ret < 0)
1080                 return ret;
1081         if (ret == 0)
1082                 return -ETIMEDOUT;
1084         if (par->panel_power_ctrl) {
1085                 /* Switch off panel power and backlight */
1086                 par->panel_power_ctrl(0);
1088                 /* Switch on panel power and backlight */
1089                 par->panel_power_ctrl(1);
1090         }
1092         return 0;
1095 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
1096                           unsigned long arg)
1098         struct lcd_sync_arg sync_arg;
1100         switch (cmd) {
1101         case FBIOGET_CONTRAST:
1102         case FBIOPUT_CONTRAST:
1103         case FBIGET_BRIGHTNESS:
1104         case FBIPUT_BRIGHTNESS:
1105         case FBIGET_COLOR:
1106         case FBIPUT_COLOR:
1107                 return -ENOTTY;
1108         case FBIPUT_HSYNC:
1109                 if (copy_from_user(&sync_arg, (char *)arg,
1110                                 sizeof(struct lcd_sync_arg)))
1111                         return -EFAULT;
1112                 lcd_cfg_horizontal_sync(sync_arg.back_porch,
1113                                         sync_arg.pulse_width,
1114                                         sync_arg.front_porch);
1115                 break;
1116         case FBIPUT_VSYNC:
1117                 if (copy_from_user(&sync_arg, (char *)arg,
1118                                 sizeof(struct lcd_sync_arg)))
1119                         return -EFAULT;
1120                 lcd_cfg_vertical_sync(sync_arg.back_porch,
1121                                         sync_arg.pulse_width,
1122                                         sync_arg.front_porch);
1123                 break;
1124         case FBIO_WAITFORVSYNC:
1125                 return fb_wait_for_vsync(info);
1126         default:
1127                 return -EINVAL;
1128         }
1129         return 0;
1132 static int cfb_blank(int blank, struct fb_info *info)
1134         struct da8xx_fb_par *par = info->par;
1135         int ret = 0;
1137         if (par->blank == blank)
1138                 return 0;
1140         par->blank = blank;
1141         switch (blank) {
1142         case FB_BLANK_UNBLANK:
1143                 if (par->panel_power_ctrl)
1144                         par->panel_power_ctrl(1);
1146                 lcd_enable_raster();
1147                 break;
1148         case FB_BLANK_POWERDOWN:
1149                 if (par->panel_power_ctrl)
1150                         par->panel_power_ctrl(0);
1152                 lcd_disable_raster(WAIT_FOR_FRAME_DONE);
1153                 break;
1154         default:
1155                 ret = -EINVAL;
1156         }
1158         return ret;
1161 /*
1162  * Set new x,y offsets in the virtual display for the visible area and switch
1163  * to the new mode.
1164  */
1165 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1166                              struct fb_info *fbi)
1168         int ret = 0;
1169         struct fb_var_screeninfo new_var;
1170         struct da8xx_fb_par         *par = fbi->par;
1171         struct fb_fix_screeninfo    *fix = &fbi->fix;
1172         unsigned int end;
1173         unsigned int start;
1174         unsigned long irq_flags;
1176         if (var->xoffset != fbi->var.xoffset ||
1177                         var->yoffset != fbi->var.yoffset) {
1178                 memcpy(&new_var, &fbi->var, sizeof(new_var));
1179                 new_var.xoffset = var->xoffset;
1180                 new_var.yoffset = var->yoffset;
1181                 if (fb_check_var(&new_var, fbi))
1182                         ret = -EINVAL;
1183                 else {
1184                         memcpy(&fbi->var, &new_var, sizeof(new_var));
1186                         start   = fix->smem_start +
1187                                 new_var.yoffset * fix->line_length +
1188                                 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1189                         end     = start + fbi->var.yres * fix->line_length - 1;
1190                         par->dma_start  = start;
1191                         par->dma_end    = end;
1192                         spin_lock_irqsave(&par->lock_for_chan_update,
1193                                         irq_flags);
1194                         if (par->which_dma_channel_done == 0) {
1195                                 lcdc_write(par->dma_start,
1196                                            LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1197                                 lcdc_write(par->dma_end,
1198                                            LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1199                         } else if (par->which_dma_channel_done == 1) {
1200                                 lcdc_write(par->dma_start,
1201                                            LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1202                                 lcdc_write(par->dma_end,
1203                                            LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1204                         }
1205                         spin_unlock_irqrestore(&par->lock_for_chan_update,
1206                                         irq_flags);
1207                 }
1208         }
1210         return ret;
1213 static struct fb_ops da8xx_fb_ops = {
1214         .owner = THIS_MODULE,
1215         .fb_check_var = fb_check_var,
1216         .fb_setcolreg = fb_setcolreg,
1217         .fb_pan_display = da8xx_pan_display,
1218         .fb_ioctl = fb_ioctl,
1219         .fb_fillrect = cfb_fillrect,
1220         .fb_copyarea = cfb_copyarea,
1221         .fb_imageblit = cfb_imageblit,
1222         .fb_blank = cfb_blank,
1223 };
1225 static int __devinit fb_probe(struct platform_device *device)
1227         struct da8xx_lcdc_platform_data *fb_pdata =
1228                                                 device->dev.platform_data;
1229         struct lcd_ctrl_config *lcd_cfg;
1230         struct da8xx_panel *lcdc_info;
1231         struct fb_info *da8xx_fb_info;
1232         struct clk *fb_clk = NULL;
1233         struct da8xx_fb_par *par;
1234         resource_size_t len;
1235         int ret, i;
1237         if (fb_pdata == NULL) {
1238                 dev_err(&device->dev, "Can not get platform data\n");
1239                 return -ENOENT;
1240         }
1242         lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1243         if (!lcdc_regs) {
1244                 dev_err(&device->dev,
1245                         "Can not get memory resource for LCD controller\n");
1246                 return -ENOENT;
1247         }
1249         len = resource_size(lcdc_regs);
1251         lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
1252         if (!lcdc_regs)
1253                 return -EBUSY;
1255         da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
1256         if (!da8xx_fb_reg_base) {
1257                 ret = -EBUSY;
1258                 goto err_request_mem;
1259         }
1261         fb_clk = clk_get(&device->dev, NULL);
1262         if (IS_ERR(fb_clk)) {
1263                 dev_err(&device->dev, "Can not get device clock\n");
1264                 ret = -ENODEV;
1265                 goto err_ioremap;
1266         }
1268         pm_runtime_irq_safe(&device->dev);
1269         pm_runtime_enable(&device->dev);
1270         pm_runtime_get_sync(&device->dev);
1273         /* Determine LCD IP Version */
1274         switch (lcdc_read(LCD_PID_REG)) {
1275         case 0x4C100102:
1276                 lcd_revision = LCD_VERSION_1;
1277                 break;
1278         case 0x4F200800:
1279         case 0x4F201000:
1280                 lcd_revision = LCD_VERSION_2;
1281                 break;
1282         default:
1283                 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1284                                 "defaulting to LCD revision 1\n",
1285                                 lcdc_read(LCD_PID_REG));
1286                 lcd_revision = LCD_VERSION_1;
1287                 break;
1288         }
1290         for (i = 0, lcdc_info = known_lcd_panels;
1291                 i < ARRAY_SIZE(known_lcd_panels);
1292                 i++, lcdc_info++) {
1293                 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1294                         break;
1295         }
1297         if (i == ARRAY_SIZE(known_lcd_panels)) {
1298                 dev_err(&device->dev, "GLCD: No valid panel found\n");
1299                 ret = -ENODEV;
1300                 goto err_pm_runtime_disable;
1301         } else
1302                 dev_info(&device->dev, "GLCD: Found %s panel\n",
1303                                         fb_pdata->type);
1305         lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1307         da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1308                                         &device->dev);
1309         if (!da8xx_fb_info) {
1310                 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1311                 ret = -ENOMEM;
1312                 goto err_pm_runtime_disable;
1313         }
1315         par = da8xx_fb_info->par;
1316         par->dev = &device->dev;
1317         par->lcdc_clk = fb_clk;
1318 #ifdef CONFIG_CPU_FREQ
1319         par->lcd_fck_rate = clk_get_rate(fb_clk);
1320 #endif
1321         par->pxl_clk = lcdc_info->pxl_clk;
1322         if (fb_pdata->panel_power_ctrl) {
1323                 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1324                 par->panel_power_ctrl(1);
1325         }
1327         if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
1328                 dev_err(&device->dev, "lcd_init failed\n");
1329                 ret = -EFAULT;
1330                 goto err_release_fb;
1331         }
1333         /* allocate frame buffer */
1334         par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
1335         par->vram_size = PAGE_ALIGN(par->vram_size/8);
1336         par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1338         par->vram_virt = dma_alloc_coherent(NULL,
1339                                             par->vram_size,
1340                                             (resource_size_t *) &par->vram_phys,
1341                                             GFP_KERNEL | GFP_DMA);
1342         if (!par->vram_virt) {
1343                 dev_err(&device->dev,
1344                         "GLCD: kmalloc for frame buffer failed\n");
1345                 ret = -EINVAL;
1346                 goto err_release_fb;
1347         }
1349         da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1350         da8xx_fb_fix.smem_start    = par->vram_phys;
1351         da8xx_fb_fix.smem_len      = par->vram_size;
1352         da8xx_fb_fix.line_length   = (lcdc_info->width * lcd_cfg->bpp) / 8;
1354         par->dma_start = par->vram_phys;
1355         par->dma_end   = par->dma_start + lcdc_info->height *
1356                 da8xx_fb_fix.line_length - 1;
1358         /* allocate palette buffer */
1359         par->v_palette_base = dma_alloc_coherent(NULL,
1360                                                PALETTE_SIZE,
1361                                                (resource_size_t *)
1362                                                &par->p_palette_base,
1363                                                GFP_KERNEL | GFP_DMA);
1364         if (!par->v_palette_base) {
1365                 dev_err(&device->dev,
1366                         "GLCD: kmalloc for palette buffer failed\n");
1367                 ret = -EINVAL;
1368                 goto err_release_fb_mem;
1369         }
1370         memset(par->v_palette_base, 0, PALETTE_SIZE);
1372         par->irq = platform_get_irq(device, 0);
1373         if (par->irq < 0) {
1374                 ret = -ENOENT;
1375                 goto err_release_pl_mem;
1376         }
1378         /* Initialize par */
1379         da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
1381         da8xx_fb_var.xres = lcdc_info->width;
1382         da8xx_fb_var.xres_virtual = lcdc_info->width;
1384         da8xx_fb_var.yres         = lcdc_info->height;
1385         da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
1387         da8xx_fb_var.grayscale =
1388             lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
1389         da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1391         da8xx_fb_var.hsync_len = lcdc_info->hsw;
1392         da8xx_fb_var.vsync_len = lcdc_info->vsw;
1394         da8xx_fb_var.right_margin = lcdc_info->hfp;
1395         da8xx_fb_var.left_margin  = lcdc_info->hbp;
1396         da8xx_fb_var.lower_margin = lcdc_info->vfp;
1397         da8xx_fb_var.upper_margin = lcdc_info->vbp;
1399         /* Initialize fbinfo */
1400         da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1401         da8xx_fb_info->fix = da8xx_fb_fix;
1402         da8xx_fb_info->var = da8xx_fb_var;
1403         da8xx_fb_info->fbops = &da8xx_fb_ops;
1404         da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1405         da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1406                                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1408         ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1409         if (ret)
1410                 goto err_release_pl_mem;
1411         da8xx_fb_info->cmap.len = par->palette_sz;
1413         /* initialize var_screeninfo */
1414         da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1415         fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1417         dev_set_drvdata(&device->dev, da8xx_fb_info);
1419         /* initialize the vsync wait queue */
1420         init_waitqueue_head(&par->vsync_wait);
1421         par->vsync_timeout = HZ / 5;
1422         par->which_dma_channel_done = -1;
1423         spin_lock_init(&par->lock_for_chan_update);
1425         /* Register the Frame Buffer  */
1426         if (register_framebuffer(da8xx_fb_info) < 0) {
1427                 dev_err(&device->dev,
1428                         "GLCD: Frame Buffer Registration Failed!\n");
1429                 ret = -EINVAL;
1430                 goto err_dealloc_cmap;
1431         }
1433 #ifdef CONFIG_CPU_FREQ
1434         ret = lcd_da8xx_cpufreq_register(par);
1435         if (ret) {
1436                 dev_err(&device->dev, "failed to register cpufreq\n");
1437                 goto err_cpu_freq;
1438         }
1439 #endif
1441         if (lcd_revision == LCD_VERSION_1)
1442                 lcdc_irq_handler = lcdc_irq_handler_rev01;
1443         else
1444                 lcdc_irq_handler = lcdc_irq_handler_rev02;
1446         ret = request_irq(par->irq, lcdc_irq_handler, 0,
1447                         DRIVER_NAME, par);
1448         if (ret)
1449                 goto irq_freq;
1450         return 0;
1452 irq_freq:
1453 #ifdef CONFIG_CPU_FREQ
1454         lcd_da8xx_cpufreq_deregister(par);
1455 err_cpu_freq:
1456 #endif
1457         unregister_framebuffer(da8xx_fb_info);
1459 err_dealloc_cmap:
1460         fb_dealloc_cmap(&da8xx_fb_info->cmap);
1462 err_release_pl_mem:
1463         dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1464                           par->p_palette_base);
1466 err_release_fb_mem:
1467         dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1469 err_release_fb:
1470         framebuffer_release(da8xx_fb_info);
1472 err_pm_runtime_disable:
1473         pm_runtime_put_sync(&device->dev);
1474         pm_runtime_disable(&device->dev);
1476 err_ioremap:
1478         iounmap((void __iomem *)da8xx_fb_reg_base);
1480 err_request_mem:
1481         release_mem_region(lcdc_regs->start, len);
1483         return ret;
1486 #ifdef CONFIG_PM
1488 struct lcdc_context {
1489         u32 clk_enable;
1490         u32 ctrl;
1491         u32 dma_ctrl;
1492         u32 raster_timing_0;
1493         u32 raster_timing_1;
1494         u32 raster_timing_2;
1495         u32 int_enable_set;
1496         u32 dma_frm_buf_base_addr_0;
1497         u32 dma_frm_buf_ceiling_addr_0;
1498         u32 dma_frm_buf_base_addr_1;
1499         u32 dma_frm_buf_ceiling_addr_1;
1500         u32 raster_ctrl;
1501 } reg_context;
1503 static void lcd_context_save(void)
1505         reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG);
1506         reg_context.ctrl = lcdc_read(LCD_CTRL_REG);
1507         reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG);
1508         reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG);
1509         reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG);
1510         reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG);
1511         reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG);
1512         reg_context.dma_frm_buf_base_addr_0 =
1513                 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1514         reg_context.dma_frm_buf_ceiling_addr_0 =
1515                 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1516         reg_context.dma_frm_buf_base_addr_1 =
1517                 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1518         reg_context.dma_frm_buf_ceiling_addr_1 =
1519                 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1520         reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG);
1521         return;
1524 static void lcd_context_restore(void)
1526         lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG);
1527         lcdc_write(reg_context.ctrl, LCD_CTRL_REG);
1528         lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG);
1529         lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG);
1530         lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG);
1531         lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG);
1532         lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG);
1533         lcdc_write(reg_context.dma_frm_buf_base_addr_0,
1534                         LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1535         lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0,
1536                         LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1537         lcdc_write(reg_context.dma_frm_buf_base_addr_1,
1538                         LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1539         lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1,
1540                         LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1541         lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG);
1542         return;
1545 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1547         struct fb_info *info = platform_get_drvdata(dev);
1548         struct da8xx_fb_par *par = info->par;
1550         console_lock();
1551         if (par->panel_power_ctrl)
1552                 par->panel_power_ctrl(0);
1554         fb_set_suspend(info, 1);
1555         lcd_disable_raster(WAIT_FOR_FRAME_DONE);
1556         lcd_context_save();
1558         pm_runtime_put_sync(&dev->dev);
1559         console_unlock();
1561         return 0;
1563 static int fb_resume(struct platform_device *dev)
1565         struct fb_info *info = platform_get_drvdata(dev);
1566         struct da8xx_fb_par *par = info->par;
1568         console_lock();
1569         if (par->panel_power_ctrl)
1570                 par->panel_power_ctrl(1);
1572         pm_runtime_get_sync(&dev->dev);
1574         lcd_context_restore();
1575         lcd_enable_raster();
1577         if (par->panel_power_ctrl)
1578                 par->panel_power_ctrl(1);
1580         fb_set_suspend(info, 0);
1581         console_unlock();
1583         return 0;
1585 #else
1586 #define fb_suspend NULL
1587 #define fb_resume NULL
1588 #endif
1590 static struct platform_driver da8xx_fb_driver = {
1591         .probe = fb_probe,
1592         .remove = __devexit_p(fb_remove),
1593         .suspend = fb_suspend,
1594         .resume = fb_resume,
1595         .driver = {
1596                    .name = DRIVER_NAME,
1597                    .owner = THIS_MODULE,
1598                    },
1599 };
1601 static int __init da8xx_fb_init(void)
1603         return platform_driver_register(&da8xx_fb_driver);
1606 static void __exit da8xx_fb_cleanup(void)
1608         platform_driver_unregister(&da8xx_fb_driver);
1611 module_init(da8xx_fb_init);
1612 module_exit(da8xx_fb_cleanup);
1614 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1615 MODULE_AUTHOR("Texas Instruments");
1616 MODULE_LICENSE("GPL");