1 /*
2 * Copyright (C) 2008-2009 MontaVista Software Inc.
3 * Copyright (C) 2008-2009 Texas Instruments Inc
4 *
5 * Based on the LCD driver for TI Avalanche processors written by
6 * Ajay Singh and Shalom Hai.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option)any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/fb.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/interrupt.h>
30 #include <linux/clk.h>
31 #include <linux/cpufreq.h>
32 #include <linux/console.h>
33 #include <linux/spinlock.h>
34 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/pm_runtime.h>
37 #include <video/da8xx-fb.h>
38 #include <asm/mach-types.h>
40 #define DRIVER_NAME "da8xx_lcdc"
42 #define LCD_VERSION_1 1
43 #define LCD_VERSION_2 2
45 /* LCD Status Register */
46 #define LCD_END_OF_FRAME1 BIT(9)
47 #define LCD_END_OF_FRAME0 BIT(8)
48 #define LCD_PL_LOAD_DONE BIT(6)
49 #define LCD_FIFO_UNDERFLOW BIT(5)
50 #define LCD_SYNC_LOST BIT(2)
52 /* LCD DMA Control Register */
53 #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
54 #define LCD_DMA_BURST_1 0x0
55 #define LCD_DMA_BURST_2 0x1
56 #define LCD_DMA_BURST_4 0x2
57 #define LCD_DMA_BURST_8 0x3
58 #define LCD_DMA_BURST_16 0x4
59 #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)
60 #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8)
61 #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9)
62 #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
64 /* LCD Control Register */
65 #define LCD_CLK_DIVISOR(x) ((x) << 8)
66 #define LCD_RASTER_MODE 0x01
68 /* LCD Raster Control Register */
69 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
70 #define PALETTE_AND_DATA 0x00
71 #define PALETTE_ONLY 0x01
72 #define DATA_ONLY 0x02
74 #define LCD_MONO_8BIT_MODE BIT(9)
75 #define LCD_RASTER_ORDER BIT(8)
76 #define LCD_TFT_MODE BIT(7)
77 #define LCD_V1_UNDERFLOW_INT_ENA BIT(6)
78 #define LCD_V2_UNDERFLOW_INT_ENA BIT(5)
79 #define LCD_V1_PL_INT_ENA BIT(4)
80 #define LCD_V2_PL_INT_ENA BIT(6)
81 #define LCD_MONOCHROME_MODE BIT(1)
82 #define LCD_RASTER_ENABLE BIT(0)
83 #define LCD_TFT_ALT_ENABLE BIT(23)
84 #define LCD_STN_565_ENABLE BIT(24)
85 #define LCD_V2_DMA_CLK_EN BIT(2)
86 #define LCD_V2_LIDD_CLK_EN BIT(1)
87 #define LCD_V2_CORE_CLK_EN BIT(0)
88 #define LCD_V2_LPP_B10 26
89 #define LCD_V2_TFT_24BPP_MODE BIT(25)
90 #define LCD_V2_TFT_24BPP_UNPACK BIT(26)
92 /* LCD Raster Timing 2 Register */
93 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
94 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
95 #define LCD_SYNC_CTRL BIT(25)
96 #define LCD_SYNC_EDGE BIT(24)
97 #define LCD_INVERT_PIXEL_CLOCK BIT(22)
98 #define LCD_INVERT_LINE_CLOCK BIT(21)
99 #define LCD_INVERT_FRAME_CLOCK BIT(20)
101 /* LCD Block */
102 #define LCD_PID_REG 0x0
103 #define LCD_CTRL_REG 0x4
104 #define LCD_STAT_REG 0x8
105 #define LCD_RASTER_CTRL_REG 0x28
106 #define LCD_RASTER_TIMING_0_REG 0x2C
107 #define LCD_RASTER_TIMING_1_REG 0x30
108 #define LCD_RASTER_TIMING_2_REG 0x34
109 #define LCD_DMA_CTRL_REG 0x40
110 #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44
111 #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
112 #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C
113 #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50
115 /* Interrupt Registers available only in Version 2 */
116 #define LCD_RAW_STAT_REG 0x58
117 #define LCD_MASKED_STAT_REG 0x5c
118 #define LCD_INT_ENABLE_SET_REG 0x60
119 #define LCD_INT_ENABLE_CLR_REG 0x64
120 #define LCD_END_OF_INT_IND_REG 0x68
122 /* Clock registers available only on Version 2 */
123 #define LCD_CLK_ENABLE_REG 0x6c
124 #define LCD_CLK_RESET_REG 0x70
125 #define LCD_CLK_MAIN_RESET BIT(3)
127 #define LCD_NUM_BUFFERS 2
129 #define WSI_TIMEOUT 50
130 #define PALETTE_SIZE 256
131 #define LEFT_MARGIN 64
132 #define RIGHT_MARGIN 64
133 #define UPPER_MARGIN 32
134 #define LOWER_MARGIN 32
135 #define WAIT_FOR_FRAME_DONE true
136 #define NO_WAIT_FOR_FRAME_DONE false
138 static resource_size_t da8xx_fb_reg_base;
139 static struct resource *lcdc_regs;
140 static unsigned int lcd_revision;
141 static irq_handler_t lcdc_irq_handler;
143 static inline unsigned int lcdc_read(unsigned int addr)
144 {
145 return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
146 }
148 static inline void lcdc_write(unsigned int val, unsigned int addr)
149 {
150 __raw_writel(val, da8xx_fb_reg_base + (addr));
151 }
153 struct da8xx_fb_par {
154 struct device *dev;
155 resource_size_t p_palette_base;
156 unsigned char *v_palette_base;
157 dma_addr_t vram_phys;
158 unsigned long vram_size;
159 void *vram_virt;
160 unsigned int dma_start;
161 unsigned int dma_end;
162 struct clk *lcdc_clk;
163 int irq;
164 unsigned long pseudo_palette[32];
165 unsigned int palette_sz;
166 unsigned int pxl_clk;
167 int blank;
168 wait_queue_head_t vsync_wait;
169 int vsync_flag;
170 int vsync_timeout;
171 spinlock_t lock_for_chan_update;
173 /*
174 * LCDC has 2 ping pong DMA channels, channel 0
175 * and channel 1.
176 */
177 unsigned int which_dma_channel_done;
178 #ifdef CONFIG_CPU_FREQ
179 struct notifier_block freq_transition;
180 unsigned int lcd_fck_rate;
181 #endif
182 void (*panel_power_ctrl)(int);
183 };
185 /* Variable Screen Information */
186 static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
187 .xoffset = 0,
188 .yoffset = 0,
189 .transp = {0, 0, 0},
190 .nonstd = 0,
191 .activate = 0,
192 .height = -1,
193 .width = -1,
194 .pixclock = 33333,/*Pico Sec*/
195 .accel_flags = 0,
196 .left_margin = LEFT_MARGIN,
197 .right_margin = RIGHT_MARGIN,
198 .upper_margin = UPPER_MARGIN,
199 .lower_margin = LOWER_MARGIN,
200 .sync = 0,
201 .vmode = FB_VMODE_NONINTERLACED
202 };
204 static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
205 .id = "DA8xx FB Drv",
206 .type = FB_TYPE_PACKED_PIXELS,
207 .type_aux = 0,
208 .visual = FB_VISUAL_PSEUDOCOLOR,
209 .xpanstep = 0,
210 .ypanstep = 1,
211 .ywrapstep = 0,
212 .accel = FB_ACCEL_NONE
213 };
215 struct da8xx_panel {
216 const char name[25]; /* Full name <vendor>_<model> */
217 unsigned short width;
218 unsigned short height;
219 int hfp; /* Horizontal front porch */
220 int hbp; /* Horizontal back porch */
221 int hsw; /* Horizontal Sync Pulse Width */
222 int vfp; /* Vertical front porch */
223 int vbp; /* Vertical back porch */
224 int vsw; /* Vertical Sync Pulse Width */
225 unsigned int pxl_clk; /* Pixel clock */
226 unsigned char invert_pxl_clk; /* Invert Pixel clock */
227 };
229 static vsync_callback_t vsync_cb_handler;
230 static void *vsync_cb_arg;
232 static struct da8xx_panel known_lcd_panels[] = {
233 /* Sharp LCD035Q3DG01 */
234 [0] = {
235 .name = "Sharp_LCD035Q3DG01",
236 .width = 320,
237 .height = 240,
238 .hfp = 8,
239 .hbp = 6,
240 .hsw = 0,
241 .vfp = 2,
242 .vbp = 2,
243 .vsw = 0,
244 .pxl_clk = 4608000,
245 .invert_pxl_clk = 1,
246 },
247 /* Sharp LK043T1DG01 */
248 [1] = {
249 .name = "Sharp_LK043T1DG01",
250 .width = 480,
251 .height = 272,
252 .hfp = 2,
253 .hbp = 2,
254 .hsw = 41,
255 .vfp = 3,
256 .vbp = 3,
257 .vsw = 10,
258 .pxl_clk = 7833600,
259 .invert_pxl_clk = 0,
260 },
261 /* ThreeFive S9700RTWV35TR */
262 [2] = {
263 .name = "TFC_S9700RTWV35TR_01B",
264 .width = 800,
265 .height = 480,
266 .hfp = 39,
267 .hbp = 39,
268 .hsw = 47,
269 .vfp = 13,
270 .vbp = 29,
271 .vsw = 2,
272 .pxl_clk = 30000000,
273 .invert_pxl_clk = 0,
274 },
275 };
277 /* Enable the Raster Engine of the LCD Controller */
278 static inline void lcd_enable_raster(void)
279 {
280 u32 reg;
282 /* Bring LCDC out of reset */
283 if (lcd_revision == LCD_VERSION_2)
284 lcdc_write(0, LCD_CLK_RESET_REG);
286 reg = lcdc_read(LCD_RASTER_CTRL_REG);
287 if (!(reg & LCD_RASTER_ENABLE))
288 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
289 }
291 /* Disable the Raster Engine of the LCD Controller */
292 static inline void lcd_disable_raster(bool wait_for_frame_done)
293 {
294 u32 reg;
295 u32 loop_cnt = 0;
296 u32 stat;
297 u32 i = 0;
299 if (wait_for_frame_done)
300 loop_cnt = 5000;
302 reg = lcdc_read(LCD_RASTER_CTRL_REG);
303 if (reg & LCD_RASTER_ENABLE)
304 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
306 /* Wait for the current frame to complete */
307 do {
308 if (lcd_revision == LCD_VERSION_1)
309 stat = lcdc_read(LCD_STAT_REG);
310 else
311 stat = lcdc_read(LCD_RAW_STAT_REG);
313 mdelay(1);
314 } while (!(stat & BIT(0)) && (i++ < loop_cnt));
316 if (lcd_revision == LCD_VERSION_1)
317 lcdc_write(stat, LCD_STAT_REG);
318 else
319 lcdc_write(stat, LCD_MASKED_STAT_REG);
321 if ((loop_cnt != 0) && (i >= loop_cnt)) {
322 printk(KERN_ERR "LCD Controller timed out\n");
323 return;
324 }
326 if (lcd_revision == LCD_VERSION_2)
327 /* Write 1 to reset LCDC */
328 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
329 }
331 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
332 {
333 u32 start;
334 u32 end;
335 u32 reg_ras;
336 u32 reg_dma;
337 u32 reg_int;
339 /* init reg to clear PLM (loading mode) fields */
340 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
341 reg_ras &= ~(3 << 20);
343 reg_dma = lcdc_read(LCD_DMA_CTRL_REG);
345 if (load_mode == LOAD_DATA) {
346 start = par->dma_start;
347 end = par->dma_end;
349 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
350 if (lcd_revision == LCD_VERSION_1) {
351 reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
352 } else {
353 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
354 LCD_V2_END_OF_FRAME0_INT_ENA |
355 LCD_V2_END_OF_FRAME1_INT_ENA;
356 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
357 }
358 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
360 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
361 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
362 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
363 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
364 } else if (load_mode == LOAD_PALETTE) {
365 start = par->p_palette_base;
366 end = start + par->palette_sz - 1;
368 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
370 if (lcd_revision == LCD_VERSION_1) {
371 reg_ras |= LCD_V1_PL_INT_ENA;
372 } else {
373 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
374 LCD_V2_PL_INT_ENA;
375 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
376 }
378 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
379 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
380 }
382 lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
383 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
385 /*
386 * The Raster enable bit must be set after all other control fields are
387 * set.
388 */
389 lcd_enable_raster();
390 }
392 /* Configure the Burst Size and fifo threhold of DMA */
393 static int lcd_cfg_dma(int burst_size, int fifo_th)
394 {
395 u32 reg;
397 reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
398 switch (burst_size) {
399 case 1:
400 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
401 break;
402 case 2:
403 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
404 break;
405 case 4:
406 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
407 break;
408 case 8:
409 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
410 break;
411 case 16:
412 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
413 break;
414 default:
415 return -EINVAL;
416 }
418 reg |= (fifo_th << 8);
420 lcdc_write(reg, LCD_DMA_CTRL_REG);
422 return 0;
423 }
425 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
426 {
427 u32 reg;
429 /* Set the AC Bias Period and Number of Transisitons per Interrupt */
430 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
431 reg |= LCD_AC_BIAS_FREQUENCY(period) |
432 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
433 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
434 }
436 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
437 int front_porch)
438 {
439 u32 reg;
441 reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
442 reg |= ((back_porch & 0xff) << 24)
443 | ((front_porch & 0xff) << 16)
444 | ((pulse_width & 0x3f) << 10);
445 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
446 }
448 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
449 int front_porch)
450 {
451 u32 reg;
453 reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
454 reg |= ((back_porch & 0xff) << 24)
455 | ((front_porch & 0xff) << 16)
456 | ((pulse_width & 0x3f) << 10);
457 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
458 }
460 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
461 {
462 u32 reg;
463 u32 reg_int;
465 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
466 LCD_MONO_8BIT_MODE |
467 LCD_MONOCHROME_MODE);
469 switch (cfg->p_disp_panel->panel_shade) {
470 case MONOCHROME:
471 reg |= LCD_MONOCHROME_MODE;
472 if (cfg->mono_8bit_mode)
473 reg |= LCD_MONO_8BIT_MODE;
474 break;
475 case COLOR_ACTIVE:
476 reg |= LCD_TFT_MODE;
477 if (cfg->tft_alt_mode)
478 reg |= LCD_TFT_ALT_ENABLE;
479 break;
481 case COLOR_PASSIVE:
482 if (cfg->stn_565_mode)
483 reg |= LCD_STN_565_ENABLE;
484 break;
486 default:
487 return -EINVAL;
488 }
490 /* enable additional interrupts here */
491 if (lcd_revision == LCD_VERSION_1) {
492 reg |= LCD_V1_UNDERFLOW_INT_ENA;
493 } else {
494 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
495 LCD_V2_UNDERFLOW_INT_ENA;
496 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
497 }
499 lcdc_write(reg, LCD_RASTER_CTRL_REG);
501 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
503 if (cfg->sync_ctrl)
504 reg |= LCD_SYNC_CTRL;
505 else
506 reg &= ~LCD_SYNC_CTRL;
508 if (cfg->sync_edge)
509 reg |= LCD_SYNC_EDGE;
510 else
511 reg &= ~LCD_SYNC_EDGE;
513 if (cfg->invert_line_clock)
514 reg |= LCD_INVERT_LINE_CLOCK;
515 else
516 reg &= ~LCD_INVERT_LINE_CLOCK;
518 if (cfg->invert_frm_clock)
519 reg |= LCD_INVERT_FRAME_CLOCK;
520 else
521 reg &= ~LCD_INVERT_FRAME_CLOCK;
523 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
525 return 0;
526 }
528 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
529 u32 bpp, u32 raster_order)
530 {
531 u32 reg;
533 /* Set the Panel Width */
534 /* Pixels per line = (PPL + 1)*16 */
535 if (lcd_revision == LCD_VERSION_1) {
536 /*
537 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
538 * pixels.
539 */
540 width &= 0x3f0;
541 } else {
542 /*
543 * 0x7F in bits 4..10 gives max horizontal resolution = 2048
544 * pixels.
545 */
546 width &= 0x7f0;
547 }
549 reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
550 reg &= 0xfffffc00;
551 if (lcd_revision == LCD_VERSION_1) {
552 reg |= ((width >> 4) - 1) << 4;
553 } else {
554 width = (width >> 4) - 1;
555 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
556 }
557 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
559 /* Set the Panel Height */
560 /* Set bits 9:0 of Lines Per Pixel */
561 reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
562 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
563 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
565 /* Set bit 10 of Lines Per Pixel */
566 if (lcd_revision == LCD_VERSION_2) {
567 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
568 reg |= ((height - 1) & 0x400) << 16;
569 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
570 }
572 /* Set the Raster Order of the Frame Buffer */
573 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
574 if (raster_order)
575 reg |= LCD_RASTER_ORDER;
577 if (bpp == 24)
578 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
579 else if (bpp == 32)
580 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
581 | LCD_V2_TFT_24BPP_UNPACK);
583 lcdc_write(reg, LCD_RASTER_CTRL_REG);
585 switch (bpp) {
586 case 1:
587 case 2:
588 case 4:
589 case 16:
590 case 24:
591 case 32:
592 par->palette_sz = 16 * 2;
593 break;
595 case 8:
596 par->palette_sz = 256 * 2;
597 break;
599 default:
600 return -EINVAL;
601 }
603 return 0;
604 }
606 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
607 unsigned blue, unsigned transp,
608 struct fb_info *info)
609 {
610 struct da8xx_fb_par *par = info->par;
611 unsigned short *palette = (unsigned short *) par->v_palette_base;
612 u_short pal;
613 int update_hw = 0;
615 if (regno > 255)
616 return 1;
618 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
619 return 1;
621 if (info->var.bits_per_pixel == 8) {
622 red >>= 4;
623 green >>= 8;
624 blue >>= 12;
626 pal = (red & 0x0f00);
627 pal |= (green & 0x00f0);
628 pal |= (blue & 0x000f);
630 if (palette[regno] != pal) {
631 update_hw = 1;
632 palette[regno] = pal;
633 }
634 } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
635 red >>= (16 - info->var.red.length);
636 red <<= info->var.red.offset;
638 green >>= (16 - info->var.green.length);
639 green <<= info->var.green.offset;
641 blue >>= (16 - info->var.blue.length);
642 blue <<= info->var.blue.offset;
644 par->pseudo_palette[regno] = red | green | blue;
646 if (palette[0] != 0x4000) {
647 update_hw = 1;
648 palette[0] = 0x4000;
649 }
650 } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
651 ((info->var.bits_per_pixel == 24) && regno < 24)) {
652 red >>= (24 - info->var.red.length);
653 red <<= info->var.red.offset;
655 green >>= (24 - info->var.green.length);
656 green <<= info->var.green.offset;
658 blue >>= (24 - info->var.blue.length);
659 blue <<= info->var.blue.offset;
661 par->pseudo_palette[regno] = red | green | blue;
663 if (palette[0] != 0x4000) {
664 update_hw = 1;
665 palette[0] = 0x4000;
666 }
667 }
669 /* Update the palette in the h/w as needed. */
670 if (update_hw)
671 lcd_blit(LOAD_PALETTE, par);
673 return 0;
674 }
676 static void lcd_reset(struct da8xx_fb_par *par)
677 {
678 /* Disable the Raster if previously Enabled */
679 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
681 /* DMA has to be disabled */
682 lcdc_write(0, LCD_DMA_CTRL_REG);
683 lcdc_write(0, LCD_RASTER_CTRL_REG);
685 if (lcd_revision == LCD_VERSION_2) {
686 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
687 /* Write 1 to reset */
688 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
689 lcdc_write(0, LCD_CLK_RESET_REG);
690 }
691 }
693 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
694 {
695 unsigned int lcd_clk, div;
697 lcd_clk = clk_get_rate(par->lcdc_clk);
698 div = lcd_clk / par->pxl_clk;
700 /* Configure the LCD clock divisor. */
701 lcdc_write(LCD_CLK_DIVISOR(div) |
702 (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
704 if (lcd_revision == LCD_VERSION_2)
705 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
706 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
708 }
710 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
711 struct da8xx_panel *panel)
712 {
713 u32 bpp;
714 int ret = 0;
716 lcd_reset(par);
718 /* Calculate the divider */
719 lcd_calc_clk_divider(par);
721 if (panel->invert_pxl_clk)
722 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
723 LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
724 else
725 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
726 ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
728 /* Configure the DMA burst size and fifo threshold. */
729 ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
730 if (ret < 0)
731 return ret;
733 /* Configure the AC bias properties. */
734 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
736 /* Configure the vertical and horizontal sync properties. */
737 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
738 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
740 /* Configure for disply */
741 ret = lcd_cfg_display(cfg);
742 if (ret < 0)
743 return ret;
746 if ((QVGA != cfg->p_disp_panel->panel_type) &&
747 (WVGA != cfg->p_disp_panel->panel_type))
748 return -EINVAL;
750 if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
751 cfg->bpp >= cfg->p_disp_panel->min_bpp)
752 bpp = cfg->bpp;
753 else
754 bpp = cfg->p_disp_panel->max_bpp;
755 if (bpp == 12)
756 bpp = 16;
757 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
758 (unsigned int)panel->height, bpp,
759 cfg->raster_order);
760 if (ret < 0)
761 return ret;
763 /* Configure FDD */
764 lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
765 (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
767 return 0;
768 }
770 int register_vsync_cb(vsync_callback_t handler, void *arg, int idx)
771 {
772 if ((vsync_cb_handler == NULL) && (vsync_cb_arg == NULL)) {
773 vsync_cb_handler = handler;
774 vsync_cb_arg = arg;
775 } else {
776 return -EEXIST;
777 }
779 return 0;
780 }
781 EXPORT_SYMBOL(register_vsync_cb);
783 int unregister_vsync_cb(vsync_callback_t handler, void *arg, int idx)
784 {
785 if ((vsync_cb_handler == handler) && (vsync_cb_arg == arg)) {
786 vsync_cb_handler = NULL;
787 vsync_cb_arg = NULL;
788 } else {
789 return -ENXIO;
790 }
792 return 0;
793 }
794 EXPORT_SYMBOL(unregister_vsync_cb);
796 /* IRQ handler for version 2 of LCDC */
797 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
798 {
799 struct da8xx_fb_par *par = arg;
800 u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
801 struct device *dev = par->dev;
802 u32 reg_int;
804 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
805 printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
806 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
807 pm_runtime_put_sync(dev);
808 lcdc_write(stat, LCD_MASKED_STAT_REG);
809 lcd_enable_raster();
810 pm_runtime_get_sync(dev);
811 } else if (stat & LCD_PL_LOAD_DONE) {
812 /*
813 * Must disable raster before changing state of any control bit.
814 * And also must be disabled before clearing the PL loading
815 * interrupt via the following write to the status register. If
816 * this is done after then one gets multiple PL done interrupts.
817 */
818 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
820 lcdc_write(stat, LCD_MASKED_STAT_REG);
822 /* Disable PL completion inerrupt */
823 reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |
824 (LCD_V2_PL_INT_ENA);
825 lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);
827 /* Setup and start data loading mode */
828 lcd_blit(LOAD_DATA, par);
829 } else {
830 lcdc_write(stat, LCD_MASKED_STAT_REG);
832 if (stat & LCD_END_OF_FRAME0) {
833 par->which_dma_channel_done = 0;
834 lcdc_write(par->dma_start,
835 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
836 lcdc_write(par->dma_end,
837 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
838 par->vsync_flag = 1;
839 wake_up_interruptible(&par->vsync_wait);
840 if (vsync_cb_handler)
841 vsync_cb_handler(vsync_cb_arg);
842 }
844 if (stat & LCD_END_OF_FRAME1) {
845 par->which_dma_channel_done = 1;
846 lcdc_write(par->dma_start,
847 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
848 lcdc_write(par->dma_end,
849 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
850 par->vsync_flag = 1;
851 wake_up_interruptible(&par->vsync_wait);
852 if (vsync_cb_handler)
853 vsync_cb_handler(vsync_cb_arg);
854 }
855 }
857 lcdc_write(0, LCD_END_OF_INT_IND_REG);
858 return IRQ_HANDLED;
859 }
861 /* IRQ handler for version 1 LCDC */
862 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
863 {
864 struct da8xx_fb_par *par = arg;
865 u32 stat = lcdc_read(LCD_STAT_REG);
866 u32 reg_ras;
868 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
869 printk(KERN_ERR "LCDC sync lost or underflow error occured\n");
870 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
871 clk_disable(par->lcdc_clk);
872 lcdc_write(stat, LCD_STAT_REG);
873 lcd_enable_raster();
874 clk_enable(par->lcdc_clk);
875 } else if (stat & LCD_PL_LOAD_DONE) {
876 /*
877 * Must disable raster before changing state of any control bit.
878 * And also must be disabled before clearing the PL loading
879 * interrupt via the following write to the status register. If
880 * this is done after then one gets multiple PL done interrupts.
881 */
882 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
884 lcdc_write(stat, LCD_STAT_REG);
886 /* Disable PL completion inerrupt */
887 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
888 reg_ras &= ~LCD_V1_PL_INT_ENA;
889 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
891 /* Setup and start data loading mode */
892 lcd_blit(LOAD_DATA, par);
893 } else {
894 lcdc_write(stat, LCD_STAT_REG);
896 if (stat & LCD_END_OF_FRAME0) {
897 lcdc_write(par->dma_start,
898 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
899 lcdc_write(par->dma_end,
900 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
901 par->vsync_flag = 1;
902 wake_up_interruptible(&par->vsync_wait);
903 }
905 if (stat & LCD_END_OF_FRAME1) {
906 lcdc_write(par->dma_start,
907 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
908 lcdc_write(par->dma_end,
909 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
910 par->vsync_flag = 1;
911 wake_up_interruptible(&par->vsync_wait);
912 }
913 }
915 return IRQ_HANDLED;
916 }
918 static int fb_check_var(struct fb_var_screeninfo *var,
919 struct fb_info *info)
920 {
921 int err = 0;
923 switch (var->bits_per_pixel) {
924 case 1:
925 case 8:
926 var->red.offset = 0;
927 var->red.length = 8;
928 var->green.offset = 0;
929 var->green.length = 8;
930 var->blue.offset = 0;
931 var->blue.length = 8;
932 var->transp.offset = 0;
933 var->transp.length = 0;
934 break;
935 case 4:
936 var->red.offset = 0;
937 var->red.length = 4;
938 var->green.offset = 0;
939 var->green.length = 4;
940 var->blue.offset = 0;
941 var->blue.length = 4;
942 var->transp.offset = 0;
943 var->transp.length = 0;
944 break;
945 case 16: /* RGB 565 */
946 var->red.offset = 11;
947 var->red.length = 5;
948 var->green.offset = 5;
949 var->green.length = 6;
950 var->blue.offset = 0;
951 var->blue.length = 5;
952 var->transp.offset = 0;
953 var->transp.length = 0;
954 break;
955 case 24:
956 var->red.offset = 16;
957 var->red.length = 8;
958 var->green.offset = 8;
959 var->green.length = 8;
960 var->blue.offset = 0;
961 var->blue.length = 8;
962 break;
963 case 32:
964 var->transp.offset = 24;
965 var->transp.length = 8;
966 var->red.offset = 16;
967 var->red.length = 8;
968 var->green.offset = 8;
969 var->green.length = 8;
970 var->blue.offset = 0;
971 var->blue.length = 8;
972 break;
973 default:
974 err = -EINVAL;
975 }
977 var->red.msb_right = 0;
978 var->green.msb_right = 0;
979 var->blue.msb_right = 0;
980 var->transp.msb_right = 0;
981 return err;
982 }
984 #ifdef CONFIG_CPU_FREQ
985 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
986 unsigned long val, void *data)
987 {
988 struct da8xx_fb_par *par;
990 par = container_of(nb, struct da8xx_fb_par, freq_transition);
991 if (val == CPUFREQ_POSTCHANGE) {
992 if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) {
993 lcd_disable_raster(WAIT_FOR_FRAME_DONE);
994 lcd_calc_clk_divider(par);
995 lcd_enable_raster();
996 }
997 }
999 return 0;
1000 }
1002 static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
1003 {
1004 par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
1006 return cpufreq_register_notifier(&par->freq_transition,
1007 CPUFREQ_TRANSITION_NOTIFIER);
1008 }
1010 static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
1011 {
1012 cpufreq_unregister_notifier(&par->freq_transition,
1013 CPUFREQ_TRANSITION_NOTIFIER);
1014 }
1015 #endif
1017 static int __devexit fb_remove(struct platform_device *dev)
1018 {
1019 struct fb_info *info = dev_get_drvdata(&dev->dev);
1021 if (info) {
1022 struct da8xx_fb_par *par = info->par;
1024 #ifdef CONFIG_CPU_FREQ
1025 lcd_da8xx_cpufreq_deregister(par);
1026 #endif
1027 if (par->panel_power_ctrl)
1028 par->panel_power_ctrl(0);
1030 lcd_disable_raster(WAIT_FOR_FRAME_DONE);
1031 lcdc_write(0, LCD_RASTER_CTRL_REG);
1033 /* disable DMA */
1034 lcdc_write(0, LCD_DMA_CTRL_REG);
1036 unregister_framebuffer(info);
1037 fb_dealloc_cmap(&info->cmap);
1038 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1039 par->p_palette_base);
1040 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
1041 par->vram_phys);
1042 free_irq(par->irq, par);
1043 pm_runtime_put_sync(&dev->dev);
1044 pm_runtime_disable(&dev->dev);
1045 framebuffer_release(info);
1046 iounmap((void __iomem *)da8xx_fb_reg_base);
1047 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
1049 }
1050 return 0;
1051 }
1053 /*
1054 * Function to wait for vertical sync which for this LCD peripheral
1055 * translates into waiting for the current raster frame to complete.
1056 */
1057 static int fb_wait_for_vsync(struct fb_info *info)
1058 {
1059 struct da8xx_fb_par *par = info->par;
1060 int ret;
1062 /*
1063 * Set flag to 0 and wait for isr to set to 1. It would seem there is a
1064 * race condition here where the ISR could have occurred just before or
1065 * just after this set. But since we are just coarsely waiting for
1066 * a frame to complete then that's OK. i.e. if the frame completed
1067 * just before this code executed then we have to wait another full
1068 * frame time but there is no way to avoid such a situation. On the
1069 * other hand if the frame completed just after then we don't need
1070 * to wait long at all. Either way we are guaranteed to return to the
1071 * user immediately after a frame completion which is all that is
1072 * required.
1073 */
1074 par->vsync_flag = 0;
1075 ret = wait_event_interruptible_timeout(par->vsync_wait,
1076 par->vsync_flag != 0,
1077 par->vsync_timeout);
1078 if (ret < 0)
1079 return ret;
1080 if (ret == 0)
1081 return -ETIMEDOUT;
1083 if (par->panel_power_ctrl) {
1084 /* Switch off panel power and backlight */
1085 par->panel_power_ctrl(0);
1087 /* Switch on panel power and backlight */
1088 par->panel_power_ctrl(1);
1089 }
1091 return 0;
1092 }
1094 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
1095 unsigned long arg)
1096 {
1097 struct lcd_sync_arg sync_arg;
1099 switch (cmd) {
1100 case FBIOGET_CONTRAST:
1101 case FBIOPUT_CONTRAST:
1102 case FBIGET_BRIGHTNESS:
1103 case FBIPUT_BRIGHTNESS:
1104 case FBIGET_COLOR:
1105 case FBIPUT_COLOR:
1106 return -ENOTTY;
1107 case FBIPUT_HSYNC:
1108 if (copy_from_user(&sync_arg, (char *)arg,
1109 sizeof(struct lcd_sync_arg)))
1110 return -EFAULT;
1111 lcd_cfg_horizontal_sync(sync_arg.back_porch,
1112 sync_arg.pulse_width,
1113 sync_arg.front_porch);
1114 break;
1115 case FBIPUT_VSYNC:
1116 if (copy_from_user(&sync_arg, (char *)arg,
1117 sizeof(struct lcd_sync_arg)))
1118 return -EFAULT;
1119 lcd_cfg_vertical_sync(sync_arg.back_porch,
1120 sync_arg.pulse_width,
1121 sync_arg.front_porch);
1122 break;
1123 case FBIO_WAITFORVSYNC:
1124 return fb_wait_for_vsync(info);
1125 default:
1126 return -EINVAL;
1127 }
1128 return 0;
1129 }
1131 static int cfb_blank(int blank, struct fb_info *info)
1132 {
1133 struct da8xx_fb_par *par = info->par;
1134 int ret = 0;
1136 if (par->blank == blank)
1137 return 0;
1139 par->blank = blank;
1140 switch (blank) {
1141 case FB_BLANK_UNBLANK:
1142 if (par->panel_power_ctrl)
1143 par->panel_power_ctrl(1);
1145 lcd_enable_raster();
1146 break;
1147 case FB_BLANK_POWERDOWN:
1148 if (par->panel_power_ctrl)
1149 par->panel_power_ctrl(0);
1151 lcd_disable_raster(WAIT_FOR_FRAME_DONE);
1152 break;
1153 default:
1154 ret = -EINVAL;
1155 }
1157 return ret;
1158 }
1160 /*
1161 * Set new x,y offsets in the virtual display for the visible area and switch
1162 * to the new mode.
1163 */
1164 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1165 struct fb_info *fbi)
1166 {
1167 int ret = 0;
1168 struct fb_var_screeninfo new_var;
1169 struct da8xx_fb_par *par = fbi->par;
1170 struct fb_fix_screeninfo *fix = &fbi->fix;
1171 unsigned int end;
1172 unsigned int start;
1173 unsigned long irq_flags;
1175 if (var->xoffset != fbi->var.xoffset ||
1176 var->yoffset != fbi->var.yoffset) {
1177 memcpy(&new_var, &fbi->var, sizeof(new_var));
1178 new_var.xoffset = var->xoffset;
1179 new_var.yoffset = var->yoffset;
1180 if (fb_check_var(&new_var, fbi))
1181 ret = -EINVAL;
1182 else {
1183 memcpy(&fbi->var, &new_var, sizeof(new_var));
1185 start = fix->smem_start +
1186 new_var.yoffset * fix->line_length +
1187 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1188 end = start + fbi->var.yres * fix->line_length - 1;
1189 par->dma_start = start;
1190 par->dma_end = end;
1191 spin_lock_irqsave(&par->lock_for_chan_update,
1192 irq_flags);
1193 if (par->which_dma_channel_done == 0) {
1194 lcdc_write(par->dma_start,
1195 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1196 lcdc_write(par->dma_end,
1197 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1198 } else if (par->which_dma_channel_done == 1) {
1199 lcdc_write(par->dma_start,
1200 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1201 lcdc_write(par->dma_end,
1202 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1203 }
1204 spin_unlock_irqrestore(&par->lock_for_chan_update,
1205 irq_flags);
1206 }
1207 }
1209 return ret;
1210 }
1212 static struct fb_ops da8xx_fb_ops = {
1213 .owner = THIS_MODULE,
1214 .fb_check_var = fb_check_var,
1215 .fb_setcolreg = fb_setcolreg,
1216 .fb_pan_display = da8xx_pan_display,
1217 .fb_ioctl = fb_ioctl,
1218 .fb_fillrect = cfb_fillrect,
1219 .fb_copyarea = cfb_copyarea,
1220 .fb_imageblit = cfb_imageblit,
1221 .fb_blank = cfb_blank,
1222 };
1224 static int __devinit fb_probe(struct platform_device *device)
1225 {
1226 struct da8xx_lcdc_platform_data *fb_pdata =
1227 device->dev.platform_data;
1228 struct lcd_ctrl_config *lcd_cfg;
1229 struct da8xx_panel *lcdc_info;
1230 struct fb_info *da8xx_fb_info;
1231 struct clk *fb_clk = NULL;
1232 struct da8xx_fb_par *par;
1233 resource_size_t len;
1234 int ret, i;
1236 if (fb_pdata == NULL) {
1237 dev_err(&device->dev, "Can not get platform data\n");
1238 return -ENOENT;
1239 }
1241 lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1242 if (!lcdc_regs) {
1243 dev_err(&device->dev,
1244 "Can not get memory resource for LCD controller\n");
1245 return -ENOENT;
1246 }
1248 len = resource_size(lcdc_regs);
1250 lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
1251 if (!lcdc_regs)
1252 return -EBUSY;
1254 da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
1255 if (!da8xx_fb_reg_base) {
1256 ret = -EBUSY;
1257 goto err_request_mem;
1258 }
1260 fb_clk = clk_get(&device->dev, NULL);
1261 if (IS_ERR(fb_clk)) {
1262 dev_err(&device->dev, "Can not get device clock\n");
1263 ret = -ENODEV;
1264 goto err_ioremap;
1265 }
1267 pm_runtime_irq_safe(&device->dev);
1268 pm_runtime_enable(&device->dev);
1269 pm_runtime_get_sync(&device->dev);
1272 /* Determine LCD IP Version */
1273 switch (lcdc_read(LCD_PID_REG)) {
1274 case 0x4C100102:
1275 lcd_revision = LCD_VERSION_1;
1276 break;
1277 case 0x4F200800:
1278 case 0x4F201000:
1279 lcd_revision = LCD_VERSION_2;
1280 break;
1281 default:
1282 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1283 "defaulting to LCD revision 1\n",
1284 lcdc_read(LCD_PID_REG));
1285 lcd_revision = LCD_VERSION_1;
1286 break;
1287 }
1289 for (i = 0, lcdc_info = known_lcd_panels;
1290 i < ARRAY_SIZE(known_lcd_panels);
1291 i++, lcdc_info++) {
1292 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1293 break;
1294 }
1296 if (i == ARRAY_SIZE(known_lcd_panels)) {
1297 dev_err(&device->dev, "GLCD: No valid panel found\n");
1298 ret = -ENODEV;
1299 goto err_pm_runtime_disable;
1300 } else
1301 dev_info(&device->dev, "GLCD: Found %s panel\n",
1302 fb_pdata->type);
1304 lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1306 da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1307 &device->dev);
1308 if (!da8xx_fb_info) {
1309 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1310 ret = -ENOMEM;
1311 goto err_pm_runtime_disable;
1312 }
1314 par = da8xx_fb_info->par;
1315 par->dev = &device->dev;
1316 par->lcdc_clk = fb_clk;
1317 #ifdef CONFIG_CPU_FREQ
1318 par->lcd_fck_rate = clk_get_rate(fb_clk);
1319 #endif
1320 par->pxl_clk = lcdc_info->pxl_clk;
1321 if (fb_pdata->panel_power_ctrl) {
1322 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1323 par->panel_power_ctrl(1);
1324 }
1326 if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
1327 dev_err(&device->dev, "lcd_init failed\n");
1328 ret = -EFAULT;
1329 goto err_release_fb;
1330 }
1332 /* allocate frame buffer */
1333 par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp;
1334 par->vram_size = PAGE_ALIGN(par->vram_size/8);
1335 par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1337 par->vram_virt = dma_alloc_coherent(NULL,
1338 par->vram_size,
1339 (resource_size_t *) &par->vram_phys,
1340 GFP_KERNEL | GFP_DMA);
1341 if (!par->vram_virt) {
1342 dev_err(&device->dev,
1343 "GLCD: kmalloc for frame buffer failed\n");
1344 ret = -EINVAL;
1345 goto err_release_fb;
1346 }
1348 da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1349 da8xx_fb_fix.smem_start = par->vram_phys;
1350 da8xx_fb_fix.smem_len = par->vram_size;
1351 da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8;
1353 par->dma_start = par->vram_phys;
1354 par->dma_end = par->dma_start + lcdc_info->height *
1355 da8xx_fb_fix.line_length - 1;
1357 /* allocate palette buffer */
1358 par->v_palette_base = dma_alloc_coherent(NULL,
1359 PALETTE_SIZE,
1360 (resource_size_t *)
1361 &par->p_palette_base,
1362 GFP_KERNEL | GFP_DMA);
1363 if (!par->v_palette_base) {
1364 dev_err(&device->dev,
1365 "GLCD: kmalloc for palette buffer failed\n");
1366 ret = -EINVAL;
1367 goto err_release_fb_mem;
1368 }
1369 memset(par->v_palette_base, 0, PALETTE_SIZE);
1371 par->irq = platform_get_irq(device, 0);
1372 if (par->irq < 0) {
1373 ret = -ENOENT;
1374 goto err_release_pl_mem;
1375 }
1377 /* Initialize par */
1378 da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
1380 da8xx_fb_var.xres = lcdc_info->width;
1381 da8xx_fb_var.xres_virtual = lcdc_info->width;
1383 da8xx_fb_var.yres = lcdc_info->height;
1384 da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS;
1386 da8xx_fb_var.grayscale =
1387 lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
1388 da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1390 da8xx_fb_var.hsync_len = lcdc_info->hsw;
1391 da8xx_fb_var.vsync_len = lcdc_info->vsw;
1393 da8xx_fb_var.right_margin = lcdc_info->hfp;
1394 da8xx_fb_var.left_margin = lcdc_info->hbp;
1395 da8xx_fb_var.lower_margin = lcdc_info->vfp;
1396 da8xx_fb_var.upper_margin = lcdc_info->vbp;
1398 /* Initialize fbinfo */
1399 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1400 da8xx_fb_info->fix = da8xx_fb_fix;
1401 da8xx_fb_info->var = da8xx_fb_var;
1402 da8xx_fb_info->fbops = &da8xx_fb_ops;
1403 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1404 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1405 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1407 ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1408 if (ret)
1409 goto err_release_pl_mem;
1410 da8xx_fb_info->cmap.len = par->palette_sz;
1412 /* initialize var_screeninfo */
1413 da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1414 fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1416 dev_set_drvdata(&device->dev, da8xx_fb_info);
1418 /* initialize the vsync wait queue */
1419 init_waitqueue_head(&par->vsync_wait);
1420 par->vsync_timeout = HZ / 5;
1421 par->which_dma_channel_done = -1;
1422 spin_lock_init(&par->lock_for_chan_update);
1424 /* Register the Frame Buffer */
1425 if (register_framebuffer(da8xx_fb_info) < 0) {
1426 dev_err(&device->dev,
1427 "GLCD: Frame Buffer Registration Failed!\n");
1428 ret = -EINVAL;
1429 goto err_dealloc_cmap;
1430 }
1432 #ifdef CONFIG_CPU_FREQ
1433 ret = lcd_da8xx_cpufreq_register(par);
1434 if (ret) {
1435 dev_err(&device->dev, "failed to register cpufreq\n");
1436 goto err_cpu_freq;
1437 }
1438 #endif
1440 if (lcd_revision == LCD_VERSION_1)
1441 lcdc_irq_handler = lcdc_irq_handler_rev01;
1442 else
1443 lcdc_irq_handler = lcdc_irq_handler_rev02;
1445 ret = request_irq(par->irq, lcdc_irq_handler, 0,
1446 DRIVER_NAME, par);
1447 if (ret)
1448 goto irq_freq;
1449 return 0;
1451 irq_freq:
1452 #ifdef CONFIG_CPU_FREQ
1453 lcd_da8xx_cpufreq_deregister(par);
1454 err_cpu_freq:
1455 #endif
1456 unregister_framebuffer(da8xx_fb_info);
1458 err_dealloc_cmap:
1459 fb_dealloc_cmap(&da8xx_fb_info->cmap);
1461 err_release_pl_mem:
1462 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1463 par->p_palette_base);
1465 err_release_fb_mem:
1466 dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1468 err_release_fb:
1469 framebuffer_release(da8xx_fb_info);
1471 err_pm_runtime_disable:
1472 pm_runtime_put_sync(&device->dev);
1473 pm_runtime_disable(&device->dev);
1475 err_ioremap:
1477 iounmap((void __iomem *)da8xx_fb_reg_base);
1479 err_request_mem:
1480 release_mem_region(lcdc_regs->start, len);
1482 return ret;
1483 }
1485 #ifdef CONFIG_PM
1487 struct lcdc_context {
1488 u32 clk_enable;
1489 u32 ctrl;
1490 u32 dma_ctrl;
1491 u32 raster_timing_0;
1492 u32 raster_timing_1;
1493 u32 raster_timing_2;
1494 u32 int_enable_set;
1495 u32 dma_frm_buf_base_addr_0;
1496 u32 dma_frm_buf_ceiling_addr_0;
1497 u32 dma_frm_buf_base_addr_1;
1498 u32 dma_frm_buf_ceiling_addr_1;
1499 u32 raster_ctrl;
1500 } reg_context;
1502 static void lcd_context_save(void)
1503 {
1504 reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG);
1505 reg_context.ctrl = lcdc_read(LCD_CTRL_REG);
1506 reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG);
1507 reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG);
1508 reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG);
1509 reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG);
1510 reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG);
1511 reg_context.dma_frm_buf_base_addr_0 =
1512 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1513 reg_context.dma_frm_buf_ceiling_addr_0 =
1514 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1515 reg_context.dma_frm_buf_base_addr_1 =
1516 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1517 reg_context.dma_frm_buf_ceiling_addr_1 =
1518 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1519 reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG);
1520 return;
1521 }
1523 static void lcd_context_restore(void)
1524 {
1525 lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG);
1526 lcdc_write(reg_context.ctrl, LCD_CTRL_REG);
1527 lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG);
1528 lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG);
1529 lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG);
1530 lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG);
1531 lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG);
1532 lcdc_write(reg_context.dma_frm_buf_base_addr_0,
1533 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1534 lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0,
1535 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1536 lcdc_write(reg_context.dma_frm_buf_base_addr_1,
1537 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1538 lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1,
1539 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1540 lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG);
1541 return;
1542 }
1544 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1545 {
1546 struct fb_info *info = platform_get_drvdata(dev);
1547 struct da8xx_fb_par *par = info->par;
1549 console_lock();
1550 if (par->panel_power_ctrl)
1551 par->panel_power_ctrl(0);
1553 fb_set_suspend(info, 1);
1554 lcd_disable_raster(WAIT_FOR_FRAME_DONE);
1555 lcd_context_save();
1557 pm_runtime_put_sync(&dev->dev);
1558 console_unlock();
1560 return 0;
1561 }
1562 static int fb_resume(struct platform_device *dev)
1563 {
1564 struct fb_info *info = platform_get_drvdata(dev);
1565 struct da8xx_fb_par *par = info->par;
1567 console_lock();
1568 if (par->panel_power_ctrl)
1569 par->panel_power_ctrl(1);
1571 pm_runtime_get_sync(&dev->dev);
1573 lcd_context_restore();
1574 lcd_enable_raster();
1576 if (par->panel_power_ctrl)
1577 par->panel_power_ctrl(1);
1579 fb_set_suspend(info, 0);
1580 console_unlock();
1582 return 0;
1583 }
1584 #else
1585 #define fb_suspend NULL
1586 #define fb_resume NULL
1587 #endif
1589 static struct platform_driver da8xx_fb_driver = {
1590 .probe = fb_probe,
1591 .remove = __devexit_p(fb_remove),
1592 .suspend = fb_suspend,
1593 .resume = fb_resume,
1594 .driver = {
1595 .name = DRIVER_NAME,
1596 .owner = THIS_MODULE,
1597 },
1598 };
1600 static int __init da8xx_fb_init(void)
1601 {
1602 return platform_driver_register(&da8xx_fb_driver);
1603 }
1605 static void __exit da8xx_fb_cleanup(void)
1606 {
1607 platform_driver_unregister(&da8xx_fb_driver);
1608 }
1610 module_init(da8xx_fb_init);
1611 module_exit(da8xx_fb_cleanup);
1613 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1614 MODULE_AUTHOR("Texas Instruments");
1615 MODULE_LICENSE("GPL");