regulator: TPS65910: Create an array for reg init data
[sitara-epos/sitara-epos-kernel.git] / include / linux / mfd / tps65910.h
1 /*
2  * tps65910.h  --  TI TPS6591x
3  *
4  * Copyright 2010-2011 Texas Instruments Inc.
5  *
6  * Author: Graeme Gregory <gg@slimlogic.co.uk>
7  * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8  * Author: Arnaud Deconinck <a-deconinck@ti.com>
9  *
10  *  This program is free software; you can redistribute it and/or modify it
11  *  under  the terms of the GNU General  Public License as published by the
12  *  Free Software Foundation;  either version 2 of the License, or (at your
13  *  option) any later version.
14  *
15  */
17 #ifndef __LINUX_MFD_TPS65910_H
18 #define __LINUX_MFD_TPS65910_H
20 #include <linux/gpio.h>
21 #include <linux/regulator/machine.h>
23 /* TPS chip id list */
24 #define TPS65910                        0
25 #define TPS65911                        1
27 /* I2C Slave Address 7-bit */
28 #define TPS65910_I2C_ID0 0x12 /* Smart Reflex */
29 #define TPS65910_I2C_ID1 0x2D /* general-purpose control */
31 /* TPS regulator type list */
32 #define REGULATOR_LDO                   0
33 #define REGULATOR_DCDC                  1
35 /*
36  * List of registers for component TPS65910
37  *
38  */
40 #define TPS65910_SECONDS                                0x0
41 #define TPS65910_MINUTES                                0x1
42 #define TPS65910_HOURS                                  0x2
43 #define TPS65910_DAYS                                   0x3
44 #define TPS65910_MONTHS                                 0x4
45 #define TPS65910_YEARS                                  0x5
46 #define TPS65910_WEEKS                                  0x6
47 #define TPS65910_ALARM_SECONDS                          0x8
48 #define TPS65910_ALARM_MINUTES                          0x9
49 #define TPS65910_ALARM_HOURS                            0xA
50 #define TPS65910_ALARM_DAYS                             0xB
51 #define TPS65910_ALARM_MONTHS                           0xC
52 #define TPS65910_ALARM_YEARS                            0xD
53 #define TPS65910_RTC_CTRL                               0x10
54 #define TPS65910_RTC_STATUS                             0x11
55 #define TPS65910_RTC_INTERRUPTS                         0x12
56 #define TPS65910_RTC_COMP_LSB                           0x13
57 #define TPS65910_RTC_COMP_MSB                           0x14
58 #define TPS65910_RTC_RES_PROG                           0x15
59 #define TPS65910_RTC_RESET_STATUS                       0x16
60 #define TPS65910_BCK1                                   0x17
61 #define TPS65910_BCK2                                   0x18
62 #define TPS65910_BCK3                                   0x19
63 #define TPS65910_BCK4                                   0x1A
64 #define TPS65910_BCK5                                   0x1B
65 #define TPS65910_PUADEN                                 0x1C
66 #define TPS65910_REF                                    0x1D
67 #define TPS65910_VRTC                                   0x1E
68 #define TPS65910_VIO                                    0x20
69 #define TPS65910_VDD1                                   0x21
70 #define TPS65910_VDD1_OP                                0x22
71 #define TPS65910_VDD1_SR                                0x23
72 #define TPS65910_VDD2                                   0x24
73 #define TPS65910_VDD2_OP                                0x25
74 #define TPS65910_VDD2_SR                                0x26
75 #define TPS65910_VDD3                                   0x27
76 #define TPS65910_VDIG1                                  0x30
77 #define TPS65910_VDIG2                                  0x31
78 #define TPS65910_VAUX1                                  0x32
79 #define TPS65910_VAUX2                                  0x33
80 #define TPS65910_VAUX33                                 0x34
81 #define TPS65910_VMMC                                   0x35
82 #define TPS65910_VPLL                                   0x36
83 #define TPS65910_VDAC                                   0x37
84 #define TPS65910_THERM                                  0x38
85 #define TPS65910_BBCH                                   0x39
86 #define TPS65910_DCDCCTRL                               0x3E
87 #define TPS65910_DEVCTRL                                0x3F
88 #define TPS65910_DEVCTRL2                               0x40
89 #define TPS65910_SLEEP_KEEP_LDO_ON                      0x41
90 #define TPS65910_SLEEP_KEEP_RES_ON                      0x42
91 #define TPS65910_SLEEP_SET_LDO_OFF                      0x43
92 #define TPS65910_SLEEP_SET_RES_OFF                      0x44
93 #define TPS65910_EN1_LDO_ASS                            0x45
94 #define TPS65910_EN1_SMPS_ASS                           0x46
95 #define TPS65910_EN2_LDO_ASS                            0x47
96 #define TPS65910_EN2_SMPS_ASS                           0x48
97 #define TPS65910_EN3_LDO_ASS                            0x49
98 #define TPS65910_SPARE                                  0x4A
99 #define TPS65910_INT_STS                                0x50
100 #define TPS65910_INT_MSK                                0x51
101 #define TPS65910_INT_STS2                               0x52
102 #define TPS65910_INT_MSK2                               0x53
103 #define TPS65910_INT_STS3                               0x54
104 #define TPS65910_INT_MSK3                               0x55
105 #define TPS65910_GPIO0                                  0x60
106 #define TPS65910_GPIO1                                  0x61
107 #define TPS65910_GPIO2                                  0x62
108 #define TPS65910_GPIO3                                  0x63
109 #define TPS65910_GPIO4                                  0x64
110 #define TPS65910_GPIO5                                  0x65
111 #define TPS65910_GPIO6                                  0x66
112 #define TPS65910_GPIO7                                  0x67
113 #define TPS65910_GPIO8                                  0x68
114 #define TPS65910_JTAGVERNUM                             0x80
115 #define TPS65910_MAX_REGISTER                           0x80
117 /*
118  * List of registers specific to TPS65911
119  */
120 #define TPS65911_VDDCTRL                                0x27
121 #define TPS65911_VDDCTRL_OP                             0x28
122 #define TPS65911_VDDCTRL_SR                             0x29
123 #define TPS65911_LDO1                                   0x30
124 #define TPS65911_LDO2                                   0x31
125 #define TPS65911_LDO5                                   0x32
126 #define TPS65911_LDO8                                   0x33
127 #define TPS65911_LDO7                                   0x34
128 #define TPS65911_LDO6                                   0x35
129 #define TPS65911_LDO4                                   0x36
130 #define TPS65911_LDO3                                   0x37
131 #define TPS65911_VMBCH                                  0x6A
132 #define TPS65911_VMBCH2                                 0x6B
134 /*
135  * List of register bitfields for component TPS65910
136  *
137  */
140 /*Register BCK1  (0x80) register.RegisterDescription */
141 #define BCK1_BCKUP_MASK                                 0xFF
142 #define BCK1_BCKUP_SHIFT                                0
145 /*Register BCK2  (0x80) register.RegisterDescription */
146 #define BCK2_BCKUP_MASK                                 0xFF
147 #define BCK2_BCKUP_SHIFT                                0
150 /*Register BCK3  (0x80) register.RegisterDescription */
151 #define BCK3_BCKUP_MASK                                 0xFF
152 #define BCK3_BCKUP_SHIFT                                0
155 /*Register BCK4  (0x80) register.RegisterDescription */
156 #define BCK4_BCKUP_MASK                                 0xFF
157 #define BCK4_BCKUP_SHIFT                                0
160 /*Register BCK5  (0x80) register.RegisterDescription */
161 #define BCK5_BCKUP_MASK                                 0xFF
162 #define BCK5_BCKUP_SHIFT                                0
165 /*Register PUADEN  (0x80) register.RegisterDescription */
166 #define PUADEN_EN3P_MASK                                0x80
167 #define PUADEN_EN3P_SHIFT                               7
168 #define PUADEN_I2CCTLP_MASK                             0x40
169 #define PUADEN_I2CCTLP_SHIFT                            6
170 #define PUADEN_I2CSRP_MASK                              0x20
171 #define PUADEN_I2CSRP_SHIFT                             5
172 #define PUADEN_PWRONP_MASK                              0x10
173 #define PUADEN_PWRONP_SHIFT                             4
174 #define PUADEN_SLEEPP_MASK                              0x08
175 #define PUADEN_SLEEPP_SHIFT                             3
176 #define PUADEN_PWRHOLDP_MASK                            0x04
177 #define PUADEN_PWRHOLDP_SHIFT                           2
178 #define PUADEN_BOOT1P_MASK                              0x02
179 #define PUADEN_BOOT1P_SHIFT                             1
180 #define PUADEN_BOOT0P_MASK                              0x01
181 #define PUADEN_BOOT0P_SHIFT                             0
184 /*Register REF  (0x80) register.RegisterDescription */
185 #define REF_VMBCH_SEL_MASK                              0x0C
186 #define REF_VMBCH_SEL_SHIFT                             2
187 #define REF_ST_MASK                                     0x03
188 #define REF_ST_SHIFT                                    0
191 /*Register VRTC  (0x80) register.RegisterDescription */
192 #define VRTC_VRTC_OFFMASK_MASK                          0x08
193 #define VRTC_VRTC_OFFMASK_SHIFT                         3
194 #define VRTC_ST_MASK                                    0x03
195 #define VRTC_ST_SHIFT                                   0
198 /*Register VIO  (0x80) register.RegisterDescription */
199 #define VIO_ILMAX_MASK                                  0xC0
200 #define VIO_ILMAX_SHIFT                                 6
201 #define VIO_SEL_MASK                                    0x0C
202 #define VIO_SEL_SHIFT                                   2
203 #define VIO_ST_MASK                                     0x03
204 #define VIO_ST_SHIFT                                    0
207 /*Register VDD1  (0x80) register.RegisterDescription */
208 #define VDD1_VGAIN_SEL_MASK                             0xC0
209 #define VDD1_VGAIN_SEL_SHIFT                            6
210 #define VDD1_ILMAX_MASK                                 0x20
211 #define VDD1_ILMAX_SHIFT                                5
212 #define VDD1_TSTEP_MASK                                 0x1C
213 #define VDD1_TSTEP_SHIFT                                2
214 #define VDD1_ST_MASK                                    0x03
215 #define VDD1_ST_SHIFT                                   0
218 /*Register VDD1_OP  (0x80) register.RegisterDescription */
219 #define VDD1_OP_CMD_MASK                                0x80
220 #define VDD1_OP_CMD_SHIFT                               7
221 #define VDD1_OP_SEL_MASK                                0x7F
222 #define VDD1_OP_SEL_SHIFT                               0
225 /*Register VDD1_SR  (0x80) register.RegisterDescription */
226 #define VDD1_SR_SEL_MASK                                0x7F
227 #define VDD1_SR_SEL_SHIFT                               0
230 /*Register VDD2  (0x80) register.RegisterDescription */
231 #define VDD2_VGAIN_SEL_MASK                             0xC0
232 #define VDD2_VGAIN_SEL_SHIFT                            6
233 #define VDD2_ILMAX_MASK                                 0x20
234 #define VDD2_ILMAX_SHIFT                                5
235 #define VDD2_TSTEP_MASK                                 0x1C
236 #define VDD2_TSTEP_SHIFT                                2
237 #define VDD2_ST_MASK                                    0x03
238 #define VDD2_ST_SHIFT                                   0
241 /*Register VDD2_OP  (0x80) register.RegisterDescription */
242 #define VDD2_OP_CMD_MASK                                0x80
243 #define VDD2_OP_CMD_SHIFT                               7
244 #define VDD2_OP_SEL_MASK                                0x7F
245 #define VDD2_OP_SEL_SHIFT                               0
247 /*Register VDD2_SR  (0x80) register.RegisterDescription */
248 #define VDD2_SR_SEL_MASK                                0x7F
249 #define VDD2_SR_SEL_SHIFT                               0
252 /*Registers VDD1, VDD2 voltage values definitions */
253 #define VDD1_2_NUM_VOLT_FINE                            73
254 #define VDD1_2_NUM_VOLT_COARSE                          3
255 #define VDD1_2_MIN_VOLT                                 6000
256 #define VDD1_2_OFFSET                                   125
259 /*Register VDD3  (0x80) register.RegisterDescription */
260 #define VDD3_CKINEN_MASK                                0x04
261 #define VDD3_CKINEN_SHIFT                               2
262 #define VDD3_ST_MASK                                    0x03
263 #define VDD3_ST_SHIFT                                   0
264 #define VDDCTRL_MIN_VOLT                                6000
265 #define VDDCTRL_OFFSET                                  125
267 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */
268 #define LDO_SEL_MASK                                    0x0C
269 #define LDO_SEL_SHIFT                                   2
270 #define LDO_ST_MASK                                     0x03
271 #define LDO_ST_SHIFT                                    0
272 #define LDO_ST_ON_BIT                                   0x01
273 #define LDO_ST_MODE_BIT                                 0x02    
276 /* Registers LDO1 to LDO8 in tps65910 */
277 #define LDO1_SEL_MASK                                   0xFC
278 #define LDO3_SEL_MASK                                   0x7C
279 #define LDO_MIN_VOLT                                    1000
280 #define LDO_MAX_VOLT                                    3300
283 /*Register VDIG1  (0x80) register.RegisterDescription */
284 #define VDIG1_SEL_MASK                                  0x0C
285 #define VDIG1_SEL_SHIFT                                 2
286 #define VDIG1_ST_MASK                                   0x03
287 #define VDIG1_ST_SHIFT                                  0
290 /*Register VDIG2  (0x80) register.RegisterDescription */
291 #define VDIG2_SEL_MASK                                  0x0C
292 #define VDIG2_SEL_SHIFT                                 2
293 #define VDIG2_ST_MASK                                   0x03
294 #define VDIG2_ST_SHIFT                                  0
297 /*Register VAUX1  (0x80) register.RegisterDescription */
298 #define VAUX1_SEL_MASK                                  0x0C
299 #define VAUX1_SEL_SHIFT                                 2
300 #define VAUX1_ST_MASK                                   0x03
301 #define VAUX1_ST_SHIFT                                  0
304 /*Register VAUX2  (0x80) register.RegisterDescription */
305 #define VAUX2_SEL_MASK                                  0x0C
306 #define VAUX2_SEL_SHIFT                                 2
307 #define VAUX2_ST_MASK                                   0x03
308 #define VAUX2_ST_SHIFT                                  0
311 /*Register VAUX33  (0x80) register.RegisterDescription */
312 #define VAUX33_SEL_MASK                                 0x0C
313 #define VAUX33_SEL_SHIFT                                2
314 #define VAUX33_ST_MASK                                  0x03
315 #define VAUX33_ST_SHIFT                                 0
318 /*Register VMMC  (0x80) register.RegisterDescription */
319 #define VMMC_SEL_MASK                                   0x0C
320 #define VMMC_SEL_SHIFT                                  2
321 #define VMMC_ST_MASK                                    0x03
322 #define VMMC_ST_SHIFT                                   0
325 /*Register VPLL  (0x80) register.RegisterDescription */
326 #define VPLL_SEL_MASK                                   0x0C
327 #define VPLL_SEL_SHIFT                                  2
328 #define VPLL_ST_MASK                                    0x03
329 #define VPLL_ST_SHIFT                                   0
332 /*Register VDAC  (0x80) register.RegisterDescription */
333 #define VDAC_SEL_MASK                                   0x0C
334 #define VDAC_SEL_SHIFT                                  2
335 #define VDAC_ST_MASK                                    0x03
336 #define VDAC_ST_SHIFT                                   0
339 /*Register THERM  (0x80) register.RegisterDescription */
340 #define THERM_THERM_HD_MASK                             0x20
341 #define THERM_THERM_HD_SHIFT                            5
342 #define THERM_THERM_TS_MASK                             0x10
343 #define THERM_THERM_TS_SHIFT                            4
344 #define THERM_THERM_HDSEL_MASK                          0x0C
345 #define THERM_THERM_HDSEL_SHIFT                         2
346 #define THERM_RSVD1_MASK                                0x02
347 #define THERM_RSVD1_SHIFT                               1
348 #define THERM_THERM_STATE_MASK                          0x01
349 #define THERM_THERM_STATE_SHIFT                         0
352 /*Register BBCH  (0x80) register.RegisterDescription */
353 #define BBCH_BBSEL_MASK                                 0x06
354 #define BBCH_BBSEL_SHIFT                                1
355 #define BBCH_BBCHEN_MASK                                0x01
356 #define BBCH_BBCHEN_SHIFT                               0
359 /*Register DCDCCTRL  (0x80) register.RegisterDescription */
360 #define DCDCCTRL_VDD2_PSKIP_MASK                        0x20
361 #define DCDCCTRL_VDD2_PSKIP_SHIFT                       5
362 #define DCDCCTRL_VDD1_PSKIP_MASK                        0x10
363 #define DCDCCTRL_VDD1_PSKIP_SHIFT                       4
364 #define DCDCCTRL_VIO_PSKIP_MASK                         0x08
365 #define DCDCCTRL_VIO_PSKIP_SHIFT                        3
366 #define DCDCCTRL_DCDCCKEXT_MASK                         0x04
367 #define DCDCCTRL_DCDCCKEXT_SHIFT                        2
368 #define DCDCCTRL_DCDCCKSYNC_MASK                        0x03
369 #define DCDCCTRL_DCDCCKSYNC_SHIFT                       0
372 /*Register DEVCTRL  (0x80) register.RegisterDescription */
373 #define DEVCTRL_RTC_PWDN_MASK                           0x40
374 #define DEVCTRL_RTC_PWDN_SHIFT                          6
375 #define DEVCTRL_CK32K_CTRL_MASK                         0x20
376 #define DEVCTRL_CK32K_CTRL_SHIFT                        5
377 #define DEVCTRL_SR_CTL_I2C_SEL_MASK                     0x10
378 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT                    4
379 #define DEVCTRL_DEV_OFF_RST_MASK                        0x08
380 #define DEVCTRL_DEV_OFF_RST_SHIFT                       3
381 #define DEVCTRL_DEV_ON_MASK                             0x04
382 #define DEVCTRL_DEV_ON_SHIFT                            2
383 #define DEVCTRL_DEV_SLP_MASK                            0x02
384 #define DEVCTRL_DEV_SLP_SHIFT                           1
385 #define DEVCTRL_DEV_OFF_MASK                            0x01
386 #define DEVCTRL_DEV_OFF_SHIFT                           0
389 /*Register DEVCTRL2  (0x80) register.RegisterDescription */
390 #define DEVCTRL2_TSLOT_LENGTH_MASK                      0x30
391 #define DEVCTRL2_TSLOT_LENGTH_SHIFT                     4
392 #define DEVCTRL2_SLEEPSIG_POL_MASK                      0x08
393 #define DEVCTRL2_SLEEPSIG_POL_SHIFT                     3
394 #define DEVCTRL2_PWON_LP_OFF_MASK                       0x04
395 #define DEVCTRL2_PWON_LP_OFF_SHIFT                      2
396 #define DEVCTRL2_PWON_LP_RST_MASK                       0x02
397 #define DEVCTRL2_PWON_LP_RST_SHIFT                      1
398 #define DEVCTRL2_IT_POL_MASK                            0x01
399 #define DEVCTRL2_IT_POL_SHIFT                           0
402 /*Register SLEEP_KEEP_LDO_ON  (0x80) register.RegisterDescription */
403 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK              0x80
404 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT             7
405 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK              0x40
406 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT             6
407 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK            0x20
408 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT           5
409 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK             0x10
410 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT            4
411 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK             0x08
412 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT            3
413 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK             0x04
414 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT            2
415 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK             0x02
416 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT            1
417 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK              0x01
418 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT             0
421 /*Register SLEEP_KEEP_RES_ON  (0x80) register.RegisterDescription */
422 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK             0x80
423 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT            7
424 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK         0x40
425 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT        6
426 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK              0x20
427 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT             5
428 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK             0x10
429 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT            4
430 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK              0x08
431 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT             3
432 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK              0x04
433 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT             2
434 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK              0x02
435 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT             1
436 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK               0x01
437 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT              0
440 /*Register SLEEP_SET_LDO_OFF  (0x80) register.RegisterDescription */
441 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK              0x80
442 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT             7
443 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK              0x40
444 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT             6
445 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK            0x20
446 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT           5
447 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK             0x10
448 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT            4
449 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK             0x08
450 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT            3
451 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK             0x04
452 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT            2
453 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK             0x02
454 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT            1
455 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK              0x01
456 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT             0
459 /*Register SLEEP_SET_RES_OFF  (0x80) register.RegisterDescription */
460 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK             0x80
461 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT            7
462 #define SLEEP_SET_RES_OFF_RSVD_MASK                     0x60
463 #define SLEEP_SET_RES_OFF_RSVD_SHIFT                    5
464 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK             0x10
465 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT            4
466 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK              0x08
467 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT             3
468 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK              0x04
469 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT             2
470 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK              0x02
471 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT             1
472 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK               0x01
473 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT              0
476 /*Register EN1_LDO_ASS  (0x80) register.RegisterDescription */
477 #define EN1_LDO_ASS_VDAC_EN1_MASK                       0x80
478 #define EN1_LDO_ASS_VDAC_EN1_SHIFT                      7
479 #define EN1_LDO_ASS_VPLL_EN1_MASK                       0x40
480 #define EN1_LDO_ASS_VPLL_EN1_SHIFT                      6
481 #define EN1_LDO_ASS_VAUX33_EN1_MASK                     0x20
482 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT                    5
483 #define EN1_LDO_ASS_VAUX2_EN1_MASK                      0x10
484 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT                     4
485 #define EN1_LDO_ASS_VAUX1_EN1_MASK                      0x08
486 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT                     3
487 #define EN1_LDO_ASS_VDIG2_EN1_MASK                      0x04
488 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT                     2
489 #define EN1_LDO_ASS_VDIG1_EN1_MASK                      0x02
490 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT                     1
491 #define EN1_LDO_ASS_VMMC_EN1_MASK                       0x01
492 #define EN1_LDO_ASS_VMMC_EN1_SHIFT                      0
495 /*Register EN1_SMPS_ASS  (0x80) register.RegisterDescription */
496 #define EN1_SMPS_ASS_RSVD_MASK                          0xE0
497 #define EN1_SMPS_ASS_RSVD_SHIFT                         5
498 #define EN1_SMPS_ASS_SPARE_EN1_MASK                     0x10
499 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT                    4
500 #define EN1_SMPS_ASS_VDD3_EN1_MASK                      0x08
501 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT                     3
502 #define EN1_SMPS_ASS_VDD2_EN1_MASK                      0x04
503 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT                     2
504 #define EN1_SMPS_ASS_VDD1_EN1_MASK                      0x02
505 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT                     1
506 #define EN1_SMPS_ASS_VIO_EN1_MASK                       0x01
507 #define EN1_SMPS_ASS_VIO_EN1_SHIFT                      0
510 /*Register EN2_LDO_ASS  (0x80) register.RegisterDescription */
511 #define EN2_LDO_ASS_VDAC_EN2_MASK                       0x80
512 #define EN2_LDO_ASS_VDAC_EN2_SHIFT                      7
513 #define EN2_LDO_ASS_VPLL_EN2_MASK                       0x40
514 #define EN2_LDO_ASS_VPLL_EN2_SHIFT                      6
515 #define EN2_LDO_ASS_VAUX33_EN2_MASK                     0x20
516 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT                    5
517 #define EN2_LDO_ASS_VAUX2_EN2_MASK                      0x10
518 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT                     4
519 #define EN2_LDO_ASS_VAUX1_EN2_MASK                      0x08
520 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT                     3
521 #define EN2_LDO_ASS_VDIG2_EN2_MASK                      0x04
522 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT                     2
523 #define EN2_LDO_ASS_VDIG1_EN2_MASK                      0x02
524 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT                     1
525 #define EN2_LDO_ASS_VMMC_EN2_MASK                       0x01
526 #define EN2_LDO_ASS_VMMC_EN2_SHIFT                      0
529 /*Register EN2_SMPS_ASS  (0x80) register.RegisterDescription */
530 #define EN2_SMPS_ASS_RSVD_MASK                          0xE0
531 #define EN2_SMPS_ASS_RSVD_SHIFT                         5
532 #define EN2_SMPS_ASS_SPARE_EN2_MASK                     0x10
533 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT                    4
534 #define EN2_SMPS_ASS_VDD3_EN2_MASK                      0x08
535 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT                     3
536 #define EN2_SMPS_ASS_VDD2_EN2_MASK                      0x04
537 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT                     2
538 #define EN2_SMPS_ASS_VDD1_EN2_MASK                      0x02
539 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT                     1
540 #define EN2_SMPS_ASS_VIO_EN2_MASK                       0x01
541 #define EN2_SMPS_ASS_VIO_EN2_SHIFT                      0
544 /*Register EN3_LDO_ASS  (0x80) register.RegisterDescription */
545 #define EN3_LDO_ASS_VDAC_EN3_MASK                       0x80
546 #define EN3_LDO_ASS_VDAC_EN3_SHIFT                      7
547 #define EN3_LDO_ASS_VPLL_EN3_MASK                       0x40
548 #define EN3_LDO_ASS_VPLL_EN3_SHIFT                      6
549 #define EN3_LDO_ASS_VAUX33_EN3_MASK                     0x20
550 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT                    5
551 #define EN3_LDO_ASS_VAUX2_EN3_MASK                      0x10
552 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT                     4
553 #define EN3_LDO_ASS_VAUX1_EN3_MASK                      0x08
554 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT                     3
555 #define EN3_LDO_ASS_VDIG2_EN3_MASK                      0x04
556 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT                     2
557 #define EN3_LDO_ASS_VDIG1_EN3_MASK                      0x02
558 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT                     1
559 #define EN3_LDO_ASS_VMMC_EN3_MASK                       0x01
560 #define EN3_LDO_ASS_VMMC_EN3_SHIFT                      0
563 /*Register SPARE  (0x80) register.RegisterDescription */
564 #define SPARE_SPARE_MASK                                0xFF
565 #define SPARE_SPARE_SHIFT                               0
568 /*Register INT_STS  (0x80) register.RegisterDescription */
569 #define INT_STS_RTC_PERIOD_IT_MASK                      0x80
570 #define INT_STS_RTC_PERIOD_IT_SHIFT                     7
571 #define INT_STS_RTC_ALARM_IT_MASK                       0x40
572 #define INT_STS_RTC_ALARM_IT_SHIFT                      6
573 #define INT_STS_HOTDIE_IT_MASK                          0x20
574 #define INT_STS_HOTDIE_IT_SHIFT                         5
575 #define INT_STS_PWRHOLD_IT_MASK                         0x10
576 #define INT_STS_PWRHOLD_IT_SHIFT                        4
577 #define INT_STS_PWRON_LP_IT_MASK                        0x08
578 #define INT_STS_PWRON_LP_IT_SHIFT                       3
579 #define INT_STS_PWRON_IT_MASK                           0x04
580 #define INT_STS_PWRON_IT_SHIFT                          2
581 #define INT_STS_VMBHI_IT_MASK                           0x02
582 #define INT_STS_VMBHI_IT_SHIFT                          1
583 #define INT_STS_VMBDCH_IT_MASK                          0x01
584 #define INT_STS_VMBDCH_IT_SHIFT                         0
587 /*Register INT_MSK  (0x80) register.RegisterDescription */
588 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK                  0x80
589 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT                 7
590 #define INT_MSK_RTC_ALARM_IT_MSK_MASK                   0x40
591 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT                  6
592 #define INT_MSK_HOTDIE_IT_MSK_MASK                      0x20
593 #define INT_MSK_HOTDIE_IT_MSK_SHIFT                     5
594 #define INT_MSK_PWRHOLD_IT_MSK_MASK                     0x10
595 #define INT_MSK_PWRHOLD_IT_MSK_SHIFT                    4
596 #define INT_MSK_PWRON_LP_IT_MSK_MASK                    0x08
597 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT                   3
598 #define INT_MSK_PWRON_IT_MSK_MASK                       0x04
599 #define INT_MSK_PWRON_IT_MSK_SHIFT                      2
600 #define INT_MSK_VMBHI_IT_MSK_MASK                       0x02
601 #define INT_MSK_VMBHI_IT_MSK_SHIFT                      1
602 #define INT_MSK_VMBDCH_IT_MSK_MASK                      0x01
603 #define INT_MSK_VMBDCH_IT_MSK_SHIFT                     0
606 /*Register INT_STS2  (0x80) register.RegisterDescription */
607 #define INT_STS2_GPIO3_F_IT_MASK                        0x80
608 #define INT_STS2_GPIO3_F_IT_SHIFT                       7
609 #define INT_STS2_GPIO3_R_IT_MASK                        0x40
610 #define INT_STS2_GPIO3_R_IT_SHIFT                       6
611 #define INT_STS2_GPIO2_F_IT_MASK                        0x20
612 #define INT_STS2_GPIO2_F_IT_SHIFT                       5
613 #define INT_STS2_GPIO2_R_IT_MASK                        0x10
614 #define INT_STS2_GPIO2_R_IT_SHIFT                       4
615 #define INT_STS2_GPIO1_F_IT_MASK                        0x08
616 #define INT_STS2_GPIO1_F_IT_SHIFT                       3
617 #define INT_STS2_GPIO1_R_IT_MASK                        0x04
618 #define INT_STS2_GPIO1_R_IT_SHIFT                       2
619 #define INT_STS2_GPIO0_F_IT_MASK                        0x02
620 #define INT_STS2_GPIO0_F_IT_SHIFT                       1
621 #define INT_STS2_GPIO0_R_IT_MASK                        0x01
622 #define INT_STS2_GPIO0_R_IT_SHIFT                       0
625 /*Register INT_MSK2  (0x80) register.RegisterDescription */
626 #define INT_MSK2_GPIO3_F_IT_MSK_MASK                    0x80
627 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT                   7
628 #define INT_MSK2_GPIO3_R_IT_MSK_MASK                    0x40
629 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT                   6
630 #define INT_MSK2_GPIO2_F_IT_MSK_MASK                    0x20
631 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT                   5
632 #define INT_MSK2_GPIO2_R_IT_MSK_MASK                    0x10
633 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT                   4
634 #define INT_MSK2_GPIO1_F_IT_MSK_MASK                    0x08
635 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT                   3
636 #define INT_MSK2_GPIO1_R_IT_MSK_MASK                    0x04
637 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT                   2
638 #define INT_MSK2_GPIO0_F_IT_MSK_MASK                    0x02
639 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT                   1
640 #define INT_MSK2_GPIO0_R_IT_MSK_MASK                    0x01
641 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT                   0
644 /*Register INT_STS3  (0x80) register.RegisterDescription */
645 #define INT_STS3_GPIO5_F_IT_MASK                        0x08
646 #define INT_STS3_GPIO5_F_IT_SHIFT                       3
647 #define INT_STS3_GPIO5_R_IT_MASK                        0x04
648 #define INT_STS3_GPIO5_R_IT_SHIFT                       2
649 #define INT_STS3_GPIO4_F_IT_MASK                        0x02
650 #define INT_STS3_GPIO4_F_IT_SHIFT                       1
651 #define INT_STS3_GPIO4_R_IT_MASK                        0x01
652 #define INT_STS3_GPIO4_R_IT_SHIFT                       0
655 /*Register INT_MSK3  (0x80) register.RegisterDescription */
656 #define INT_MSK3_GPIO5_F_IT_MSK_MASK                    0x08
657 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT                   3
658 #define INT_MSK3_GPIO5_R_IT_MSK_MASK                    0x04
659 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT                   2
660 #define INT_MSK3_GPIO4_F_IT_MSK_MASK                    0x02
661 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT                   1
662 #define INT_MSK3_GPIO4_R_IT_MSK_MASK                    0x01
663 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT                   0
666 /*Register GPIO  (0x80) register.RegisterDescription */
667 #define GPIO_DEB_MASK                           0x10
668 #define GPIO_DEB_SHIFT                          4
669 #define GPIO_PUEN_MASK                          0x08
670 #define GPIO_PUEN_SHIFT                         3
671 #define GPIO_CFG_MASK                           0x04
672 #define GPIO_CFG_SHIFT                          2
673 #define GPIO_STS_MASK                           0x02
674 #define GPIO_STS_SHIFT                          1
675 #define GPIO_SET_MASK                           0x01
676 #define GPIO_SET_SHIFT                          0
679 /*Register JTAGVERNUM  (0x80) register.RegisterDescription */
680 #define JTAGVERNUM_VERNUM_MASK                          0x0F
681 #define JTAGVERNUM_VERNUM_SHIFT                         0
684 /* Register VDDCTRL (0x27) bit definitions */
685 #define VDDCTRL_ST_MASK                                  0x03
686 #define VDDCTRL_ST_SHIFT                                 0
689 /*Register VDDCTRL_OP  (0x28) bit definitios */
690 #define VDDCTRL_OP_CMD_MASK                              0x80
691 #define VDDCTRL_OP_CMD_SHIFT                             7
692 #define VDDCTRL_OP_SEL_MASK                              0x7F
693 #define VDDCTRL_OP_SEL_SHIFT                             0
696 /*Register VDDCTRL_SR  (0x29) bit definitions */
697 #define VDDCTRL_SR_SEL_MASK                              0x7F
698 #define VDDCTRL_SR_SEL_SHIFT                             0
701 /* IRQ Definitions */
702 #define TPS65910_IRQ_VBAT_VMBDCH                        0
703 #define TPS65910_IRQ_VBAT_VMHI                          1
704 #define TPS65910_IRQ_PWRON                              2
705 #define TPS65910_IRQ_PWRON_LP                           3
706 #define TPS65910_IRQ_PWRHOLD                            4
707 #define TPS65910_IRQ_HOTDIE                             5
708 #define TPS65910_IRQ_RTC_ALARM                          6
709 #define TPS65910_IRQ_RTC_PERIOD                         7
710 #define TPS65910_IRQ_GPIO_R                             8
711 #define TPS65910_IRQ_GPIO_F                             9
712 #define TPS65910_NUM_IRQ                                10
714 #define TPS65911_IRQ_VBAT_VMBDCH                        0
715 #define TPS65911_IRQ_VBAT_VMBDCH2L                      1
716 #define TPS65911_IRQ_VBAT_VMBDCH2H                      2
717 #define TPS65911_IRQ_VBAT_VMHI                          3
718 #define TPS65911_IRQ_PWRON                              4
719 #define TPS65911_IRQ_PWRON_LP                           5
720 #define TPS65911_IRQ_PWRHOLD_F                          6
721 #define TPS65911_IRQ_PWRHOLD_R                          7
722 #define TPS65911_IRQ_HOTDIE                             8
723 #define TPS65911_IRQ_RTC_ALARM                          9
724 #define TPS65911_IRQ_RTC_PERIOD                         10
725 #define TPS65911_IRQ_GPIO0_R                            11
726 #define TPS65911_IRQ_GPIO0_F                            12
727 #define TPS65911_IRQ_GPIO1_R                            13
728 #define TPS65911_IRQ_GPIO1_F                            14
729 #define TPS65911_IRQ_GPIO2_R                            15
730 #define TPS65911_IRQ_GPIO2_F                            16
731 #define TPS65911_IRQ_GPIO3_R                            17
732 #define TPS65911_IRQ_GPIO3_F                            18
733 #define TPS65911_IRQ_GPIO4_R                            19
734 #define TPS65911_IRQ_GPIO4_F                            20
735 #define TPS65911_IRQ_GPIO5_R                            21
736 #define TPS65911_IRQ_GPIO5_F                            22
737 #define TPS65911_IRQ_WTCHDG                             23
738 #define TPS65911_IRQ_PWRDN                              24
740 #define TPS65911_NUM_IRQ                                25
743 /* GPIO Register Definitions */
744 #define TPS65910_GPIO_DEB                               BIT(2)
745 #define TPS65910_GPIO_PUEN                              BIT(3)
746 #define TPS65910_GPIO_CFG                               BIT(2)
747 #define TPS65910_GPIO_STS                               BIT(1)
748 #define TPS65910_GPIO_SET                               BIT(0)
750 /* Regulator Index Definitions */
751 #define TPS65910_REG_VRTC                               0
752 #define TPS65910_REG_VIO                                1
753 #define TPS65910_REG_VDD1                               2
754 #define TPS65910_REG_VDD2                               3
755 #define TPS65910_REG_VDD3                               4
756 #define TPS65910_REG_VDIG1                              5
757 #define TPS65910_REG_VDIG2                              6
758 #define TPS65910_REG_VPLL                               7
759 #define TPS65910_REG_VDAC                               8
760 #define TPS65910_REG_VAUX1                              9
761 #define TPS65910_REG_VAUX2                              10
762 #define TPS65910_REG_VAUX33                             11
763 #define TPS65910_REG_VMMC                               12
765 #define TPS65911_REG_VDDCTRL                            4
766 #define TPS65911_REG_LDO1                               5
767 #define TPS65911_REG_LDO2                               6
768 #define TPS65911_REG_LDO3                               7
769 #define TPS65911_REG_LDO4                               8
770 #define TPS65911_REG_LDO5                               9
771 #define TPS65911_REG_LDO6                               10
772 #define TPS65911_REG_LDO7                               11
773 #define TPS65911_REG_LDO8                               12
775 /* Max number of TPS65910/11 regulators */
776 #define TPS65910_NUM_REGS                               13
778 /**
779  * struct tps65910_board
780  * Board platform data may be used to initialize regulators.
781  */
783 struct tps65910_board {
784         int gpio_base;
785         int irq;
786         int irq_base;
787         int vmbch_threshold;
788         int vmbch2_threshold;
789         struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
790 };
792 /**
793  * struct tps65910 - tps65910 sub-driver chip access routines
794  */
796 struct tps65910 {
797         struct device *dev;
798         struct i2c_client *i2c_client;
799         struct mutex io_mutex;
800         unsigned int id;
801         int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
802         int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src);
804         /* Client devices */
805         struct tps65910_pmic *pmic;
806         struct tps65910_rtc *rtc;
807         struct tps65910_power *power;
809         /* GPIO Handling */
810         struct gpio_chip gpio;
812         /* IRQ Handling */
813         struct mutex irq_lock;
814         int chip_irq;
815         int irq_base;
816         int irq_num;
817         u32 irq_mask;
818 };
820 struct tps65910_platform_data {
821         int irq;
822         int irq_base;
823 };
825 int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
826 int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
827 void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
828 int tps65910_irq_init(struct tps65910 *tps65910, int irq,
829                 struct tps65910_platform_data *pdata);
830 int tps65910_irq_exit(struct tps65910 *tps65910);
832 static inline int tps65910_chip_id(struct tps65910 *tps65910)
834         return tps65910->id;
837 #endif /*  __LINUX_MFD_TPS65910_H */