1 /*
2 * tps65910.h -- TI TPS6591x
3 *
4 * Copyright 2010-2011 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8 * Author: Arnaud Deconinck <a-deconinck@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
17 #ifndef __LINUX_MFD_TPS65910_H
18 #define __LINUX_MFD_TPS65910_H
20 /* TPS chip id list */
21 #define TPS65910 0
22 #define TPS65911 1
24 /* TPS regulator type list */
25 #define REGULATOR_LDO 0
26 #define REGULATOR_DCDC 1
28 /*
29 * List of registers for component TPS65910
30 *
31 */
33 #define TPS65910_SECONDS 0x0
34 #define TPS65910_MINUTES 0x1
35 #define TPS65910_HOURS 0x2
36 #define TPS65910_DAYS 0x3
37 #define TPS65910_MONTHS 0x4
38 #define TPS65910_YEARS 0x5
39 #define TPS65910_WEEKS 0x6
40 #define TPS65910_ALARM_SECONDS 0x8
41 #define TPS65910_ALARM_MINUTES 0x9
42 #define TPS65910_ALARM_HOURS 0xA
43 #define TPS65910_ALARM_DAYS 0xB
44 #define TPS65910_ALARM_MONTHS 0xC
45 #define TPS65910_ALARM_YEARS 0xD
46 #define TPS65910_RTC_CTRL 0x10
47 #define TPS65910_RTC_STATUS 0x11
48 #define TPS65910_RTC_INTERRUPTS 0x12
49 #define TPS65910_RTC_COMP_LSB 0x13
50 #define TPS65910_RTC_COMP_MSB 0x14
51 #define TPS65910_RTC_RES_PROG 0x15
52 #define TPS65910_RTC_RESET_STATUS 0x16
53 #define TPS65910_BCK1 0x17
54 #define TPS65910_BCK2 0x18
55 #define TPS65910_BCK3 0x19
56 #define TPS65910_BCK4 0x1A
57 #define TPS65910_BCK5 0x1B
58 #define TPS65910_PUADEN 0x1C
59 #define TPS65910_REF 0x1D
60 #define TPS65910_VRTC 0x1E
61 #define TPS65910_VIO 0x20
62 #define TPS65910_VDD1 0x21
63 #define TPS65910_VDD1_OP 0x22
64 #define TPS65910_VDD1_SR 0x23
65 #define TPS65910_VDD2 0x24
66 #define TPS65910_VDD2_OP 0x25
67 #define TPS65910_VDD2_SR 0x26
68 #define TPS65910_VDD3 0x27
69 #define TPS65910_VDIG1 0x30
70 #define TPS65910_VDIG2 0x31
71 #define TPS65910_VAUX1 0x32
72 #define TPS65910_VAUX2 0x33
73 #define TPS65910_VAUX33 0x34
74 #define TPS65910_VMMC 0x35
75 #define TPS65910_VPLL 0x36
76 #define TPS65910_VDAC 0x37
77 #define TPS65910_THERM 0x38
78 #define TPS65910_BBCH 0x39
79 #define TPS65910_DCDCCTRL 0x3E
80 #define TPS65910_DEVCTRL 0x3F
81 #define TPS65910_DEVCTRL2 0x40
82 #define TPS65910_SLEEP_KEEP_LDO_ON 0x41
83 #define TPS65910_SLEEP_KEEP_RES_ON 0x42
84 #define TPS65910_SLEEP_SET_LDO_OFF 0x43
85 #define TPS65910_SLEEP_SET_RES_OFF 0x44
86 #define TPS65910_EN1_LDO_ASS 0x45
87 #define TPS65910_EN1_SMPS_ASS 0x46
88 #define TPS65910_EN2_LDO_ASS 0x47
89 #define TPS65910_EN2_SMPS_ASS 0x48
90 #define TPS65910_EN3_LDO_ASS 0x49
91 #define TPS65910_SPARE 0x4A
92 #define TPS65910_INT_STS 0x50
93 #define TPS65910_INT_MSK 0x51
94 #define TPS65910_INT_STS2 0x52
95 #define TPS65910_INT_MSK2 0x53
96 #define TPS65910_INT_STS3 0x54
97 #define TPS65910_INT_MSK3 0x55
98 #define TPS65910_GPIO0 0x60
99 #define TPS65910_GPIO1 0x61
100 #define TPS65910_GPIO2 0x62
101 #define TPS65910_GPIO3 0x63
102 #define TPS65910_GPIO4 0x64
103 #define TPS65910_GPIO5 0x65
104 #define TPS65910_GPIO6 0x66
105 #define TPS65910_GPIO7 0x67
106 #define TPS65910_GPIO8 0x68
107 #define TPS65910_JTAGVERNUM 0x80
108 #define TPS65910_MAX_REGISTER 0x80
110 /*
111 * List of registers specific to TPS65911
112 */
113 #define TPS65911_VDDCTRL 0x27
114 #define TPS65911_VDDCTRL_OP 0x28
115 #define TPS65911_VDDCTRL_SR 0x29
116 #define TPS65911_LDO1 0x30
117 #define TPS65911_LDO2 0x31
118 #define TPS65911_LDO5 0x32
119 #define TPS65911_LDO8 0x33
120 #define TPS65911_LDO7 0x34
121 #define TPS65911_LDO6 0x35
122 #define TPS65911_LDO4 0x36
123 #define TPS65911_LDO3 0x37
124 #define TPS65911_VMBCH 0x6A
125 #define TPS65911_VMBCH2 0x6B
127 /*
128 * List of register bitfields for component TPS65910
129 *
130 */
133 /*Register BCK1 (0x80) register.RegisterDescription */
134 #define BCK1_BCKUP_MASK 0xFF
135 #define BCK1_BCKUP_SHIFT 0
138 /*Register BCK2 (0x80) register.RegisterDescription */
139 #define BCK2_BCKUP_MASK 0xFF
140 #define BCK2_BCKUP_SHIFT 0
143 /*Register BCK3 (0x80) register.RegisterDescription */
144 #define BCK3_BCKUP_MASK 0xFF
145 #define BCK3_BCKUP_SHIFT 0
148 /*Register BCK4 (0x80) register.RegisterDescription */
149 #define BCK4_BCKUP_MASK 0xFF
150 #define BCK4_BCKUP_SHIFT 0
153 /*Register BCK5 (0x80) register.RegisterDescription */
154 #define BCK5_BCKUP_MASK 0xFF
155 #define BCK5_BCKUP_SHIFT 0
158 /*Register PUADEN (0x80) register.RegisterDescription */
159 #define PUADEN_EN3P_MASK 0x80
160 #define PUADEN_EN3P_SHIFT 7
161 #define PUADEN_I2CCTLP_MASK 0x40
162 #define PUADEN_I2CCTLP_SHIFT 6
163 #define PUADEN_I2CSRP_MASK 0x20
164 #define PUADEN_I2CSRP_SHIFT 5
165 #define PUADEN_PWRONP_MASK 0x10
166 #define PUADEN_PWRONP_SHIFT 4
167 #define PUADEN_SLEEPP_MASK 0x08
168 #define PUADEN_SLEEPP_SHIFT 3
169 #define PUADEN_PWRHOLDP_MASK 0x04
170 #define PUADEN_PWRHOLDP_SHIFT 2
171 #define PUADEN_BOOT1P_MASK 0x02
172 #define PUADEN_BOOT1P_SHIFT 1
173 #define PUADEN_BOOT0P_MASK 0x01
174 #define PUADEN_BOOT0P_SHIFT 0
177 /*Register REF (0x80) register.RegisterDescription */
178 #define REF_VMBCH_SEL_MASK 0x0C
179 #define REF_VMBCH_SEL_SHIFT 2
180 #define REF_ST_MASK 0x03
181 #define REF_ST_SHIFT 0
184 /*Register VRTC (0x80) register.RegisterDescription */
185 #define VRTC_VRTC_OFFMASK_MASK 0x08
186 #define VRTC_VRTC_OFFMASK_SHIFT 3
187 #define VRTC_ST_MASK 0x03
188 #define VRTC_ST_SHIFT 0
191 /*Register VIO (0x80) register.RegisterDescription */
192 #define VIO_ILMAX_MASK 0xC0
193 #define VIO_ILMAX_SHIFT 6
194 #define VIO_SEL_MASK 0x0C
195 #define VIO_SEL_SHIFT 2
196 #define VIO_ST_MASK 0x03
197 #define VIO_ST_SHIFT 0
200 /*Register VDD1 (0x80) register.RegisterDescription */
201 #define VDD1_VGAIN_SEL_MASK 0xC0
202 #define VDD1_VGAIN_SEL_SHIFT 6
203 #define VDD1_ILMAX_MASK 0x20
204 #define VDD1_ILMAX_SHIFT 5
205 #define VDD1_TSTEP_MASK 0x1C
206 #define VDD1_TSTEP_SHIFT 2
207 #define VDD1_ST_MASK 0x03
208 #define VDD1_ST_SHIFT 0
211 /*Register VDD1_OP (0x80) register.RegisterDescription */
212 #define VDD1_OP_CMD_MASK 0x80
213 #define VDD1_OP_CMD_SHIFT 7
214 #define VDD1_OP_SEL_MASK 0x7F
215 #define VDD1_OP_SEL_SHIFT 0
218 /*Register VDD1_SR (0x80) register.RegisterDescription */
219 #define VDD1_SR_SEL_MASK 0x7F
220 #define VDD1_SR_SEL_SHIFT 0
223 /*Register VDD2 (0x80) register.RegisterDescription */
224 #define VDD2_VGAIN_SEL_MASK 0xC0
225 #define VDD2_VGAIN_SEL_SHIFT 6
226 #define VDD2_ILMAX_MASK 0x20
227 #define VDD2_ILMAX_SHIFT 5
228 #define VDD2_TSTEP_MASK 0x1C
229 #define VDD2_TSTEP_SHIFT 2
230 #define VDD2_ST_MASK 0x03
231 #define VDD2_ST_SHIFT 0
234 /*Register VDD2_OP (0x80) register.RegisterDescription */
235 #define VDD2_OP_CMD_MASK 0x80
236 #define VDD2_OP_CMD_SHIFT 7
237 #define VDD2_OP_SEL_MASK 0x7F
238 #define VDD2_OP_SEL_SHIFT 0
240 /*Register VDD2_SR (0x80) register.RegisterDescription */
241 #define VDD2_SR_SEL_MASK 0x7F
242 #define VDD2_SR_SEL_SHIFT 0
245 /*Registers VDD1, VDD2 voltage values definitions */
246 #define VDD1_2_NUM_VOLT_FINE 73
247 #define VDD1_2_NUM_VOLT_COARSE 3
248 #define VDD1_2_MIN_VOLT 6000
249 #define VDD1_2_OFFSET 125
252 /*Register VDD3 (0x80) register.RegisterDescription */
253 #define VDD3_CKINEN_MASK 0x04
254 #define VDD3_CKINEN_SHIFT 2
255 #define VDD3_ST_MASK 0x03
256 #define VDD3_ST_SHIFT 0
257 #define VDDCTRL_MIN_VOLT 6000
258 #define VDDCTRL_OFFSET 125
260 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */
261 #define LDO_SEL_MASK 0x0C
262 #define LDO_SEL_SHIFT 2
263 #define LDO_ST_MASK 0x03
264 #define LDO_ST_SHIFT 0
265 #define LDO_ST_ON_BIT 0x01
266 #define LDO_ST_MODE_BIT 0x02
269 /* Registers LDO1 to LDO8 in tps65910 */
270 #define LDO1_SEL_MASK 0xFC
271 #define LDO3_SEL_MASK 0x7C
272 #define LDO_MIN_VOLT 1000
273 #define LDO_MAX_VOLT 3300
276 /*Register VDIG1 (0x80) register.RegisterDescription */
277 #define VDIG1_SEL_MASK 0x0C
278 #define VDIG1_SEL_SHIFT 2
279 #define VDIG1_ST_MASK 0x03
280 #define VDIG1_ST_SHIFT 0
283 /*Register VDIG2 (0x80) register.RegisterDescription */
284 #define VDIG2_SEL_MASK 0x0C
285 #define VDIG2_SEL_SHIFT 2
286 #define VDIG2_ST_MASK 0x03
287 #define VDIG2_ST_SHIFT 0
290 /*Register VAUX1 (0x80) register.RegisterDescription */
291 #define VAUX1_SEL_MASK 0x0C
292 #define VAUX1_SEL_SHIFT 2
293 #define VAUX1_ST_MASK 0x03
294 #define VAUX1_ST_SHIFT 0
297 /*Register VAUX2 (0x80) register.RegisterDescription */
298 #define VAUX2_SEL_MASK 0x0C
299 #define VAUX2_SEL_SHIFT 2
300 #define VAUX2_ST_MASK 0x03
301 #define VAUX2_ST_SHIFT 0
304 /*Register VAUX33 (0x80) register.RegisterDescription */
305 #define VAUX33_SEL_MASK 0x0C
306 #define VAUX33_SEL_SHIFT 2
307 #define VAUX33_ST_MASK 0x03
308 #define VAUX33_ST_SHIFT 0
311 /*Register VMMC (0x80) register.RegisterDescription */
312 #define VMMC_SEL_MASK 0x0C
313 #define VMMC_SEL_SHIFT 2
314 #define VMMC_ST_MASK 0x03
315 #define VMMC_ST_SHIFT 0
318 /*Register VPLL (0x80) register.RegisterDescription */
319 #define VPLL_SEL_MASK 0x0C
320 #define VPLL_SEL_SHIFT 2
321 #define VPLL_ST_MASK 0x03
322 #define VPLL_ST_SHIFT 0
325 /*Register VDAC (0x80) register.RegisterDescription */
326 #define VDAC_SEL_MASK 0x0C
327 #define VDAC_SEL_SHIFT 2
328 #define VDAC_ST_MASK 0x03
329 #define VDAC_ST_SHIFT 0
332 /*Register THERM (0x80) register.RegisterDescription */
333 #define THERM_THERM_HD_MASK 0x20
334 #define THERM_THERM_HD_SHIFT 5
335 #define THERM_THERM_TS_MASK 0x10
336 #define THERM_THERM_TS_SHIFT 4
337 #define THERM_THERM_HDSEL_MASK 0x0C
338 #define THERM_THERM_HDSEL_SHIFT 2
339 #define THERM_RSVD1_MASK 0x02
340 #define THERM_RSVD1_SHIFT 1
341 #define THERM_THERM_STATE_MASK 0x01
342 #define THERM_THERM_STATE_SHIFT 0
345 /*Register BBCH (0x80) register.RegisterDescription */
346 #define BBCH_BBSEL_MASK 0x06
347 #define BBCH_BBSEL_SHIFT 1
348 #define BBCH_BBCHEN_MASK 0x01
349 #define BBCH_BBCHEN_SHIFT 0
352 /*Register DCDCCTRL (0x80) register.RegisterDescription */
353 #define DCDCCTRL_VDD2_PSKIP_MASK 0x20
354 #define DCDCCTRL_VDD2_PSKIP_SHIFT 5
355 #define DCDCCTRL_VDD1_PSKIP_MASK 0x10
356 #define DCDCCTRL_VDD1_PSKIP_SHIFT 4
357 #define DCDCCTRL_VIO_PSKIP_MASK 0x08
358 #define DCDCCTRL_VIO_PSKIP_SHIFT 3
359 #define DCDCCTRL_DCDCCKEXT_MASK 0x04
360 #define DCDCCTRL_DCDCCKEXT_SHIFT 2
361 #define DCDCCTRL_DCDCCKSYNC_MASK 0x03
362 #define DCDCCTRL_DCDCCKSYNC_SHIFT 0
365 /*Register DEVCTRL (0x80) register.RegisterDescription */
366 #define DEVCTRL_RTC_PWDN_MASK 0x40
367 #define DEVCTRL_RTC_PWDN_SHIFT 6
368 #define DEVCTRL_CK32K_CTRL_MASK 0x20
369 #define DEVCTRL_CK32K_CTRL_SHIFT 5
370 #define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10
371 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4
372 #define DEVCTRL_DEV_OFF_RST_MASK 0x08
373 #define DEVCTRL_DEV_OFF_RST_SHIFT 3
374 #define DEVCTRL_DEV_ON_MASK 0x04
375 #define DEVCTRL_DEV_ON_SHIFT 2
376 #define DEVCTRL_DEV_SLP_MASK 0x02
377 #define DEVCTRL_DEV_SLP_SHIFT 1
378 #define DEVCTRL_DEV_OFF_MASK 0x01
379 #define DEVCTRL_DEV_OFF_SHIFT 0
382 /*Register DEVCTRL2 (0x80) register.RegisterDescription */
383 #define DEVCTRL2_TSLOT_LENGTH_MASK 0x30
384 #define DEVCTRL2_TSLOT_LENGTH_SHIFT 4
385 #define DEVCTRL2_SLEEPSIG_POL_MASK 0x08
386 #define DEVCTRL2_SLEEPSIG_POL_SHIFT 3
387 #define DEVCTRL2_PWON_LP_OFF_MASK 0x04
388 #define DEVCTRL2_PWON_LP_OFF_SHIFT 2
389 #define DEVCTRL2_PWON_LP_RST_MASK 0x02
390 #define DEVCTRL2_PWON_LP_RST_SHIFT 1
391 #define DEVCTRL2_IT_POL_MASK 0x01
392 #define DEVCTRL2_IT_POL_SHIFT 0
395 /*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */
396 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80
397 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7
398 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40
399 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6
400 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20
401 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5
402 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10
403 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4
404 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08
405 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3
406 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04
407 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2
408 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02
409 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1
410 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01
411 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0
414 /*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */
415 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80
416 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7
417 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40
418 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6
419 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20
420 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5
421 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10
422 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4
423 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08
424 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3
425 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04
426 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2
427 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02
428 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1
429 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01
430 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0
433 /*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */
434 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80
435 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7
436 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40
437 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6
438 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20
439 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5
440 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10
441 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4
442 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08
443 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3
444 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04
445 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2
446 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02
447 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1
448 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01
449 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0
452 /*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */
453 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80
454 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7
455 #define SLEEP_SET_RES_OFF_RSVD_MASK 0x60
456 #define SLEEP_SET_RES_OFF_RSVD_SHIFT 5
457 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10
458 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4
459 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08
460 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3
461 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04
462 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2
463 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02
464 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1
465 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01
466 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0
469 /*Register EN1_LDO_ASS (0x80) register.RegisterDescription */
470 #define EN1_LDO_ASS_VDAC_EN1_MASK 0x80
471 #define EN1_LDO_ASS_VDAC_EN1_SHIFT 7
472 #define EN1_LDO_ASS_VPLL_EN1_MASK 0x40
473 #define EN1_LDO_ASS_VPLL_EN1_SHIFT 6
474 #define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20
475 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5
476 #define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10
477 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4
478 #define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08
479 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3
480 #define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04
481 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2
482 #define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02
483 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1
484 #define EN1_LDO_ASS_VMMC_EN1_MASK 0x01
485 #define EN1_LDO_ASS_VMMC_EN1_SHIFT 0
488 /*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */
489 #define EN1_SMPS_ASS_RSVD_MASK 0xE0
490 #define EN1_SMPS_ASS_RSVD_SHIFT 5
491 #define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10
492 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4
493 #define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08
494 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3
495 #define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04
496 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2
497 #define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02
498 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1
499 #define EN1_SMPS_ASS_VIO_EN1_MASK 0x01
500 #define EN1_SMPS_ASS_VIO_EN1_SHIFT 0
503 /*Register EN2_LDO_ASS (0x80) register.RegisterDescription */
504 #define EN2_LDO_ASS_VDAC_EN2_MASK 0x80
505 #define EN2_LDO_ASS_VDAC_EN2_SHIFT 7
506 #define EN2_LDO_ASS_VPLL_EN2_MASK 0x40
507 #define EN2_LDO_ASS_VPLL_EN2_SHIFT 6
508 #define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20
509 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5
510 #define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10
511 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4
512 #define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08
513 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3
514 #define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04
515 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2
516 #define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02
517 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1
518 #define EN2_LDO_ASS_VMMC_EN2_MASK 0x01
519 #define EN2_LDO_ASS_VMMC_EN2_SHIFT 0
522 /*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */
523 #define EN2_SMPS_ASS_RSVD_MASK 0xE0
524 #define EN2_SMPS_ASS_RSVD_SHIFT 5
525 #define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10
526 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4
527 #define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08
528 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3
529 #define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04
530 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2
531 #define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02
532 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1
533 #define EN2_SMPS_ASS_VIO_EN2_MASK 0x01
534 #define EN2_SMPS_ASS_VIO_EN2_SHIFT 0
537 /*Register EN3_LDO_ASS (0x80) register.RegisterDescription */
538 #define EN3_LDO_ASS_VDAC_EN3_MASK 0x80
539 #define EN3_LDO_ASS_VDAC_EN3_SHIFT 7
540 #define EN3_LDO_ASS_VPLL_EN3_MASK 0x40
541 #define EN3_LDO_ASS_VPLL_EN3_SHIFT 6
542 #define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20
543 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5
544 #define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10
545 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4
546 #define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08
547 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3
548 #define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04
549 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2
550 #define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02
551 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1
552 #define EN3_LDO_ASS_VMMC_EN3_MASK 0x01
553 #define EN3_LDO_ASS_VMMC_EN3_SHIFT 0
556 /*Register SPARE (0x80) register.RegisterDescription */
557 #define SPARE_SPARE_MASK 0xFF
558 #define SPARE_SPARE_SHIFT 0
561 /*Register INT_STS (0x80) register.RegisterDescription */
562 #define INT_STS_RTC_PERIOD_IT_MASK 0x80
563 #define INT_STS_RTC_PERIOD_IT_SHIFT 7
564 #define INT_STS_RTC_ALARM_IT_MASK 0x40
565 #define INT_STS_RTC_ALARM_IT_SHIFT 6
566 #define INT_STS_HOTDIE_IT_MASK 0x20
567 #define INT_STS_HOTDIE_IT_SHIFT 5
568 #define INT_STS_PWRHOLD_IT_MASK 0x10
569 #define INT_STS_PWRHOLD_IT_SHIFT 4
570 #define INT_STS_PWRON_LP_IT_MASK 0x08
571 #define INT_STS_PWRON_LP_IT_SHIFT 3
572 #define INT_STS_PWRON_IT_MASK 0x04
573 #define INT_STS_PWRON_IT_SHIFT 2
574 #define INT_STS_VMBHI_IT_MASK 0x02
575 #define INT_STS_VMBHI_IT_SHIFT 1
576 #define INT_STS_VMBDCH_IT_MASK 0x01
577 #define INT_STS_VMBDCH_IT_SHIFT 0
580 /*Register INT_MSK (0x80) register.RegisterDescription */
581 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80
582 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7
583 #define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40
584 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6
585 #define INT_MSK_HOTDIE_IT_MSK_MASK 0x20
586 #define INT_MSK_HOTDIE_IT_MSK_SHIFT 5
587 #define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10
588 #define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4
589 #define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
590 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3
591 #define INT_MSK_PWRON_IT_MSK_MASK 0x04
592 #define INT_MSK_PWRON_IT_MSK_SHIFT 2
593 #define INT_MSK_VMBHI_IT_MSK_MASK 0x02
594 #define INT_MSK_VMBHI_IT_MSK_SHIFT 1
595 #define INT_MSK_VMBDCH_IT_MSK_MASK 0x01
596 #define INT_MSK_VMBDCH_IT_MSK_SHIFT 0
599 /*Register INT_STS2 (0x80) register.RegisterDescription */
600 #define INT_STS2_GPIO3_F_IT_MASK 0x80
601 #define INT_STS2_GPIO3_F_IT_SHIFT 7
602 #define INT_STS2_GPIO3_R_IT_MASK 0x40
603 #define INT_STS2_GPIO3_R_IT_SHIFT 6
604 #define INT_STS2_GPIO2_F_IT_MASK 0x20
605 #define INT_STS2_GPIO2_F_IT_SHIFT 5
606 #define INT_STS2_GPIO2_R_IT_MASK 0x10
607 #define INT_STS2_GPIO2_R_IT_SHIFT 4
608 #define INT_STS2_GPIO1_F_IT_MASK 0x08
609 #define INT_STS2_GPIO1_F_IT_SHIFT 3
610 #define INT_STS2_GPIO1_R_IT_MASK 0x04
611 #define INT_STS2_GPIO1_R_IT_SHIFT 2
612 #define INT_STS2_GPIO0_F_IT_MASK 0x02
613 #define INT_STS2_GPIO0_F_IT_SHIFT 1
614 #define INT_STS2_GPIO0_R_IT_MASK 0x01
615 #define INT_STS2_GPIO0_R_IT_SHIFT 0
618 /*Register INT_MSK2 (0x80) register.RegisterDescription */
619 #define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80
620 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7
621 #define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40
622 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6
623 #define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20
624 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5
625 #define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10
626 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4
627 #define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08
628 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3
629 #define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04
630 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2
631 #define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02
632 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1
633 #define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01
634 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0
637 /*Register INT_STS3 (0x80) register.RegisterDescription */
638 #define INT_STS3_GPIO5_F_IT_MASK 0x08
639 #define INT_STS3_GPIO5_F_IT_SHIFT 3
640 #define INT_STS3_GPIO5_R_IT_MASK 0x04
641 #define INT_STS3_GPIO5_R_IT_SHIFT 2
642 #define INT_STS3_GPIO4_F_IT_MASK 0x02
643 #define INT_STS3_GPIO4_F_IT_SHIFT 1
644 #define INT_STS3_GPIO4_R_IT_MASK 0x01
645 #define INT_STS3_GPIO4_R_IT_SHIFT 0
648 /*Register INT_MSK3 (0x80) register.RegisterDescription */
649 #define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08
650 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3
651 #define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04
652 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2
653 #define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02
654 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1
655 #define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01
656 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0
659 /*Register GPIO (0x80) register.RegisterDescription */
660 #define GPIO_DEB_MASK 0x10
661 #define GPIO_DEB_SHIFT 4
662 #define GPIO_PUEN_MASK 0x08
663 #define GPIO_PUEN_SHIFT 3
664 #define GPIO_CFG_MASK 0x04
665 #define GPIO_CFG_SHIFT 2
666 #define GPIO_STS_MASK 0x02
667 #define GPIO_STS_SHIFT 1
668 #define GPIO_SET_MASK 0x01
669 #define GPIO_SET_SHIFT 0
672 /*Register JTAGVERNUM (0x80) register.RegisterDescription */
673 #define JTAGVERNUM_VERNUM_MASK 0x0F
674 #define JTAGVERNUM_VERNUM_SHIFT 0
677 /* Register VDDCTRL (0x27) bit definitions */
678 #define VDDCTRL_ST_MASK 0x03
679 #define VDDCTRL_ST_SHIFT 0
682 /*Register VDDCTRL_OP (0x28) bit definitios */
683 #define VDDCTRL_OP_CMD_MASK 0x80
684 #define VDDCTRL_OP_CMD_SHIFT 7
685 #define VDDCTRL_OP_SEL_MASK 0x7F
686 #define VDDCTRL_OP_SEL_SHIFT 0
689 /*Register VDDCTRL_SR (0x29) bit definitions */
690 #define VDDCTRL_SR_SEL_MASK 0x7F
691 #define VDDCTRL_SR_SEL_SHIFT 0
694 /* IRQ Definitions */
695 #define TPS65910_IRQ_VBAT_VMBDCH 0
696 #define TPS65910_IRQ_VBAT_VMHI 1
697 #define TPS65910_IRQ_PWRON 2
698 #define TPS65910_IRQ_PWRON_LP 3
699 #define TPS65910_IRQ_PWRHOLD 4
700 #define TPS65910_IRQ_HOTDIE 5
701 #define TPS65910_IRQ_RTC_ALARM 6
702 #define TPS65910_IRQ_RTC_PERIOD 7
703 #define TPS65910_IRQ_GPIO_R 8
704 #define TPS65910_IRQ_GPIO_F 9
705 #define TPS65910_NUM_IRQ 10
707 #define TPS65911_IRQ_VBAT_VMBDCH 0
708 #define TPS65911_IRQ_VBAT_VMBDCH2L 1
709 #define TPS65911_IRQ_VBAT_VMBDCH2H 2
710 #define TPS65911_IRQ_VBAT_VMHI 3
711 #define TPS65911_IRQ_PWRON 4
712 #define TPS65911_IRQ_PWRON_LP 5
713 #define TPS65911_IRQ_PWRHOLD_F 6
714 #define TPS65911_IRQ_PWRHOLD_R 7
715 #define TPS65911_IRQ_HOTDIE 8
716 #define TPS65911_IRQ_RTC_ALARM 9
717 #define TPS65911_IRQ_RTC_PERIOD 10
718 #define TPS65911_IRQ_GPIO0_R 11
719 #define TPS65911_IRQ_GPIO0_F 12
720 #define TPS65911_IRQ_GPIO1_R 13
721 #define TPS65911_IRQ_GPIO1_F 14
722 #define TPS65911_IRQ_GPIO2_R 15
723 #define TPS65911_IRQ_GPIO2_F 16
724 #define TPS65911_IRQ_GPIO3_R 17
725 #define TPS65911_IRQ_GPIO3_F 18
726 #define TPS65911_IRQ_GPIO4_R 19
727 #define TPS65911_IRQ_GPIO4_F 20
728 #define TPS65911_IRQ_GPIO5_R 21
729 #define TPS65911_IRQ_GPIO5_F 22
730 #define TPS65911_IRQ_WTCHDG 23
731 #define TPS65911_IRQ_PWRDN 24
733 #define TPS65911_NUM_IRQ 25
736 /* GPIO Register Definitions */
737 #define TPS65910_GPIO_DEB BIT(2)
738 #define TPS65910_GPIO_PUEN BIT(3)
739 #define TPS65910_GPIO_CFG BIT(2)
740 #define TPS65910_GPIO_STS BIT(1)
741 #define TPS65910_GPIO_SET BIT(0)
743 /**
744 * struct tps65910_board
745 * Board platform data may be used to initialize regulators.
746 */
748 struct tps65910_board {
749 int gpio_base;
750 int irq;
751 int irq_base;
752 int vmbch_threshold;
753 int vmbch2_threshold;
754 struct regulator_init_data *tps65910_pmic_init_data;
755 };
757 /**
758 * struct tps65910 - tps65910 sub-driver chip access routines
759 */
761 struct tps65910 {
762 struct device *dev;
763 struct i2c_client *i2c_client;
764 struct mutex io_mutex;
765 unsigned int id;
766 int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
767 int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src);
769 /* Client devices */
770 struct tps65910_pmic *pmic;
771 struct tps65910_rtc *rtc;
772 struct tps65910_power *power;
774 /* GPIO Handling */
775 struct gpio_chip gpio;
777 /* IRQ Handling */
778 struct mutex irq_lock;
779 int chip_irq;
780 int irq_base;
781 int irq_num;
782 u32 irq_mask;
783 };
785 struct tps65910_platform_data {
786 int irq;
787 int irq_base;
788 };
790 int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
791 int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
792 void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
793 int tps65910_irq_init(struct tps65910 *tps65910, int irq,
794 struct tps65910_platform_data *pdata);
795 int tps65910_irq_exit(struct tps65910 *tps65910);
797 static inline int tps65910_chip_id(struct tps65910 *tps65910)
798 {
799 return tps65910->id;
800 }
802 #endif /* __LINUX_MFD_TPS65910_H */