sound/soc/davinci/davinci-i2s.c

   1 /*
   2  * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
   3  *
   4  * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
   5  * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/device.h>
  15 #include <linux/slab.h>
  16 #include <linux/delay.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19
  20 #include <sound/core.h>
  21 #include <sound/pcm.h>
  22 #include <sound/pcm_params.h>
  23 #include <sound/initval.h>
  24 #include <sound/soc.h>
  25
  26 #include <mach/asp.h>
  27
  28 #include "davinci-pcm.h"
  29 #include "davinci-i2s.h"
  30
  31
  32 /*
  33  * NOTE:  terminology here is confusing.
  34  *
  35  *  - This driver supports the "Audio Serial Port" (ASP),
  36  *    found on dm6446, dm355, and other DaVinci chips.
  37  *
  38  *  - But it labels it a "Multi-channel Buffered Serial Port"
  39  *    (McBSP) as on older chips like the dm642 ... which was
  40  *    backward-compatible, possibly explaining that confusion.
  41  *
  42  *  - OMAP chips have a controller called McBSP, which is
  43  *    incompatible with the DaVinci flavor of McBSP.
  44  *
  45  *  - Newer DaVinci chips have a controller called McASP,
  46  *    incompatible with ASP and with either McBSP.
  47  *
  48  * In short:  this uses ASP to implement I2S, not McBSP.
  49  * And it won't be the only DaVinci implemention of I2S.
  50  */
  51 #define DAVINCI_MCBSP_DRR_REG   0x00
  52 #define DAVINCI_MCBSP_DXR_REG   0x04
  53 #define DAVINCI_MCBSP_SPCR_REG  0x08
  54 #define DAVINCI_MCBSP_RCR_REG   0x0c
  55 #define DAVINCI_MCBSP_XCR_REG   0x10
  56 #define DAVINCI_MCBSP_SRGR_REG  0x14
  57 #define DAVINCI_MCBSP_PCR_REG   0x24
  58
  59 #define DAVINCI_MCBSP_SPCR_RRST         (1 << 0)
  60 #define DAVINCI_MCBSP_SPCR_RINTM(v)     ((v) << 4)
  61 #define DAVINCI_MCBSP_SPCR_XRST         (1 << 16)
  62 #define DAVINCI_MCBSP_SPCR_XINTM(v)     ((v) << 20)
  63 #define DAVINCI_MCBSP_SPCR_GRST         (1 << 22)
  64 #define DAVINCI_MCBSP_SPCR_FRST         (1 << 23)
  65 #define DAVINCI_MCBSP_SPCR_FREE         (1 << 25)
  66
  67 #define DAVINCI_MCBSP_RCR_RWDLEN1(v)    ((v) << 5)
  68 #define DAVINCI_MCBSP_RCR_RFRLEN1(v)    ((v) << 8)
  69 #define DAVINCI_MCBSP_RCR_RDATDLY(v)    ((v) << 16)
  70 #define DAVINCI_MCBSP_RCR_RFIG          (1 << 18)
  71 #define DAVINCI_MCBSP_RCR_RWDLEN2(v)    ((v) << 21)
  72 #define DAVINCI_MCBSP_RCR_RFRLEN2(v)    ((v) << 24)
  73 #define DAVINCI_MCBSP_RCR_RPHASE        BIT(31)
  74
  75 #define DAVINCI_MCBSP_XCR_XWDLEN1(v)    ((v) << 5)
  76 #define DAVINCI_MCBSP_XCR_XFRLEN1(v)    ((v) << 8)
  77 #define DAVINCI_MCBSP_XCR_XDATDLY(v)    ((v) << 16)
  78 #define DAVINCI_MCBSP_XCR_XFIG          (1 << 18)
  79 #define DAVINCI_MCBSP_XCR_XWDLEN2(v)    ((v) << 21)
  80 #define DAVINCI_MCBSP_XCR_XFRLEN2(v)    ((v) << 24)
  81 #define DAVINCI_MCBSP_XCR_XPHASE        BIT(31)
  82
  83 #define DAVINCI_MCBSP_SRGR_FWID(v)      ((v) << 8)
  84 #define DAVINCI_MCBSP_SRGR_FPER(v)      ((v) << 16)
  85 #define DAVINCI_MCBSP_SRGR_FSGM         (1 << 28)
  86 #define DAVINCI_MCBSP_SRGR_CLKSM        BIT(29)
  87
  88 #define DAVINCI_MCBSP_PCR_CLKRP         (1 << 0)
  89 #define DAVINCI_MCBSP_PCR_CLKXP         (1 << 1)
  90 #define DAVINCI_MCBSP_PCR_FSRP          (1 << 2)
  91 #define DAVINCI_MCBSP_PCR_FSXP          (1 << 3)
  92 #define DAVINCI_MCBSP_PCR_SCLKME        (1 << 7)
  93 #define DAVINCI_MCBSP_PCR_CLKRM         (1 << 8)
  94 #define DAVINCI_MCBSP_PCR_CLKXM         (1 << 9)
  95 #define DAVINCI_MCBSP_PCR_FSRM          (1 << 10)
  96 #define DAVINCI_MCBSP_PCR_FSXM          (1 << 11)
  97
  98 enum {
  99         DAVINCI_MCBSP_WORD_8 = 0,
 100         DAVINCI_MCBSP_WORD_12,
 101         DAVINCI_MCBSP_WORD_16,
 102         DAVINCI_MCBSP_WORD_20,
 103         DAVINCI_MCBSP_WORD_24,
 104         DAVINCI_MCBSP_WORD_32,
 105 };
 106
 107 static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
 108         [SNDRV_PCM_FORMAT_S8]           = 1,
 109         [SNDRV_PCM_FORMAT_S16_LE]       = 2,
 110         [SNDRV_PCM_FORMAT_S32_LE]       = 4,
 111 };
 112
 113 static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
 114         [SNDRV_PCM_FORMAT_S8]           = DAVINCI_MCBSP_WORD_8,
 115         [SNDRV_PCM_FORMAT_S16_LE]       = DAVINCI_MCBSP_WORD_16,
 116         [SNDRV_PCM_FORMAT_S32_LE]       = DAVINCI_MCBSP_WORD_32,
 117 };
 118
 119 static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
 120         [SNDRV_PCM_FORMAT_S8]           = SNDRV_PCM_FORMAT_S16_LE,
 121         [SNDRV_PCM_FORMAT_S16_LE]       = SNDRV_PCM_FORMAT_S32_LE,
 122 };
 123
 124 struct davinci_mcbsp_dev {
 125         struct device *dev;
 126         struct davinci_pcm_dma_params   dma_params[2];
 127         void __iomem                    *base;
 128 #define MOD_DSP_A       0
 129 #define MOD_DSP_B       1
 130         int                             mode;
 131         u32                             pcr;
 132         struct clk                      *clk;
 133         /*
 134          * Combining both channels into 1 element will at least double the
 135          * amount of time between servicing the dma channel, increase
 136          * effiency, and reduce the chance of overrun/underrun. But,
 137          * it will result in the left & right channels being swapped.
 138          *
 139          * If relabeling the left and right channels is not possible,
 140          * you may want to let the codec know to swap them back.
 141          *
 142          * It may allow x10 the amount of time to service dma requests,
 143          * if the codec is master and is using an unnecessarily fast bit clock
 144          * (ie. tlvaic23b), independent of the sample rate. So, having an
 145          * entire frame at once means it can be serviced at the sample rate
 146          * instead of the bit clock rate.
 147          *
 148          * In the now unlikely case that an underrun still
 149          * occurs, both the left and right samples will be repeated
 150          * so that no pops are heard, and the left and right channels
 151          * won't end up being swapped because of the underrun.
 152          */
 153         unsigned enable_channel_combine:1;
 154
 155         unsigned int fmt;
 156         int clk_div;
 157         int clk_input_pin;
 158         bool i2s_accurate_sck;
 159 };
 160
 161 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
 162                                            int reg, u32 val)
 163 {
 164         __raw_writel(val, dev->base + reg);
 165 }
 166
 167 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
 168 {
 169         return __raw_readl(dev->base + reg);
 170 }
 171
 172 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
 173 {
 174         u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
 175         /* The clock needs to toggle to complete reset.
 176          * So, fake it by toggling the clk polarity.
 177          */
 178         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
 179         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
 180 }
 181
 182 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
 183                 struct snd_pcm_substream *substream)
 184 {
 185         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 186         struct snd_soc_platform *platform = rtd->platform;
 187         int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 188         u32 spcr;
 189         u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
 190         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 191         if (spcr & mask) {
 192                 /* start off disabled */
 193                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
 194                                 spcr & ~mask);
 195                 toggle_clock(dev, playback);
 196         }
 197         if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
 198                         DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
 199                 /* Start the sample generator */
 200                 spcr |= DAVINCI_MCBSP_SPCR_GRST;
 201                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 202         }
 203
 204         if (playback) {
 205                 /* Stop the DMA to avoid data loss */
 206                 /* while the transmitter is out of reset to handle XSYNCERR */
 207                 if (platform->driver->ops->trigger) {
 208                         int ret = platform->driver->ops->trigger(substream,
 209                                 SNDRV_PCM_TRIGGER_STOP);
 210                         if (ret < 0)
 211                                 printk(KERN_DEBUG "Playback DMA stop failed\n");
 212                 }
 213
 214                 /* Enable the transmitter */
 215                 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 216                 spcr |= DAVINCI_MCBSP_SPCR_XRST;
 217                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 218
 219                 /* wait for any unexpected frame sync error to occur */
 220                 udelay(100);
 221
 222                 /* Disable the transmitter to clear any outstanding XSYNCERR */
 223                 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 224                 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
 225                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 226                 toggle_clock(dev, playback);
 227
 228                 /* Restart the DMA */
 229                 if (platform->driver->ops->trigger) {
 230                         int ret = platform->driver->ops->trigger(substream,
 231                                 SNDRV_PCM_TRIGGER_START);
 232                         if (ret < 0)
 233                                 printk(KERN_DEBUG "Playback DMA start failed\n");
 234                 }
 235         }
 236
 237         /* Enable transmitter or receiver */
 238         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 239         spcr |= mask;
 240
 241         if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
 242                 /* Start frame sync */
 243                 spcr |= DAVINCI_MCBSP_SPCR_FRST;
 244         }
 245         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 246 }
 247
 248 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
 249 {
 250         u32 spcr;
 251
 252         /* Reset transmitter/receiver and sample rate/frame sync generators */
 253         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 254         spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
 255         spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
 256         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 257         toggle_clock(dev, playback);
 258 }
 259
 260 #define DEFAULT_BITPERSAMPLE    16
 261
 262 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 263                                    unsigned int fmt)
 264 {
 265         struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
 266         unsigned int pcr;
 267         unsigned int srgr;
 268         /* Attention srgr is updated by hw_params! */
 269         srgr = DAVINCI_MCBSP_SRGR_FSGM |
 270                 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
 271                 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
 272
 273         dev->fmt = fmt;
 274         /* set master/slave audio interface */
 275         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 276         case SND_SOC_DAIFMT_CBS_CFS:
 277                 /* cpu is master */
 278                 pcr = DAVINCI_MCBSP_PCR_FSXM |
 279                         DAVINCI_MCBSP_PCR_FSRM |
 280                         DAVINCI_MCBSP_PCR_CLKXM |
 281                         DAVINCI_MCBSP_PCR_CLKRM;
 282                 break;
 283         case SND_SOC_DAIFMT_CBM_CFS:
 284                 pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
 285                 /*
 286                  * Selection of the clock input pin that is the
 287                  * input for the Sample Rate Generator.
 288                  * McBSP FSR and FSX are driven by the Sample Rate
 289                  * Generator.
 290                  */
 291                 switch (dev->clk_input_pin) {
 292                 case MCBSP_CLKS:
 293                         pcr |= DAVINCI_MCBSP_PCR_CLKXM |
 294                                 DAVINCI_MCBSP_PCR_CLKRM;
 295                         break;
 296                 case MCBSP_CLKR:
 297                         pcr |= DAVINCI_MCBSP_PCR_SCLKME;
 298                         break;
 299                 default:
 300                         dev_err(dev->dev, "bad clk_input_pin\n");
 301                         return -EINVAL;
 302                 }
 303
 304                 break;
 305         case SND_SOC_DAIFMT_CBM_CFM:
 306                 /* codec is master */
 307                 pcr = 0;
 308                 break;
 309         default:
 310                 printk(KERN_ERR "%s:bad master\n", __func__);
 311                 return -EINVAL;
 312         }
 313
 314         /* interface format */
 315         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 316         case SND_SOC_DAIFMT_I2S:
 317                 /* Davinci doesn't support TRUE I2S, but some codecs will have
 318                  * the left and right channels contiguous. This allows
 319                  * dsp_a mode to be used with an inverted normal frame clk.
 320                  * If your codec is master and does not have contiguous
 321                  * channels, then you will have sound on only one channel.
 322                  * Try using a different mode, or codec as slave.
 323                  *
 324                  * The TLV320AIC33 is an example of a codec where this works.
 325                  * It has a variable bit clock frequency allowing it to have
 326                  * valid data on every bit clock.
 327                  *
 328                  * The TLV320AIC23 is an example of a codec where this does not
 329                  * work. It has a fixed bit clock frequency with progressively
 330                  * more empty bit clock slots between channels as the sample
 331                  * rate is lowered.
 332                  */
 333                 fmt ^= SND_SOC_DAIFMT_NB_IF;
 334         case SND_SOC_DAIFMT_DSP_A:
 335                 dev->mode = MOD_DSP_A;
 336                 break;
 337         case SND_SOC_DAIFMT_DSP_B:
 338                 dev->mode = MOD_DSP_B;
 339                 break;
 340         default:
 341                 printk(KERN_ERR "%s:bad format\n", __func__);
 342                 return -EINVAL;
 343         }
 344
 345         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 346         case SND_SOC_DAIFMT_NB_NF:
 347                 /* CLKRP Receive clock polarity,
 348                  *      1 - sampled on rising edge of CLKR
 349                  *      valid on rising edge
 350                  * CLKXP Transmit clock polarity,
 351                  *      1 - clocked on falling edge of CLKX
 352                  *      valid on rising edge
 353                  * FSRP  Receive frame sync pol, 0 - active high
 354                  * FSXP  Transmit frame sync pol, 0 - active high
 355                  */
 356                 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
 357                 break;
 358         case SND_SOC_DAIFMT_IB_IF:
 359                 /* CLKRP Receive clock polarity,
 360                  *      0 - sampled on falling edge of CLKR
 361                  *      valid on falling edge
 362                  * CLKXP Transmit clock polarity,
 363                  *      0 - clocked on rising edge of CLKX
 364                  *      valid on falling edge
 365                  * FSRP  Receive frame sync pol, 1 - active low
 366                  * FSXP  Transmit frame sync pol, 1 - active low
 367                  */
 368                 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
 369                 break;
 370         case SND_SOC_DAIFMT_NB_IF:
 371                 /* CLKRP Receive clock polarity,
 372                  *      1 - sampled on rising edge of CLKR
 373                  *      valid on rising edge
 374                  * CLKXP Transmit clock polarity,
 375                  *      1 - clocked on falling edge of CLKX
 376                  *      valid on rising edge
 377                  * FSRP  Receive frame sync pol, 1 - active low
 378                  * FSXP  Transmit frame sync pol, 1 - active low
 379                  */
 380                 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
 381                         DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
 382                 break;
 383         case SND_SOC_DAIFMT_IB_NF:
 384                 /* CLKRP Receive clock polarity,
 385                  *      0 - sampled on falling edge of CLKR
 386                  *      valid on falling edge
 387                  * CLKXP Transmit clock polarity,
 388                  *      0 - clocked on rising edge of CLKX
 389                  *      valid on falling edge
 390                  * FSRP  Receive frame sync pol, 0 - active high
 391                  * FSXP  Transmit frame sync pol, 0 - active high
 392                  */
 393                 break;
 394         default:
 395                 return -EINVAL;
 396         }
 397         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
 398         dev->pcr = pcr;
 399         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
 400         return 0;
 401 }
 402
 403 static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 404                                 int div_id, int div)
 405 {
 406         struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
 407
 408         if (div_id != DAVINCI_MCBSP_CLKGDV)
 409                 return -ENODEV;
 410
 411         dev->clk_div = div;
 412         return 0;
 413 }
 414
 415 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 416                                  struct snd_pcm_hw_params *params,
 417                                  struct snd_soc_dai *dai)
 418 {
 419         struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
 420         struct davinci_pcm_dma_params *dma_params =
 421                                         &dev->dma_params[substream->stream];
 422         struct snd_interval *i = NULL;
 423         int mcbsp_word_length, master;
 424         unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
 425         u32 spcr;
 426         snd_pcm_format_t fmt;
 427         unsigned element_cnt = 1;
 428
 429         /* general line settings */
 430         spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
 431         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 432                 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
 433                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 434         } else {
 435                 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
 436                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 437         }
 438
 439         master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 440         fmt = params_format(params);
 441         mcbsp_word_length = asp_word_length[fmt];
 442
 443         switch (master) {
 444         case SND_SOC_DAIFMT_CBS_CFS:
 445                 freq = clk_get_rate(dev->clk);
 446                 srgr = DAVINCI_MCBSP_SRGR_FSGM |
 447                        DAVINCI_MCBSP_SRGR_CLKSM;
 448                 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
 449                                                 8 - 1);
 450                 if (dev->i2s_accurate_sck) {
 451                         clk_div = 256;
 452                         do {
 453                                 framesize = (freq / (--clk_div)) /
 454                                 params->rate_num *
 455                                         params->rate_den;
 456                         } while (((framesize < 33) || (framesize > 4095)) &&
 457                                  (clk_div));
 458                         clk_div--;
 459                         srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
 460                 } else {
 461                         /* symmetric waveforms */
 462                         clk_div = freq / (mcbsp_word_length * 16) /
 463                                   params->rate_num * params->rate_den;
 464                         srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
 465                                                         16 - 1);
 466                 }
 467                 clk_div &= 0xFF;
 468                 srgr |= clk_div;
 469                 break;
 470         case SND_SOC_DAIFMT_CBM_CFS:
 471                 srgr = DAVINCI_MCBSP_SRGR_FSGM;
 472                 clk_div = dev->clk_div - 1;
 473                 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
 474                 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
 475                 clk_div &= 0xFF;
 476                 srgr |= clk_div;
 477                 break;
 478         case SND_SOC_DAIFMT_CBM_CFM:
 479                 /* Clock and frame sync given from external sources */
 480                 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
 481                 srgr = DAVINCI_MCBSP_SRGR_FSGM;
 482                 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
 483                 pr_debug("%s - %d  FWID set: re-read srgr = %X\n",
 484                         __func__, __LINE__, snd_interval_value(i) - 1);
 485
 486                 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
 487                 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
 488                 break;
 489         default:
 490                 return -EINVAL;
 491         }
 492         davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
 493
 494         rcr = DAVINCI_MCBSP_RCR_RFIG;
 495         xcr = DAVINCI_MCBSP_XCR_XFIG;
 496         if (dev->mode == MOD_DSP_B) {
 497                 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
 498                 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
 499         } else {
 500                 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
 501                 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
 502         }
 503         /* Determine xfer data type */
 504         fmt = params_format(params);
 505         if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
 506                 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
 507                 return -EINVAL;
 508         }
 509
 510         if (params_channels(params) == 2) {
 511                 element_cnt = 2;
 512                 if (double_fmt[fmt] && dev->enable_channel_combine) {
 513                         element_cnt = 1;
 514                         fmt = double_fmt[fmt];
 515                 }
 516                 switch (master) {
 517                 case SND_SOC_DAIFMT_CBS_CFS:
 518                 case SND_SOC_DAIFMT_CBS_CFM:
 519                         rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
 520                         xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
 521                         rcr |= DAVINCI_MCBSP_RCR_RPHASE;
 522                         xcr |= DAVINCI_MCBSP_XCR_XPHASE;
 523                         break;
 524                 case SND_SOC_DAIFMT_CBM_CFM:
 525                 case SND_SOC_DAIFMT_CBM_CFS:
 526                         rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
 527                         xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
 528                         break;
 529                 default:
 530                         return -EINVAL;
 531                 }
 532         }
 533         dma_params->acnt = dma_params->data_type = data_type[fmt];
 534         dma_params->fifo_level = 0;
 535         mcbsp_word_length = asp_word_length[fmt];
 536
 537         switch (master) {
 538         case SND_SOC_DAIFMT_CBS_CFS:
 539         case SND_SOC_DAIFMT_CBS_CFM:
 540                 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
 541                 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
 542                 break;
 543         case SND_SOC_DAIFMT_CBM_CFM:
 544         case SND_SOC_DAIFMT_CBM_CFS:
 545                 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
 546                 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
 547                 break;
 548         default:
 549                 return -EINVAL;
 550         }
 551
 552         rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
 553                 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
 554         xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
 555                 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
 556
 557         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 558                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
 559         else
 560                 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
 561
 562         pr_debug("%s - %d  srgr=%X\n", __func__, __LINE__, srgr);
 563         pr_debug("%s - %d  xcr=%X\n", __func__, __LINE__, xcr);
 564         pr_debug("%s - %d  rcr=%X\n", __func__, __LINE__, rcr);
 565         return 0;
 566 }
 567
 568 static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
 569                 struct snd_soc_dai *dai)
 570 {
 571         struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
 572         int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 573         davinci_mcbsp_stop(dev, playback);
 574         return 0;
 575 }
 576
 577 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 578                                struct snd_soc_dai *dai)
 579 {
 580         struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
 581         int ret = 0;
 582         int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 583
 584         switch (cmd) {
 585         case SNDRV_PCM_TRIGGER_START:
 586         case SNDRV_PCM_TRIGGER_RESUME:
 587         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 588                 davinci_mcbsp_start(dev, substream);
 589                 break;
 590         case SNDRV_PCM_TRIGGER_STOP:
 591         case SNDRV_PCM_TRIGGER_SUSPEND:
 592         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 593                 davinci_mcbsp_stop(dev, playback);
 594                 break;
 595         default:
 596                 ret = -EINVAL;
 597         }
 598         return ret;
 599 }
 600
 601 static int davinci_i2s_startup(struct snd_pcm_substream *substream,
 602                                struct snd_soc_dai *dai)
 603 {
 604         struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
 605
 606         snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
 607         return 0;
 608 }
 609
 610 static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
 611                 struct snd_soc_dai *dai)
 612 {
 613         struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
 614         int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 615         davinci_mcbsp_stop(dev, playback);
 616 }
 617
 618 #define DAVINCI_I2S_RATES       SNDRV_PCM_RATE_8000_96000
 619
 620 static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
 621         .startup        = davinci_i2s_startup,
 622         .shutdown       = davinci_i2s_shutdown,
 623         .prepare        = davinci_i2s_prepare,
 624         .trigger        = davinci_i2s_trigger,
 625         .hw_params      = davinci_i2s_hw_params,
 626         .set_fmt        = davinci_i2s_set_dai_fmt,
 627         .set_clkdiv     = davinci_i2s_dai_set_clkdiv,
 628
 629 };
 630
 631 static struct snd_soc_dai_driver davinci_i2s_dai = {
 632         .playback = {
 633                 .channels_min = 2,
 634                 .channels_max = 2,
 635                 .rates = DAVINCI_I2S_RATES,
 636                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 637         .capture = {
 638                 .channels_min = 2,
 639                 .channels_max = 2,
 640                 .rates = DAVINCI_I2S_RATES,
 641                 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
 642         .ops = &davinci_i2s_dai_ops,
 643
 644 };
 645
 646 static int davinci_i2s_probe(struct platform_device *pdev)
 647 {
 648         struct snd_platform_data *pdata = pdev->dev.platform_data;
 649         struct davinci_mcbsp_dev *dev;
 650         struct resource *mem, *ioarea, *res;
 651         enum dma_event_q asp_chan_q = EVENTQ_0;
 652         enum dma_event_q ram_chan_q = EVENTQ_1;
 653         int ret;
 654
 655         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 656         if (!mem) {
 657                 dev_err(&pdev->dev, "no mem resource?\n");
 658                 return -ENODEV;
 659         }
 660
 661         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 662                                     pdev->name);
 663         if (!ioarea) {
 664                 dev_err(&pdev->dev, "McBSP region already claimed\n");
 665                 return -EBUSY;
 666         }
 667
 668         dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
 669         if (!dev) {
 670                 ret = -ENOMEM;
 671                 goto err_release_region;
 672         }
 673         if (pdata) {
 674                 dev->enable_channel_combine = pdata->enable_channel_combine;
 675                 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].sram_size =
 676                         pdata->sram_size_playback;
 677                 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
 678                         pdata->sram_size_capture;
 679                 dev->clk_input_pin = pdata->clk_input_pin;
 680                 dev->i2s_accurate_sck = pdata->i2s_accurate_sck;
 681                 asp_chan_q = pdata->asp_chan_q;
 682                 ram_chan_q = pdata->ram_chan_q;
 683         }
 684
 685         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].asp_chan_q   = asp_chan_q;
 686         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].ram_chan_q   = ram_chan_q;
 687         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].asp_chan_q    = asp_chan_q;
 688         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].ram_chan_q    = ram_chan_q;
 689
 690         dev->clk = clk_get(&pdev->dev, NULL);
 691         if (IS_ERR(dev->clk)) {
 692                 ret = -ENODEV;
 693                 goto err_free_mem;
 694         }
 695         clk_enable(dev->clk);
 696
 697         dev->base = (void __iomem *)IO_ADDRESS(mem->start);
 698
 699         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].dma_addr =
 700             (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
 701
 702         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].dma_addr =
 703             (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
 704
 705         /* first TX, then RX */
 706         res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 707         if (!res) {
 708                 dev_err(&pdev->dev, "no DMA resource\n");
 709                 ret = -ENXIO;
 710                 goto err_free_mem;
 711         }
 712         dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].channel = res->start;
 713
 714         res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
 715         if (!res) {
 716                 dev_err(&pdev->dev, "no DMA resource\n");
 717                 ret = -ENXIO;
 718                 goto err_free_mem;
 719         }
 720         dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start;
 721         dev->dev = &pdev->dev;
 722
 723         dev_set_drvdata(&pdev->dev, dev);
 724
 725         ret = snd_soc_register_dai(&pdev->dev, &davinci_i2s_dai);
 726         if (ret != 0)
 727                 goto err_free_mem;
 728
 729         return 0;
 730
 731 err_free_mem:
 732         kfree(dev);
 733 err_release_region:
 734         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 735
 736         return ret;
 737 }
 738
 739 static int davinci_i2s_remove(struct platform_device *pdev)
 740 {
 741         struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev);
 742         struct resource *mem;
 743
 744         snd_soc_unregister_dai(&pdev->dev);
 745         clk_disable(dev->clk);
 746         clk_put(dev->clk);
 747         dev->clk = NULL;
 748         kfree(dev);
 749         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 750         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 751
 752         return 0;
 753 }
 754
 755 static struct platform_driver davinci_mcbsp_driver = {
 756         .probe          = davinci_i2s_probe,
 757         .remove         = davinci_i2s_remove,
 758         .driver         = {
 759                 .name   = "davinci-mcbsp",
 760                 .owner  = THIS_MODULE,
 761         },
 762 };
 763
 764 static int __init davinci_i2s_init(void)
 765 {
 766         return platform_driver_register(&davinci_mcbsp_driver);
 767 }
 768 module_init(davinci_i2s_init);
 769
 770 static void __exit davinci_i2s_exit(void)
 771 {
 772         platform_driver_unregister(&davinci_mcbsp_driver);
 773 }
 774 module_exit(davinci_i2s_exit);
 775
 776 MODULE_AUTHOR("Vladimir Barinov");
 777 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
 778 MODULE_LICENSE("GPL");