1 /*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/io.h>
24 #include <linux/clk.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/initval.h>
30 #include <sound/soc.h>
32 #include "davinci-pcm.h"
33 #include "davinci-mcasp.h"
35 /*
36 * McASP register definitions
37 */
38 #define DAVINCI_MCASP_PID_REG 0x00
39 #define DAVINCI_MCASP_PWREMUMGT_REG 0x04
41 #define DAVINCI_MCASP_PFUNC_REG 0x10
42 #define DAVINCI_MCASP_PDIR_REG 0x14
43 #define DAVINCI_MCASP_PDOUT_REG 0x18
44 #define DAVINCI_MCASP_PDSET_REG 0x1c
46 #define DAVINCI_MCASP_PDCLR_REG 0x20
48 #define DAVINCI_MCASP_TLGC_REG 0x30
49 #define DAVINCI_MCASP_TLMR_REG 0x34
51 #define DAVINCI_MCASP_GBLCTL_REG 0x44
52 #define DAVINCI_MCASP_AMUTE_REG 0x48
53 #define DAVINCI_MCASP_LBCTL_REG 0x4c
55 #define DAVINCI_MCASP_TXDITCTL_REG 0x50
57 #define DAVINCI_MCASP_GBLCTLR_REG 0x60
58 #define DAVINCI_MCASP_RXMASK_REG 0x64
59 #define DAVINCI_MCASP_RXFMT_REG 0x68
60 #define DAVINCI_MCASP_RXFMCTL_REG 0x6c
62 #define DAVINCI_MCASP_ACLKRCTL_REG 0x70
63 #define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
64 #define DAVINCI_MCASP_RXTDM_REG 0x78
65 #define DAVINCI_MCASP_EVTCTLR_REG 0x7c
67 #define DAVINCI_MCASP_RXSTAT_REG 0x80
68 #define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
69 #define DAVINCI_MCASP_RXCLKCHK_REG 0x88
70 #define DAVINCI_MCASP_REVTCTL_REG 0x8c
72 #define DAVINCI_MCASP_GBLCTLX_REG 0xa0
73 #define DAVINCI_MCASP_TXMASK_REG 0xa4
74 #define DAVINCI_MCASP_TXFMT_REG 0xa8
75 #define DAVINCI_MCASP_TXFMCTL_REG 0xac
77 #define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
78 #define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
79 #define DAVINCI_MCASP_TXTDM_REG 0xb8
80 #define DAVINCI_MCASP_EVTCTLX_REG 0xbc
82 #define DAVINCI_MCASP_TXSTAT_REG 0xc0
83 #define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
84 #define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
85 #define DAVINCI_MCASP_XEVTCTL_REG 0xcc
87 /* Left(even TDM Slot) Channel Status Register File */
88 #define DAVINCI_MCASP_DITCSRA_REG 0x100
89 /* Right(odd TDM slot) Channel Status Register File */
90 #define DAVINCI_MCASP_DITCSRB_REG 0x118
91 /* Left(even TDM slot) User Data Register File */
92 #define DAVINCI_MCASP_DITUDRA_REG 0x130
93 /* Right(odd TDM Slot) User Data Register File */
94 #define DAVINCI_MCASP_DITUDRB_REG 0x148
96 /* Serializer n Control Register */
97 #define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
98 #define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
99 (n << 2))
101 /* Transmit Buffer for Serializer n */
102 #define DAVINCI_MCASP_TXBUF_REG 0x200
103 /* Receive Buffer for Serializer n */
104 #define DAVINCI_MCASP_RXBUF_REG 0x280
106 /* McASP FIFO Registers */
107 #define DAVINCI_MCASP_WFIFOCTL (0x1010)
108 #define DAVINCI_MCASP_WFIFOSTS (0x1014)
109 #define DAVINCI_MCASP_RFIFOCTL (0x1018)
110 #define DAVINCI_MCASP_RFIFOSTS (0x101C)
111 #define MCASP_VER3_WFIFOCTL (0x1000)
112 #define MCASP_VER3_WFIFOSTS (0x1004)
113 #define MCASP_VER3_RFIFOCTL (0x1008)
114 #define MCASP_VER3_RFIFOSTS (0x100C)
116 /*
117 * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
118 * Register Bits
119 */
120 #define MCASP_FREE BIT(0)
121 #define MCASP_SOFT BIT(1)
123 /*
124 * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
125 */
126 #define AXR(n) (1<<n)
127 #define PFUNC_AMUTE BIT(25)
128 #define ACLKX BIT(26)
129 #define AHCLKX BIT(27)
130 #define AFSX BIT(28)
131 #define ACLKR BIT(29)
132 #define AHCLKR BIT(30)
133 #define AFSR BIT(31)
135 /*
136 * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
137 */
138 #define AXR(n) (1<<n)
139 #define PDIR_AMUTE BIT(25)
140 #define ACLKX BIT(26)
141 #define AHCLKX BIT(27)
142 #define AFSX BIT(28)
143 #define ACLKR BIT(29)
144 #define AHCLKR BIT(30)
145 #define AFSR BIT(31)
147 /*
148 * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
149 */
150 #define DITEN BIT(0) /* Transmit DIT mode enable/disable */
151 #define VA BIT(2)
152 #define VB BIT(3)
154 /*
155 * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
156 */
157 #define TXROT(val) (val)
158 #define TXSEL BIT(3)
159 #define TXSSZ(val) (val<<4)
160 #define TXPBIT(val) (val<<8)
161 #define TXPAD(val) (val<<13)
162 #define TXORD BIT(15)
163 #define FSXDLY(val) (val<<16)
165 /*
166 * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
167 */
168 #define RXROT(val) (val)
169 #define RXSEL BIT(3)
170 #define RXSSZ(val) (val<<4)
171 #define RXPBIT(val) (val<<8)
172 #define RXPAD(val) (val<<13)
173 #define RXORD BIT(15)
174 #define FSRDLY(val) (val<<16)
176 /*
177 * DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
178 */
179 #define FSXPOL BIT(0)
180 #define AFSXE BIT(1)
181 #define FSXDUR BIT(4)
182 #define FSXMOD(val) (val<<7)
184 /*
185 * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
186 */
187 #define FSRPOL BIT(0)
188 #define AFSRE BIT(1)
189 #define FSRDUR BIT(4)
190 #define FSRMOD(val) (val<<7)
192 /*
193 * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
194 */
195 #define ACLKXDIV(val) (val)
196 #define ACLKXE BIT(5)
197 #define TX_ASYNC BIT(6)
198 #define ACLKXPOL BIT(7)
200 /*
201 * DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
202 */
203 #define ACLKRDIV(val) (val)
204 #define ACLKRE BIT(5)
205 #define RX_ASYNC BIT(6)
206 #define ACLKRPOL BIT(7)
208 /*
209 * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
210 * Register Bits
211 */
212 #define AHCLKXDIV(val) (val)
213 #define AHCLKXPOL BIT(14)
214 #define AHCLKXE BIT(15)
216 /*
217 * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
218 * Register Bits
219 */
220 #define AHCLKRDIV(val) (val)
221 #define AHCLKRPOL BIT(14)
222 #define AHCLKRE BIT(15)
224 /*
225 * DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
226 */
227 #define MODE(val) (val)
228 #define DISMOD (val)(val<<2)
229 #define TXSTATE BIT(4)
230 #define RXSTATE BIT(5)
232 /*
233 * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
234 */
235 #define LBEN BIT(0)
236 #define LBORD BIT(1)
237 #define LBGENMODE(val) (val<<2)
239 /*
240 * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
241 */
242 #define TXTDMS(n) (1<<n)
244 /*
245 * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
246 */
247 #define RXTDMS(n) (1<<n)
249 /*
250 * DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
251 */
252 #define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
253 #define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
254 #define RXSERCLR BIT(2) /* Receiver Serializer Clear */
255 #define RXSMRST BIT(3) /* Receiver State Machine Reset */
256 #define RXFSRST BIT(4) /* Frame Sync Generator Reset */
257 #define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
258 #define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
259 #define TXSERCLR BIT(10) /* Transmit Serializer Clear */
260 #define TXSMRST BIT(11) /* Transmitter State Machine Reset */
261 #define TXFSRST BIT(12) /* Frame Sync Generator Reset */
263 /*
264 * DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
265 */
266 #define MUTENA(val) (val)
267 #define MUTEINPOL BIT(2)
268 #define MUTEINENA BIT(3)
269 #define MUTEIN BIT(4)
270 #define MUTER BIT(5)
271 #define MUTEX BIT(6)
272 #define MUTEFSR BIT(7)
273 #define MUTEFSX BIT(8)
274 #define MUTEBADCLKR BIT(9)
275 #define MUTEBADCLKX BIT(10)
276 #define MUTERXDMAERR BIT(11)
277 #define MUTETXDMAERR BIT(12)
279 /*
280 * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
281 */
282 #define RXDATADMADIS BIT(0)
284 /*
285 * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
286 */
287 #define TXDATADMADIS BIT(0)
289 /*
290 * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
291 */
292 #define FIFO_ENABLE BIT(16)
293 #define NUMEVT_MASK (0xFF << 8)
294 #define NUMDMA_MASK (0xFF)
296 #define DAVINCI_MCASP_NUM_SERIALIZER 16
298 static inline void mcasp_set_bits(void __iomem *reg, u32 val)
299 {
300 __raw_writel(__raw_readl(reg) | val, reg);
301 }
303 static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
304 {
305 __raw_writel((__raw_readl(reg) & ~(val)), reg);
306 }
308 static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
309 {
310 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
311 }
313 static inline void mcasp_set_reg(void __iomem *reg, u32 val)
314 {
315 __raw_writel(val, reg);
316 }
318 static inline u32 mcasp_get_reg(void __iomem *reg)
319 {
320 return (unsigned int)__raw_readl(reg);
321 }
323 static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
324 {
325 int i = 0;
327 mcasp_set_bits(regs, val);
329 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
330 /* loop count is to avoid the lock-up */
331 for (i = 0; i < 1000; i++) {
332 if ((mcasp_get_reg(regs) & val) == val)
333 break;
334 }
336 if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
337 printk(KERN_ERR "GBLCTL write error\n");
338 }
340 static void mcasp_start_rx(struct davinci_audio_dev *dev)
341 {
342 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
343 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
344 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
345 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
347 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
348 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
349 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
351 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
352 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
353 }
355 static void mcasp_start_tx(struct davinci_audio_dev *dev)
356 {
357 u8 offset = 0, i;
358 u32 cnt;
360 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
361 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
362 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
363 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
365 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
366 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
367 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
368 for (i = 0; i < dev->num_serializer; i++) {
369 if (dev->serial_dir[i] == TX_MODE) {
370 offset = i;
371 break;
372 }
373 }
375 /* wait for TX ready */
376 cnt = 0;
377 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
378 TXSTATE) && (cnt < 100000))
379 cnt++;
381 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
382 }
384 static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
385 {
386 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
387 if (dev->txnumevt) { /* flush and enable FIFO */
388 if (dev->version == MCASP_VERSION_3) {
389 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
390 FIFO_ENABLE);
391 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
392 FIFO_ENABLE);
393 } else {
394 mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
395 FIFO_ENABLE);
396 mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
397 FIFO_ENABLE);
398 }
399 }
400 mcasp_start_tx(dev);
401 } else {
402 if (dev->rxnumevt) { /* flush and enable FIFO */
403 if (dev->version == MCASP_VERSION_3) {
404 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
405 FIFO_ENABLE);
406 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
407 FIFO_ENABLE);
408 } else {
409 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
410 FIFO_ENABLE);
411 mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
412 FIFO_ENABLE);
413 }
414 }
415 mcasp_start_rx(dev);
416 }
417 }
419 static void mcasp_stop_rx(struct davinci_audio_dev *dev)
420 {
421 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
422 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
423 }
425 static void mcasp_stop_tx(struct davinci_audio_dev *dev)
426 {
427 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
428 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
429 }
431 static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
432 {
433 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
434 if (dev->txnumevt) { /* disable FIFO */
435 if (dev->version == MCASP_VERSION_3)
436 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
437 FIFO_ENABLE);
438 else
439 mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
440 FIFO_ENABLE);
441 }
442 mcasp_stop_tx(dev);
443 } else {
444 if (dev->rxnumevt) { /* disable FIFO */
445 if (dev->version == MCASP_VERSION_3)
446 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
447 FIFO_ENABLE);
448 else
449 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
450 FIFO_ENABLE);
451 }
452 mcasp_stop_rx(dev);
453 }
454 }
456 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
457 unsigned int fmt)
458 {
459 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
460 void __iomem *base = dev->base;
462 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
463 case SND_SOC_DAIFMT_CBS_CFS:
464 /* codec is clock and frame slave */
465 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
466 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
468 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
469 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
471 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
472 ACLKX | AHCLKX | AFSX);
473 break;
474 case SND_SOC_DAIFMT_CBM_CFS:
475 /* codec is clock master and frame slave */
476 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
477 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
479 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
480 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
482 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
483 ACLKX | ACLKR);
484 mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
485 AFSX | AFSR);
486 break;
487 case SND_SOC_DAIFMT_CBM_CFM:
488 /* codec is clock and frame master */
489 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
490 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
492 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
493 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
495 mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
496 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
497 break;
499 default:
500 return -EINVAL;
501 }
503 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
504 case SND_SOC_DAIFMT_IB_NF:
505 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
506 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
508 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
509 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
510 break;
512 case SND_SOC_DAIFMT_NB_IF:
513 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
514 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
516 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
517 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
518 break;
520 case SND_SOC_DAIFMT_IB_IF:
521 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
522 mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
524 mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
525 mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
526 break;
528 case SND_SOC_DAIFMT_NB_NF:
529 mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
530 mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
532 mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
533 mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
534 break;
536 default:
537 return -EINVAL;
538 }
540 return 0;
541 }
543 static int davinci_config_channel_size(struct davinci_audio_dev *dev,
544 int channel_size)
545 {
546 u32 fmt = 0;
547 u32 mask, rotate;
549 switch (channel_size) {
550 case DAVINCI_AUDIO_WORD_8:
551 fmt = 0x03;
552 rotate = 6;
553 mask = 0x000000ff;
554 break;
556 case DAVINCI_AUDIO_WORD_12:
557 fmt = 0x05;
558 rotate = 5;
559 mask = 0x00000fff;
560 break;
562 case DAVINCI_AUDIO_WORD_16:
563 fmt = 0x07;
564 rotate = 4;
565 mask = 0x0000ffff;
566 break;
568 case DAVINCI_AUDIO_WORD_20:
569 fmt = 0x09;
570 rotate = 3;
571 mask = 0x000fffff;
572 break;
574 case DAVINCI_AUDIO_WORD_24:
575 fmt = 0x0B;
576 rotate = 2;
577 mask = 0x00ffffff;
578 break;
580 case DAVINCI_AUDIO_WORD_28:
581 fmt = 0x0D;
582 rotate = 1;
583 mask = 0x0fffffff;
584 break;
586 case DAVINCI_AUDIO_WORD_32:
587 fmt = 0x0F;
588 rotate = 0;
589 mask = 0xffffffff;
590 break;
592 default:
593 return -EINVAL;
594 }
596 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
597 RXSSZ(fmt), RXSSZ(0x0F));
598 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
599 TXSSZ(fmt), TXSSZ(0x0F));
600 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXROT(rotate),
601 TXROT(7));
602 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXROT(rotate),
603 RXROT(7));
604 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
605 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, mask);
607 return 0;
608 }
610 static void davinci_hw_common_param(struct davinci_audio_dev *dev, int stream)
611 {
612 int i;
613 u8 tx_ser = 0;
614 u8 rx_ser = 0;
616 /* Default configuration */
617 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
619 /* All PINS as McASP */
620 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
622 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
623 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
624 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
625 TXDATADMADIS);
626 } else {
627 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
628 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
629 RXDATADMADIS);
630 }
632 for (i = 0; i < dev->num_serializer; i++) {
633 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
634 dev->serial_dir[i]);
635 if (dev->serial_dir[i] == TX_MODE) {
636 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
637 AXR(i));
638 tx_ser++;
639 } else if (dev->serial_dir[i] == RX_MODE) {
640 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
641 AXR(i));
642 rx_ser++;
643 }
644 }
646 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
647 if (dev->txnumevt * tx_ser > 64)
648 dev->txnumevt = 1;
650 if (dev->version == MCASP_VERSION_3) {
651 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
652 NUMDMA_MASK);
653 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
654 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
655 } else {
656 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
657 tx_ser, NUMDMA_MASK);
658 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
659 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
660 }
661 }
663 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
664 if (dev->rxnumevt * rx_ser > 64)
665 dev->rxnumevt = 1;
667 if (dev->version == MCASP_VERSION_3) {
668 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
669 NUMDMA_MASK);
670 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
671 ((dev->rxnumevt * rx_ser) << 8),
672 NUMEVT_MASK);
673 } else {
674 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
675 rx_ser, NUMDMA_MASK);
676 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
677 ((dev->rxnumevt * rx_ser) << 8),
678 NUMEVT_MASK);
679 }
680 }
681 }
683 static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
684 {
685 int i, active_slots;
686 u32 mask = 0;
688 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
689 for (i = 0; i < active_slots; i++)
690 mask |= (1 << i);
692 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
694 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
695 /* bit stream is MSB first with no delay */
696 /* DSP_B mode */
697 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
698 AHCLKXE);
699 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
700 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
702 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
703 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
704 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
705 else
706 printk(KERN_ERR "playback tdm slot %d not supported\n",
707 dev->tdm_slots);
709 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
710 } else {
711 /* bit stream is MSB first with no delay */
712 /* DSP_B mode */
713 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
714 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
715 AHCLKRE);
716 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
718 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
719 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
720 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
721 else
722 printk(KERN_ERR "capture tdm slot %d not supported\n",
723 dev->tdm_slots);
725 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
726 }
727 }
729 /* S/PDIF */
730 static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
731 {
732 /* Set the PDIR for Serialiser as output */
733 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AFSX);
735 /* TXMASK for 24 bits */
736 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, 0x00FFFFFF);
738 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
739 and LSB first */
740 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
741 TXROT(6) | TXSSZ(15));
743 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
744 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
745 AFSXE | FSXMOD(0x180));
747 /* Set the TX tdm : for all the slots */
748 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
750 /* Set the TX clock controls : div = 1 and internal */
751 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
752 ACLKXE | TX_ASYNC);
754 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
756 /* Only 44100 and 48000 are valid, both have the same setting */
757 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
759 /* Enable the DIT */
760 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
761 }
763 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
764 struct snd_pcm_hw_params *params,
765 struct snd_soc_dai *cpu_dai)
766 {
767 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
768 struct davinci_pcm_dma_params *dma_params =
769 &dev->dma_params[substream->stream];
770 int word_length;
771 u8 fifo_level;
773 davinci_hw_common_param(dev, substream->stream);
774 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
775 fifo_level = dev->txnumevt;
776 else
777 fifo_level = dev->rxnumevt;
779 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
780 davinci_hw_dit_param(dev);
781 else
782 davinci_hw_param(dev, substream->stream);
784 switch (params_format(params)) {
785 case SNDRV_PCM_FORMAT_U8:
786 case SNDRV_PCM_FORMAT_S8:
787 dma_params->data_type = 1;
788 word_length = DAVINCI_AUDIO_WORD_8;
789 break;
791 case SNDRV_PCM_FORMAT_U16_LE:
792 case SNDRV_PCM_FORMAT_S16_LE:
793 dma_params->data_type = 2;
794 word_length = DAVINCI_AUDIO_WORD_16;
795 break;
797 case SNDRV_PCM_FORMAT_U32_LE:
798 case SNDRV_PCM_FORMAT_S32_LE:
799 dma_params->data_type = 4;
800 word_length = DAVINCI_AUDIO_WORD_32;
801 break;
803 default:
804 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
805 return -EINVAL;
806 }
808 if (dev->version == MCASP_VERSION_2 && !fifo_level)
809 dma_params->acnt = 4;
810 else
811 dma_params->acnt = dma_params->data_type;
813 dma_params->fifo_level = fifo_level;
814 davinci_config_channel_size(dev, word_length);
816 return 0;
817 }
819 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
820 int cmd, struct snd_soc_dai *cpu_dai)
821 {
822 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
823 int ret = 0;
825 switch (cmd) {
826 case SNDRV_PCM_TRIGGER_RESUME:
827 case SNDRV_PCM_TRIGGER_START:
828 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
829 if (!dev->clk_active) {
830 clk_enable(dev->clk);
831 dev->clk_active = 1;
832 }
833 davinci_mcasp_start(dev, substream->stream);
834 break;
836 case SNDRV_PCM_TRIGGER_SUSPEND:
837 davinci_mcasp_stop(dev, substream->stream);
838 if (dev->clk_active) {
839 clk_disable(dev->clk);
840 dev->clk_active = 0;
841 }
843 break;
845 case SNDRV_PCM_TRIGGER_STOP:
846 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
847 davinci_mcasp_stop(dev, substream->stream);
848 break;
850 default:
851 ret = -EINVAL;
852 }
854 return ret;
855 }
857 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
858 struct snd_soc_dai *dai)
859 {
860 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
862 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
863 return 0;
864 }
866 static struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
867 .startup = davinci_mcasp_startup,
868 .trigger = davinci_mcasp_trigger,
869 .hw_params = davinci_mcasp_hw_params,
870 .set_fmt = davinci_mcasp_set_dai_fmt,
872 };
874 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
875 SNDRV_PCM_FMTBIT_U8 | \
876 SNDRV_PCM_FMTBIT_S16_LE | \
877 SNDRV_PCM_FMTBIT_U16_LE | \
878 SNDRV_PCM_FMTBIT_S32_LE | \
879 SNDRV_PCM_FMTBIT_U32_LE)
881 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
882 {
883 .name = "davinci-mcasp.0",
884 .playback = {
885 .channels_min = 2,
886 .channels_max = 2,
887 .rates = DAVINCI_MCASP_RATES,
888 .formats = DAVINCI_MCASP_PCM_FMTS,
889 },
890 .capture = {
891 .channels_min = 2,
892 .channels_max = 2,
893 .rates = DAVINCI_MCASP_RATES,
894 .formats = DAVINCI_MCASP_PCM_FMTS,
895 },
896 .ops = &davinci_mcasp_dai_ops,
898 },
899 {
900 "davinci-mcasp.1",
901 .playback = {
902 .channels_min = 1,
903 .channels_max = 384,
904 .rates = DAVINCI_MCASP_RATES,
905 .formats = DAVINCI_MCASP_PCM_FMTS,
906 },
907 .ops = &davinci_mcasp_dai_ops,
908 },
910 };
912 static int davinci_mcasp_probe(struct platform_device *pdev)
913 {
914 struct davinci_pcm_dma_params *dma_data;
915 struct resource *mem, *ioarea, *res;
916 struct snd_platform_data *pdata;
917 struct davinci_audio_dev *dev;
918 int ret = 0;
920 dev = kzalloc(sizeof(struct davinci_audio_dev), GFP_KERNEL);
921 if (!dev)
922 return -ENOMEM;
924 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
925 if (!mem) {
926 dev_err(&pdev->dev, "no mem resource?\n");
927 ret = -ENODEV;
928 goto err_release_data;
929 }
931 ioarea = request_mem_region(mem->start,
932 resource_size(mem), pdev->name);
933 if (!ioarea) {
934 dev_err(&pdev->dev, "Audio region already claimed\n");
935 ret = -EBUSY;
936 goto err_release_data;
937 }
939 pdata = pdev->dev.platform_data;
940 dev->clk = clk_get(&pdev->dev, NULL);
941 if (IS_ERR(dev->clk)) {
942 ret = -ENODEV;
943 goto err_release_region;
944 }
946 clk_enable(dev->clk);
947 dev->clk_active = 1;
949 dev->base = ioremap(mem->start, resource_size(mem));
950 if (!dev->base) {
951 dev_err(&pdev->dev, "ioremap failed\n");
952 ret = -ENOMEM;
953 goto err_release_clk;
954 }
956 dev->op_mode = pdata->op_mode;
957 dev->tdm_slots = pdata->tdm_slots;
958 dev->num_serializer = pdata->num_serializer;
959 dev->serial_dir = pdata->serial_dir;
960 dev->codec_fmt = pdata->codec_fmt;
961 dev->version = pdata->version;
962 dev->txnumevt = pdata->txnumevt;
963 dev->rxnumevt = pdata->rxnumevt;
965 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
966 dma_data->asp_chan_q = pdata->asp_chan_q;
967 dma_data->ram_chan_q = pdata->ram_chan_q;
968 dma_data->sram_size = pdata->sram_size_playback;
969 if (dev->version == MCASP_VERSION_3)
970 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset);
971 else
972 dma_data->dma_addr = (dma_addr_t) (pdata->tx_dma_offset +
973 mem->start);
975 /* first TX, then RX */
976 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
977 if (!res) {
978 dev_err(&pdev->dev, "no DMA resource\n");
979 ret = -ENODEV;
980 goto err_iounmap;
981 }
983 dma_data->channel = res->start;
985 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
986 dma_data->asp_chan_q = pdata->asp_chan_q;
987 dma_data->ram_chan_q = pdata->ram_chan_q;
988 dma_data->sram_size = pdata->sram_size_capture;
989 if (dev->version == MCASP_VERSION_3)
990 dma_data->dma_addr = (dma_addr_t) (pdata->rx_dma_offset);
991 else
992 dma_data->dma_addr = (dma_addr_t)(pdata->rx_dma_offset +
993 mem->start);
995 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
996 if (!res) {
997 dev_err(&pdev->dev, "no DMA resource\n");
998 ret = -ENODEV;
999 goto err_iounmap;
1000 }
1002 dma_data->channel = res->start;
1003 dev_set_drvdata(&pdev->dev, dev);
1004 ret = snd_soc_register_dai(&pdev->dev, &davinci_mcasp_dai[pdata->op_mode]);
1006 if (ret != 0)
1007 goto err_iounmap;
1008 return 0;
1010 err_iounmap:
1011 iounmap(dev->base);
1012 err_release_clk:
1013 clk_disable(dev->clk);
1014 clk_put(dev->clk);
1015 err_release_region:
1016 release_mem_region(mem->start, resource_size(mem));
1017 err_release_data:
1018 kfree(dev);
1020 return ret;
1021 }
1023 static int davinci_mcasp_remove(struct platform_device *pdev)
1024 {
1025 struct davinci_audio_dev *dev = dev_get_drvdata(&pdev->dev);
1026 struct resource *mem;
1028 snd_soc_unregister_dai(&pdev->dev);
1029 clk_disable(dev->clk);
1030 clk_put(dev->clk);
1031 dev->clk = NULL;
1033 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1034 release_mem_region(mem->start, resource_size(mem));
1036 kfree(dev);
1038 return 0;
1039 }
1041 static struct platform_driver davinci_mcasp_driver = {
1042 .probe = davinci_mcasp_probe,
1043 .remove = davinci_mcasp_remove,
1044 .driver = {
1045 .name = "davinci-mcasp",
1046 .owner = THIS_MODULE,
1047 },
1048 };
1050 static int __init davinci_mcasp_init(void)
1051 {
1052 return platform_driver_register(&davinci_mcasp_driver);
1053 }
1054 module_init(davinci_mcasp_init);
1056 static void __exit davinci_mcasp_exit(void)
1057 {
1058 platform_driver_unregister(&davinci_mcasp_driver);
1059 }
1060 module_exit(davinci_mcasp_exit);
1062 MODULE_AUTHOR("Steve Chen");
1063 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1064 MODULE_LICENSE("GPL");