index d2618b6dcb010417889f4d7e51227f0efc7bf68a..588917333ca3ea090a1175aa15f15c4fdb88542b 100644 (file)
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/input/matrix_keypad.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <plat/mmc.h>
#include "board-flash.h"
+#include "cpuidle33xx.h"
#include "mux.h"
#include "devices.h"
#include "hsmmc.h"
/* TSc controller */
#include <linux/input/ti_tscadc.h>
+#include <linux/lis3lv02d.h>
static struct resource tsc_resources[] = {
[0] = {
#define GP_EVM_REV_IS_1_1A 0x2
#define GP_EVM_REV_IS_UNKNOWN 0xFF
static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
+unsigned int gigabit_enable = 1;
#define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */
#define EEPROM_NO_OF_MAC_ADDR 3
{NULL, 0},
};
+static struct pinmux_config d_can_gp_pin_mux[] = {
+ {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
+ {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
+
+static struct pinmux_config d_can_ia_pin_mux[] = {
+ {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
+ {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
+
+/* Module pin mux for uart2 */
+static struct pinmux_config uart2_pin_mux[] = {
+ {"spi0_sclk.uart2_rxd", OMAP_MUX_MODE1 | AM33XX_SLEWCTRL_SLOW |
+ AM33XX_PIN_INPUT_PULLUP},
+ {"spi0_d0.uart2_txd", OMAP_MUX_MODE1 | AM33XX_PULL_UP |
+ AM33XX_PULL_DISA |
+ AM33XX_SLEWCTRL_SLOW},
+ {NULL, 0},
+};
+
+
/*
* @pin_mux - single module pin-mux structure which defines pin-mux
* details for all its pins.
}
+/* Matrix GPIO Keypad Support for profile-0 only: TODO */
+
+/* pinmux for keypad device */
+static struct pinmux_config matrix_keypad_pin_mux[] = {
+ {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a6.gpio1_22", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {NULL, 0},
+};
+
+/* Keys mapping */
+static const uint32_t am335x_evm_matrix_keys[] = {
+ KEY(0, 0, KEY_MENU),
+ KEY(1, 0, KEY_BACK),
+ KEY(2, 0, KEY_LEFT),
+
+ KEY(0, 1, KEY_RIGHT),
+ KEY(1, 1, KEY_ENTER),
+ KEY(2, 1, KEY_DOWN),
+};
+
+const struct matrix_keymap_data am335x_evm_keymap_data = {
+ .keymap = am335x_evm_matrix_keys,
+ .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
+};
+
+static const unsigned int am335x_evm_keypad_row_gpios[] = {
+ GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
+};
+
+static const unsigned int am335x_evm_keypad_col_gpios[] = {
+ GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
+};
+
+static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
+ .keymap_data = &am335x_evm_keymap_data,
+ .row_gpios = am335x_evm_keypad_row_gpios,
+ .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
+ .col_gpios = am335x_evm_keypad_col_gpios,
+ .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
+ .active_low = false,
+ .debounce_ms = 5,
+ .col_scan_delay_us = 2,
+};
+
+static struct platform_device am335x_evm_keyboard = {
+ .name = "matrix-keypad",
+ .id = -1,
+ .dev = {
+ .platform_data = &am335x_evm_keypad_platform_data,
+ },
+};
+
+static void matrix_keypad_init(int evm_id, int profile)
+{
+ int err;
+
+ setup_pin_mux(matrix_keypad_pin_mux);
+ err = platform_device_register(&am335x_evm_keyboard);
+ if (err) {
+ pr_err("failed to register matrix keypad (2x3) device\n");
+ }
+}
+
+
+/* pinmux for keypad device */
+static struct pinmux_config volume_keys_pin_mux[] = {
+ {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {NULL, 0},
+};
+
+/* Configure GPIOs for Volume Keys */
+static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
+ {
+ .code = KEY_VOLUMEUP,
+ .gpio = GPIO_TO_PIN(0, 2),
+ .active_low = true,
+ .desc = "volume-up",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+ {
+ .code = KEY_VOLUMEDOWN,
+ .gpio = GPIO_TO_PIN(0, 3),
+ .active_low = true,
+ .desc = "volume-down",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+};
+
+static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
+ .buttons = am335x_evm_volume_gpio_buttons,
+ .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
+};
+
+static struct platform_device am335x_evm_volume_keys = {
+ .name = "gpio-keys",
+ .id = -1,
+ .dev = {
+ .platform_data = &am335x_evm_volume_gpio_key_info,
+ },
+};
+
+static void volume_keys_init(int evm_id, int profile)
+{
+ int err;
+
+ setup_pin_mux(volume_keys_pin_mux);
+ err = platform_device_register(&am335x_evm_volume_keys);
+ if (err)
+ pr_err("failed to register matrix keypad (2x3) device\n");
+}
+
/*
* @evm_id - evm id which needs to be configured
* @dev_cfg - single evm structure which includes
{NULL, 0},
};
+/* pinmux for profibus */
+static struct pinmux_config profibus_pin_mux[] = {
+ {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
+ {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
+ {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+};
+
/* Module pin mux for eCAP0 */
static struct pinmux_config ecap0_pin_mux[] = {
{"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
#define AM335XEVM_WLAN_PMENA_GPIO GPIO_TO_PIN(1, 30)
#define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17)
-#define AM335XEVM_BT_ENABLE_GPIO GPIO_TO_PIN(1, 31)
struct wl12xx_platform_data am335xevm_wlan_data = {
.irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
- .board_ref_clock = WL12XX_REFCLOCK_26, /* 26 MHz */
- .board_tcxo_clock = WL12XX_REFCLOCK_26, /* 26 MHz */
+ .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
};
/* Module pin mux for wlan and bluetooth */
{NULL, 0},
};
-static struct pinmux_config wl12xx_pin_mux[] = {
+static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
+ {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+ };
+
+static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
{"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
{"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
{"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
return;
}
+/* setup uart2 */
+static void uart2_init(int evm_id, int profile)
+{
+ setup_pin_mux(uart2_pin_mux);
+ return;
+}
+
/* NAND partition information */
static struct mtd_partition am335x_nand_partitions[] = {
/* All the partition sizes are listed in terms of NAND block size */
ARRAY_SIZE(am335x_nand_partitions), 0, 0);
}
+static struct lis3lv02d_platform_data lis331dlh_pdata = {
+ .click_flags = LIS3_CLICK_SINGLE_X |
+ LIS3_CLICK_SINGLE_Y |
+ LIS3_CLICK_SINGLE_Z,
+ .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
+ LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
+ LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
+ .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
+ .wakeup_thresh = 10,
+ .click_thresh_x = 10,
+ .click_thresh_y = 10,
+ .click_thresh_z = 10,
+ .g_range = 2,
+ .st_min_limits[0] = 120,
+ .st_min_limits[1] = 120,
+ .st_min_limits[2] = 140,
+ .st_max_limits[0] = 550,
+ .st_max_limits[1] = 550,
+ .st_max_limits[2] = 750,
+};
+
static struct i2c_board_info am335x_i2c_boardinfo1[] = {
{
I2C_BOARD_INFO("tlv320aic3x", 0x1b),
},
+ {
+ I2C_BOARD_INFO("lis331dlh", 0x18),
+ .platform_data = &lis331dlh_pdata,
+ },
+ {
+ I2C_BOARD_INFO("tsl2550", 0x39),
+ },
+ {
+ I2C_BOARD_INFO("tmp275", 0x48),
+ },
};
static void i2c1_init(int evm_id, int profile)
static void wl12xx_bluetooth_enable(void)
{
- int status = gpio_request(AM335XEVM_BT_ENABLE_GPIO, "bt_en\n");
+ int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
+ "bt_en\n");
if (status < 0)
pr_err("Failed to request gpio for bt_enable");
- pr_info("Enable bluetooth...\n");
- gpio_direction_output(AM335XEVM_BT_ENABLE_GPIO, 0);
- msleep(1);
- gpio_set_value(AM335XEVM_BT_ENABLE_GPIO, 1);
+ pr_info("Configure Bluetooth Enable pin...\n");
+ gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
}
static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
{
- if (on)
- gpio_set_value(AM335XEVM_WLAN_PMENA_GPIO, 1);
+ if (on) {
+ gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
+ mdelay(70);
+ }
else
- gpio_set_value(AM335XEVM_WLAN_PMENA_GPIO, 0);
+ gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
return 0;
}
struct omap_mmc_platform_data *pdata;
int ret;
+ /* Register WLAN and BT enable pins based on the evm board revision */
+ if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
+ am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
+ am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
+ }
+ else {
+ am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
+ am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
+ }
+
wl12xx_bluetooth_enable();
if (wl12xx_set_platform_data(&am335xevm_wlan_data))
goto out;
}
- ret = gpio_request_one(AM335XEVM_WLAN_PMENA_GPIO, GPIOF_OUT_INIT_LOW,
- "wlan_en");
+ ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
+ GPIOF_OUT_INIT_LOW, "wlan_en");
if (ret) {
pr_err("Error requesting wlan enable gpio: %d\n", ret);
goto out;
}
- setup_pin_mux(wl12xx_pin_mux);
+ if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
+ setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
+ else
+ setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
pdata->slots[0].set_power = wl12xx_set_power;
out:
return;
}
+static void d_can_init(int evm_id, int profile)
+{
+ switch (evm_id) {
+ case IND_AUT_MTR_EVM:
+ if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
+ setup_pin_mux(d_can_ia_pin_mux);
+ /* Instance Zero */
+ am33xx_d_can_init(0);
+ }
+ break;
+ case GEN_PURP_EVM:
+ if (profile == PROFILE_1) {
+ setup_pin_mux(d_can_gp_pin_mux);
+ /* Instance One */
+ am33xx_d_can_init(1);
+ }
+ break;
+ default:
+ break;
+ }
+}
+
static void mmc0_init(int evm_id, int profile)
{
setup_pin_mux(mmc0_pin_mux);
}
#endif
+static void profibus_init(int evm_id, int profile)
+{
+ setup_pin_mux(profibus_pin_mux);
+ return;
+}
/* Low-Cost EVM */
static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
{usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{evm_nand_init, DEV_ON_DGHTR_BRD,
(PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
- {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
+ {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
{mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
{mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
{mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
{uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
PROFILE_5)},
{wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
+ {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1},
+ {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
+ {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0},
+ {uart2_init, DEV_ON_DGHTR_BRD, PROFILE_3},
{NULL, 0, 0},
};
{mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
{usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
{evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
{spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
{uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
* information is required for configuring phy address and hence
* should be call only after board detection
*/
- am33xx_cpsw_init();
+ am33xx_cpsw_init(gigabit_enable);
return;
out:
* information is required for configuring phy address and hence
* should be call only after board detection
*/
- am33xx_cpsw_init();
+
+ am33xx_cpsw_init(gigabit_enable);
}
static struct at24_platform_data am335x_daughter_board_eeprom_info = {
setup_pin_mux(clkout2_pin_mux);
}
+void __iomem * __init am33xx_get_mem_ctlr(void)
+{
+ void __iomem *am33xx_emif_base;
+
+ am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
+
+ if (!am33xx_emif_base)
+ pr_warning("%s: Unable to map DDR2 controller", __func__);
+
+ return am33xx_emif_base;
+}
+
+static struct resource am33xx_cpuidle_resources[] = {
+ {
+ .start = AM33XX_EMIF0_BASE,
+ .end = AM33XX_EMIF0_BASE + SZ_32K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+/* AM33XX devices support DDR2 power down */
+static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
+ .ddr2_pdown = 1,
+};
+
+static struct platform_device am33xx_cpuidle_device = {
+ .name = "cpuidle-am33xx",
+ .num_resources = ARRAY_SIZE(am33xx_cpuidle_resources),
+ .resource = am33xx_cpuidle_resources,
+ .dev = {
+ .platform_data = &am33xx_cpuidle_pdata,
+ },
+};
+
+static void __init am33xx_cpuidle_init(void)
+{
+ int ret;
+
+ am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
+
+ ret = platform_device_register(&am33xx_cpuidle_device);
+
+ if (ret)
+ pr_warning("AM33XX cpuidle registration failed\n");
+
+}
+
static void __init am335x_evm_init(void)
{
+ am33xx_cpuidle_init();
am33xx_mux_init(board_mux);
omap_serial_init();
am335x_rtc_init();
usb_musb_init(&musb_board_data);
omap_board_config = am335x_evm_config;
omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
+ /* Create an alias for icss clock */
+ if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
+ pr_err("failed to create an alias: icss_uart_gclk --> pruss\n");
+ /* Create an alias for gfx/sgx clock */
+ if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
+ pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n");
}
static void __init am335x_evm_map_io(void)