index 2b550fb398ae1767b2393d45e14fea1dccec7970..cd8ca3ab958c856b2a12735f1f81dfe95aae7158 100644 (file)
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/i2c/at24.h>
+#include <linux/phy.h>
#include <linux/gpio.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/input/matrix_keypad.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/err.h>
+#include <linux/wl12xx.h>
+#include <linux/ethtool.h>
/* LCD controller is similar to DA850 */
#include <video/da8xx-fb.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+#include <asm/hardware/asp.h>
#include <plat/irqs.h>
#include <plat/board.h>
#include <plat/common.h>
#include <plat/lcdc.h>
#include <plat/usb.h>
+#include <plat/mmc.h>
+
+#include "board-flash.h"
+#include "mux.h"
+#include "devices.h"
+#include "hsmmc.h"
+
+/* Convert GPIO signal to GPIO pin number */
+#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
+
+/* TLK PHY IDs */
+#define TLK110_PHY_ID 0x2000A201
+#define TLK110_PHY_MASK 0xfffffff0
+
+/* BBB PHY IDs */
+#define BBB_PHY_ID 0x7c0f1
+#define BBB_PHY_MASK 0xfffffffe
+
+/* TLK110 PHY register offsets */
+#define TLK110_COARSEGAIN_REG 0x00A3
+#define TLK110_LPFHPF_REG 0x00AC
+#define TLK110_SPAREANALOG_REG 0x00B9
+#define TLK110_VRCR_REG 0x00D0
+#define TLK110_SETFFE_REG 0x0107
+#define TLK110_FTSP_REG 0x0154
+#define TLK110_ALFATPIDL_REG 0x002A
+#define TLK110_PSCOEF21_REG 0x0096
+#define TLK110_PSCOEF3_REG 0x0097
+#define TLK110_ALFAFACTOR1_REG 0x002C
+#define TLK110_ALFAFACTOR2_REG 0x0023
+#define TLK110_CFGPS_REG 0x0095
+#define TLK110_FTSPTXGAIN_REG 0x0150
+#define TLK110_SWSCR3_REG 0x000B
+#define TLK110_SCFALLBACK_REG 0x0040
+#define TLK110_PHYRCR_REG 0x001F
+
+/* TLK110 register writes values */
+#define TLK110_COARSEGAIN_VAL 0x0000
+#define TLK110_LPFHPF_VAL 0x8000
+#define TLK110_SPANALOG_VAL 0x0000
+#define TLK110_VRCR_VAL 0x0008
+#define TLK110_SETFFE_VAL 0x0605
+#define TLK110_FTSP_VAL 0x0255
+#define TLK110_ALFATPIDL_VAL 0x7998
+#define TLK110_PSCOEF21_VAL 0x3A20
+#define TLK110_PSCOEF3_VAL 0x003F
+#define TLK110_ALFACTOR1_VAL 0xFF80
+#define TLK110_ALFACTOR2_VAL 0x021C
+#define TLK110_CFGPS_VAL 0x0000
+#define TLK110_FTSPTXGAIN_VAL 0x6A88
+#define TLK110_SWSCR3_VAL 0x0000
+#define TLK110_SCFALLBACK_VAL 0xC11D
+#define TLK110_PHYRCR_VAL 0x4000
+
+#ifdef CONFIG_TLK110_WORKAROUND
+#define am335x_tlk110_phy_init()\
+ do { \
+ phy_register_fixup_for_uid(TLK110_PHY_ID,\
+ TLK110_PHY_MASK,\
+ am335x_tlk110_phy_fixup);\
+ } while (0);
+#else
+#define am335x_tlk110_phy_init() do { } while (0);
+#endif
static const struct display_panel disp_panel = {
WVGA,
/* TSc controller */
#include <linux/input/ti_tscadc.h>
+#include <linux/lis3lv02d.h>
static struct resource tsc_resources[] = {
[0] = {
.resource = tsc_resources,
};
-#include "board-flash.h"
-#include "mux.h"
+static u8 am335x_iis_serializer_direction1[] = {
+ INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE,
+ INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
+ INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
+ INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
+};
+
+static struct snd_platform_data am335x_evm_snd_data1 = {
+ .tx_dma_offset = 0x46400000, /* McASP1 */
+ .rx_dma_offset = 0x46400000,
+ .op_mode = DAVINCI_MCASP_IIS_MODE,
+ .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
+ .tdm_slots = 2,
+ .serial_dir = am335x_iis_serializer_direction1,
+ .asp_chan_q = EVENTQ_2,
+ .version = MCASP_VERSION_3,
+ .txnumevt = 1,
+ .rxnumevt = 1,
+};
+
+static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
+ {
+ .mmc = 1,
+ .caps = MMC_CAP_4_BIT_DATA,
+ .gpio_cd = GPIO_TO_PIN(0, 6),
+ .gpio_wp = GPIO_TO_PIN(3, 18),
+ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
+ },
+ {
+ .mmc = 0, /* will be set at runtime */
+ },
+ {
+ .mmc = 0, /* will be set at runtime */
+ },
+ {} /* Terminator */
+};
+
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
struct am335x_evm_eeprom_config {
u32 header;
u8 name[8];
- u32 version;
+ char version[4];
u8 serial[12];
u8 opt[32];
};
#define GP_EVM_REV_IS_1_1A 0x2
#define GP_EVM_REV_IS_UNKNOWN 0xFF
static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
+unsigned int gigabit_enable = 1;
+
+#define EEPROM_MAC_ADDRESS_OFFSET 60 /* 4+8+4+12+32 */
+#define EEPROM_NO_OF_MAC_ADDR 3
+static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
#define AM335X_EEPROM_HEADER 0xEE3355AA
{NULL, 0},
};
+/* Module pin mux for SPI fash */
+static struct pinmux_config spi0_pin_mux[] = {
+ {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
+ | AM33XX_INPUT_EN},
+ {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
+ | AM33XX_INPUT_EN},
+ {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
+ | AM33XX_INPUT_EN},
+ {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
+ | AM33XX_INPUT_EN},
+ {NULL, 0},
+};
+
+/* Module pin mux for SPI flash */
+static struct pinmux_config spi1_pin_mux[] = {
+ {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
+ | AM33XX_INPUT_EN},
+ {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
+ | AM33XX_PULL_UP | AM33XX_INPUT_EN},
+ {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
+ | AM33XX_INPUT_EN},
+ {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
+ | AM33XX_PULL_UP | AM33XX_INPUT_EN},
+ {NULL, 0},
+};
/* Module pin mux for rgmii1 */
static struct pinmux_config rgmii1_pin_mux[] = {
{NULL, 0},
};
+/* Module pin mux for rmii1 */
+static struct pinmux_config rmii1_pin_mux[] = {
+ {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
+ {NULL, 0},
+};
+
+static struct pinmux_config i2c1_pin_mux[] = {
+ {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
+ AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
+ {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
+ AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
+ {NULL, 0},
+};
+
+/* Module pin mux for mcasp1 */
+static struct pinmux_config mcasp1_pin_mux[] = {
+ {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
+ AM33XX_PIN_INPUT_PULLDOWN},
+ {NULL, 0},
+};
+
+
+/* Module pin mux for mmc0 */
+static struct pinmux_config mmc0_pin_mux[] = {
+ {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
+
+static struct pinmux_config mmc0_no_cd_pin_mux[] = {
+ {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
+ {NULL, 0},
+};
+
+/* Module pin mux for mmc1 */
+static struct pinmux_config mmc1_pin_mux[] = {
+ {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
+
+/* Module pin mux for uart3 */
+static struct pinmux_config uart3_pin_mux[] = {
+ {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
+ {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
+ {NULL, 0},
+};
+
+static struct pinmux_config d_can_gp_pin_mux[] = {
+ {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
+ {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
+
+static struct pinmux_config d_can_ia_pin_mux[] = {
+ {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
+ {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
/*
* @pin_mux - single module pin-mux structure which defines pin-mux
}
+/* Matrix GPIO Keypad Support for profile-0 only: TODO */
+
+/* pinmux for keypad device */
+static struct pinmux_config matrix_keypad_pin_mux[] = {
+ {"gpmc_a5.gpio1_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a6.gpio1_22", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a9.gpio1_25", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"gpmc_a10.gpio1_26", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"gpmc_a11.gpio1_27", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {NULL, 0},
+};
+
+/* Keys mapping */
+static const uint32_t am335x_evm_matrix_keys[] = {
+ KEY(0, 0, KEY_MENU),
+ KEY(1, 0, KEY_BACK),
+ KEY(2, 0, KEY_LEFT),
+
+ KEY(0, 1, KEY_RIGHT),
+ KEY(1, 1, KEY_ENTER),
+ KEY(2, 1, KEY_DOWN),
+};
+
+const struct matrix_keymap_data am335x_evm_keymap_data = {
+ .keymap = am335x_evm_matrix_keys,
+ .keymap_size = ARRAY_SIZE(am335x_evm_matrix_keys),
+};
+
+static const unsigned int am335x_evm_keypad_row_gpios[] = {
+ GPIO_TO_PIN(1, 25), GPIO_TO_PIN(1, 26), GPIO_TO_PIN(1, 27)
+};
+
+static const unsigned int am335x_evm_keypad_col_gpios[] = {
+ GPIO_TO_PIN(1, 21), GPIO_TO_PIN(1, 22)
+};
+
+static struct matrix_keypad_platform_data am335x_evm_keypad_platform_data = {
+ .keymap_data = &am335x_evm_keymap_data,
+ .row_gpios = am335x_evm_keypad_row_gpios,
+ .num_row_gpios = ARRAY_SIZE(am335x_evm_keypad_row_gpios),
+ .col_gpios = am335x_evm_keypad_col_gpios,
+ .num_col_gpios = ARRAY_SIZE(am335x_evm_keypad_col_gpios),
+ .active_low = false,
+ .debounce_ms = 5,
+ .col_scan_delay_us = 2,
+};
+
+static struct platform_device am335x_evm_keyboard = {
+ .name = "matrix-keypad",
+ .id = -1,
+ .dev = {
+ .platform_data = &am335x_evm_keypad_platform_data,
+ },
+};
+
+static void matrix_keypad_init(int evm_id, int profile)
+{
+ int err;
+
+ setup_pin_mux(matrix_keypad_pin_mux);
+ err = platform_device_register(&am335x_evm_keyboard);
+ if (err) {
+ pr_err("failed to register matrix keypad (2x3) device\n");
+ }
+}
+
+
+/* pinmux for keypad device */
+static struct pinmux_config volume_keys_pin_mux[] = {
+ {"spi0_sclk.gpio0_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"spi0_d0.gpio0_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {NULL, 0},
+};
+
+/* Configure GPIOs for Volume Keys */
+static struct gpio_keys_button am335x_evm_volume_gpio_buttons[] = {
+ {
+ .code = KEY_VOLUMEUP,
+ .gpio = GPIO_TO_PIN(0, 2),
+ .active_low = true,
+ .desc = "volume-up",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+ {
+ .code = KEY_VOLUMEDOWN,
+ .gpio = GPIO_TO_PIN(0, 3),
+ .active_low = true,
+ .desc = "volume-down",
+ .type = EV_KEY,
+ .wakeup = 1,
+ },
+};
+
+static struct gpio_keys_platform_data am335x_evm_volume_gpio_key_info = {
+ .buttons = am335x_evm_volume_gpio_buttons,
+ .nbuttons = ARRAY_SIZE(am335x_evm_volume_gpio_buttons),
+};
+
+static struct platform_device am335x_evm_volume_keys = {
+ .name = "gpio-keys",
+ .id = -1,
+ .dev = {
+ .platform_data = &am335x_evm_volume_gpio_key_info,
+ },
+};
+
+static void volume_keys_init(int evm_id, int profile)
+{
+ int err;
+
+ setup_pin_mux(volume_keys_pin_mux);
+ err = platform_device_register(&am335x_evm_volume_keys);
+ if (err)
+ pr_err("failed to register matrix keypad (2x3) device\n");
+}
+
/*
* @evm_id - evm id which needs to be configured
* @dev_cfg - single evm structure which includes
}
}
-/* Convert GPIO signal to GPIO pin number */
-#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
-
#define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7)
/* pinmux for usb0 drvvbus */
{NULL, 0},
};
+/* pinmux for profibus */
+static struct pinmux_config profibus_pin_mux[] = {
+ {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
+ {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
+ {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+};
+
/* Module pin mux for eCAP0 */
static struct pinmux_config ecap0_pin_mux[] = {
{"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
static int backlight_enable;
+#define AM335XEVM_WLAN_PMENA_GPIO GPIO_TO_PIN(1, 30)
+#define AM335XEVM_WLAN_IRQ_GPIO GPIO_TO_PIN(3, 17)
+
+struct wl12xx_platform_data am335xevm_wlan_data = {
+ .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
+ .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
+};
+
+/* Module pin mux for wlan and bluetooth */
+static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
+ {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
+
+static struct pinmux_config uart1_wl12xx_pin_mux[] = {
+ {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
+ {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
+ {NULL, 0},
+};
+
+static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
+ {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+ };
+
+static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
+ {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+ {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+ };
+
static void enable_ecap0(int evm_id, int profile)
{
backlight_enable = true;
return;
}
+static void rmii1_init(int evm_id, int profile)
+{
+ setup_pin_mux(rmii1_pin_mux);
+ return;
+}
+
static void usb0_init(int evm_id, int profile)
{
setup_pin_mux(usb0_pin_mux);
return;
}
+/* setup uart3 */
+static void uart3_init(int evm_id, int profile)
+{
+ setup_pin_mux(uart3_pin_mux);
+ return;
+}
+
/* NAND partition information */
static struct mtd_partition am335x_nand_partitions[] = {
/* All the partition sizes are listed in terms of NAND block size */
},
};
+/* SPI 0/1 Platform Data */
+/* SPI flash information */
+static struct mtd_partition am335x_spi_partitions[] = {
+ /* All the partition sizes are listed in terms of erase size */
+ {
+ .name = "SPL",
+ .offset = 0, /* Offset = 0x0 */
+ .size = SZ_128K,
+ },
+ {
+ .name = "U-Boot",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
+ .size = 2 * SZ_128K,
+ },
+ {
+ .name = "U-Boot Env",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
+ .size = 2 * SZ_4K,
+ },
+ {
+ .name = "Kernel",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x62000 */
+ .size = 28 * SZ_128K,
+ },
+ {
+ .name = "File System",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x3E2000 */
+ .size = MTDPART_SIZ_FULL, /* size ~= 4.1 MiB */
+ }
+};
+
+static const struct flash_platform_data am335x_spi_flash = {
+ .type = "w25q64",
+ .name = "spi_flash",
+ .parts = am335x_spi_partitions,
+ .nr_parts = ARRAY_SIZE(am335x_spi_partitions),
+};
+
+/*
+ * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
+ * So setup Max speed to be less than that of Controller speed
+ */
+static struct spi_board_info am335x_spi0_slave_info[] = {
+ {
+ .modalias = "m25p80",
+ .platform_data = &am335x_spi_flash,
+ .irq = -1,
+ .max_speed_hz = 24000000,
+ .bus_num = 1,
+ .chip_select = 0,
+ },
+};
+
+static struct spi_board_info am335x_spi1_slave_info[] = {
+ {
+ .modalias = "m25p80",
+ .platform_data = &am335x_spi_flash,
+ .irq = -1,
+ .max_speed_hz = 12000000,
+ .bus_num = 2,
+ .chip_select = 0,
+ },
+};
+
static void evm_nand_init(int evm_id, int profile)
{
setup_pin_mux(nand_pin_mux);
ARRAY_SIZE(am335x_nand_partitions), 0, 0);
}
+static struct lis3lv02d_platform_data lis331dlh_pdata = {
+ .click_flags = LIS3_CLICK_SINGLE_X |
+ LIS3_CLICK_SINGLE_Y |
+ LIS3_CLICK_SINGLE_Z,
+ .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
+ LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
+ LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
+ .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
+ .wakeup_thresh = 10,
+ .click_thresh_x = 10,
+ .click_thresh_y = 10,
+ .click_thresh_z = 10,
+ .g_range = 2,
+ .st_min_limits[0] = 120,
+ .st_min_limits[1] = 120,
+ .st_min_limits[2] = 140,
+ .st_max_limits[0] = 550,
+ .st_max_limits[1] = 550,
+ .st_max_limits[2] = 750,
+};
+
+static struct i2c_board_info am335x_i2c_boardinfo1[] = {
+ {
+ I2C_BOARD_INFO("tlv320aic3x", 0x1b),
+ },
+ {
+ I2C_BOARD_INFO("lis331dlh", 0x18),
+ .platform_data = &lis331dlh_pdata,
+ },
+ {
+ I2C_BOARD_INFO("tsl2550", 0x39),
+ },
+ {
+ I2C_BOARD_INFO("tmp275", 0x48),
+ },
+};
+
+static void i2c1_init(int evm_id, int profile)
+{
+ setup_pin_mux(i2c1_pin_mux);
+ omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
+ ARRAY_SIZE(am335x_i2c_boardinfo1));
+ return;
+}
+
+/* Setup McASP 1 */
+static void mcasp1_init(int evm_id, int profile)
+{
+ /* Configure McASP */
+ setup_pin_mux(mcasp1_pin_mux);
+ am335x_register_mcasp1(&am335x_evm_snd_data1);
+ return;
+}
+
+static void mmc1_init(int evm_id, int profile)
+{
+ setup_pin_mux(mmc1_pin_mux);
+
+ am335x_mmc[1].mmc = 2;
+ am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
+ am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
+ am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
+ am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
+
+ /* mmc will be initialized when mmc0_init is called */
+ return;
+}
+
+static void mmc2_wl12xx_init(int evm_id, int profile)
+{
+ setup_pin_mux(mmc2_wl12xx_pin_mux);
+
+ am335x_mmc[1].mmc = 3;
+ am335x_mmc[1].name = "wl1271";
+ am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
+ | MMC_PM_KEEP_POWER;
+ am335x_mmc[1].nonremovable = true;
+ am335x_mmc[1].gpio_cd = -EINVAL;
+ am335x_mmc[1].gpio_wp = -EINVAL;
+ am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
+
+ /* mmc will be initialized when mmc0_init is called */
+ return;
+}
+
+static void uart1_wl12xx_init(int evm_id, int profile)
+{
+ setup_pin_mux(uart1_wl12xx_pin_mux);
+}
+
+static void wl12xx_bluetooth_enable(void)
+{
+ int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
+ "bt_en\n");
+ if (status < 0)
+ pr_err("Failed to request gpio for bt_enable");
+
+ pr_info("Configure Bluetooth Enable pin...\n");
+ gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
+}
+
+static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
+{
+ if (on) {
+ gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
+ mdelay(70);
+ }
+ else
+ gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
+
+ return 0;
+}
+
+static void wl12xx_init(int evm_id, int profile)
+{
+ struct device *dev;
+ struct omap_mmc_platform_data *pdata;
+ int ret;
+
+ /* Register WLAN and BT enable pins based on the evm board revision */
+ if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
+ am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
+ am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
+ }
+ else {
+ am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
+ am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
+ }
+
+ wl12xx_bluetooth_enable();
+
+ if (wl12xx_set_platform_data(&am335xevm_wlan_data))
+ pr_err("error setting wl12xx data\n");
+
+ dev = am335x_mmc[1].dev;
+ if (!dev) {
+ pr_err("wl12xx mmc device initialization failed\n");
+ goto out;
+ }
+
+ pdata = dev->platform_data;
+ if (!pdata) {
+ pr_err("Platfrom data of wl12xx device not set\n");
+ goto out;
+ }
+
+ ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
+ GPIOF_OUT_INIT_LOW, "wlan_en");
+ if (ret) {
+ pr_err("Error requesting wlan enable gpio: %d\n", ret);
+ goto out;
+ }
+
+ if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
+ setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
+ else
+ setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
+
+ pdata->slots[0].set_power = wl12xx_set_power;
+out:
+ return;
+}
+
+static void d_can_init(int evm_id, int profile)
+{
+ switch (evm_id) {
+ case IND_AUT_MTR_EVM:
+ if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
+ setup_pin_mux(d_can_ia_pin_mux);
+ /* Instance Zero */
+ am33xx_d_can_init(0);
+ }
+ break;
+ case GEN_PURP_EVM:
+ if (profile == PROFILE_1) {
+ setup_pin_mux(d_can_gp_pin_mux);
+ /* Instance One */
+ am33xx_d_can_init(1);
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+static void mmc0_init(int evm_id, int profile)
+{
+ setup_pin_mux(mmc0_pin_mux);
+
+ omap2_hsmmc_init(am335x_mmc);
+ return;
+}
+
+static void mmc0_no_cd_init(int evm_id, int profile)
+{
+ setup_pin_mux(mmc0_no_cd_pin_mux);
+
+ omap2_hsmmc_init(am335x_mmc);
+ return;
+}
+
+
+/* setup spi0 */
+static void spi0_init(int evm_id, int profile)
+{
+ setup_pin_mux(spi0_pin_mux);
+ spi_register_board_info(am335x_spi0_slave_info,
+ ARRAY_SIZE(am335x_spi0_slave_info));
+ return;
+}
+
+/* setup spi1 */
+static void spi1_init(int evm_id, int profile)
+{
+ setup_pin_mux(spi1_pin_mux);
+ spi_register_board_info(am335x_spi1_slave_info,
+ ARRAY_SIZE(am335x_spi1_slave_info));
+ return;
+}
+
+
+static int beaglebone_phy_fixup(struct phy_device *phydev)
+{
+ phydev->supported &= ~(SUPPORTED_100baseT_Half |
+ SUPPORTED_100baseT_Full);
+
+ return 0;
+}
+
+#ifdef CONFIG_TLK110_WORKAROUND
+static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
+{
+ unsigned int val;
+
+ /* This is done as a workaround to support TLK110 rev1.0 phy */
+ val = phy_read(phydev, TLK110_COARSEGAIN_REG);
+ phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
+
+ val = phy_read(phydev, TLK110_LPFHPF_REG);
+ phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
+
+ val = phy_read(phydev, TLK110_SPAREANALOG_REG);
+ phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
+
+ val = phy_read(phydev, TLK110_VRCR_REG);
+ phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
+
+ val = phy_read(phydev, TLK110_SETFFE_REG);
+ phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
+
+ val = phy_read(phydev, TLK110_FTSP_REG);
+ phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
+
+ val = phy_read(phydev, TLK110_ALFATPIDL_REG);
+ phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
+
+ val = phy_read(phydev, TLK110_PSCOEF21_REG);
+ phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
+
+ val = phy_read(phydev, TLK110_PSCOEF3_REG);
+ phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
+
+ val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
+ phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
+
+ val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
+ phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
+
+ val = phy_read(phydev, TLK110_CFGPS_REG);
+ phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
+
+ val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
+ phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
+
+ val = phy_read(phydev, TLK110_SWSCR3_REG);
+ phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
+
+ val = phy_read(phydev, TLK110_SCFALLBACK_REG);
+ phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
+
+ val = phy_read(phydev, TLK110_PHYRCR_REG);
+ phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
+
+ return 0;
+}
+#endif
+
+static void profibus_init(int evm_id, int profile)
+{
+ setup_pin_mux(profibus_pin_mux);
+ return;
+}
+
/* Low-Cost EVM */
static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
{rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
{usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{evm_nand_init, DEV_ON_DGHTR_BRD,
(PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
+ {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
+ {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
+ {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
+ {mmc2_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
+ PROFILE_5)},
+ {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
+ {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5},
+ {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},
+ {uart1_wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
+ PROFILE_5)},
+ {wl12xx_init, DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
+ {d_can_init, DEV_ON_DGHTR_BRD, PROFILE_1},
+ {matrix_keypad_init, DEV_ON_DGHTR_BRD, PROFILE_0},
+ {volume_keys_init, DEV_ON_DGHTR_BRD, PROFILE_0},
{NULL, 0, 0},
};
{mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
{usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {profibus_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
{evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
+ {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
+ {uart3_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
+ {i2c1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_ALL},
{NULL, 0, 0},
};
{usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
{usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
{evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
+ {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
+ {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {NULL, 0, 0},
+};
+
+/* Beaglebone < Rev A3 */
+static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
+ {rmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {NULL, 0, 0},
+};
+
+/* Beaglebone Rev A3 and after */
+static struct evm_dev_cfg beaglebone_dev_cfg[] = {
+ {mii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
{NULL, 0, 0},
};
_configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
PROFILE_0);
+ /* Fillup global evmid */
+ am33xx_evmid_fillup(IND_AUT_MTR_EVM);
+
+ /* Initialize TLK110 PHY registers for phy version 1.0 */
+ am335x_tlk110_phy_init();
+
+
}
static void setup_ip_phone_evm(void)
_configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
}
+/* BeagleBone < Rev A3 */
+static void setup_beaglebone_old(void)
+{
+ pr_info("The board is a AM335x Beaglebone < Rev A3.\n");
+
+ /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
+ am335x_mmc[0].gpio_wp = -EINVAL;
+
+ _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
+
+ phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
+ beaglebone_phy_fixup);
+}
+
+/* BeagleBone after Rev A3 */
+static void setup_beaglebone(void)
+{
+ pr_info("The board is a AM335x Beaglebone.\n");
+
+ /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
+ am335x_mmc[0].gpio_wp = -EINVAL;
+
+ _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
+}
+
+
static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
{
u8 tmp;
int ret;
char tmp[10];
+ /* 1st get the MAC address from EEPROM */
+ ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
+ EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
+
+ if (ret != sizeof(am335x_mac_addr)) {
+ pr_warning("AM335X: EVM Config read fail: %d\n", ret);
+ return;
+ }
+
+ /* Fillup global mac id */
+ am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
+ &am335x_mac_addr[1][0]);
+
/* get board specific data */
ret = mem_acc->read(mem_acc, (char *)&config, 0, sizeof(config));
if (ret != sizeof(config)) {
goto out;
}
- snprintf(tmp, sizeof(config.name), "%s", config.name);
+ snprintf(tmp, sizeof(config.name) + 1, "%s", config.name);
pr_info("Board name: %s\n", tmp);
- /* only 6 characters of options string used for now */
- snprintf(tmp, 7, "%s", config.opt);
- pr_info("SKU: %s\n", tmp);
-
- if (!strncmp("SKU#00", config.opt, 6))
- setup_low_cost_evm();
- else if (!strncmp("SKU#01", config.opt, 6))
- setup_general_purpose_evm();
- else if (!strncmp("SKU#02", config.opt, 6))
- setup_ind_auto_motor_ctrl_evm();
- else if (!strncmp("SKU#03", config.opt, 6))
- setup_ip_phone_evm();
- else
- goto out;
+ snprintf(tmp, sizeof(config.version) + 1, "%s", config.version);
+ pr_info("Board version: %s\n", tmp);
+ if (!strncmp("A335BONE", config.name, 8)) {
+ daughter_brd_detected = false;
+ if(!strncmp("00A1", config.version, 4) ||
+ !strncmp("00A2", config.version, 4))
+ setup_beaglebone_old();
+ else
+ setup_beaglebone();
+ } else {
+ /* only 6 characters of options string used for now */
+ snprintf(tmp, 7, "%s", config.opt);
+ pr_info("SKU: %s\n", tmp);
+
+ if (!strncmp("SKU#00", config.opt, 6))
+ setup_low_cost_evm();
+ else if (!strncmp("SKU#01", config.opt, 6))
+ setup_general_purpose_evm();
+ else if (!strncmp("SKU#02", config.opt, 6))
+ setup_ind_auto_motor_ctrl_evm();
+ else if (!strncmp("SKU#03", config.opt, 6))
+ setup_ip_phone_evm();
+ else
+ goto out;
+ }
/* Initialize cpsw after board detection is completed as board
* information is required for configuring phy address and hence
* should be call only after board detection
*/
- am33xx_cpsw_init();
+ am33xx_cpsw_init(gigabit_enable);
return;
out:
/*
- * for bring-up assume a full configuration, this should
- * eventually be changed to assume a minimal configuration
+ * If the EEPROM hasn't been programed or an incorrect header
+ * or board name are read, assume this is an old beaglebone board
+ * (< Rev A3)
*/
pr_err("Could not detect any board, falling back to: "
- "General purpose EVM in profile 0 with daughter card connected\n");
- daughter_brd_detected = true;
- setup_general_purpose_evm();
+ "Beaglebone (< Rev A3) with no daughter card connected\n");
+ daughter_brd_detected = false;
+ setup_beaglebone_old();
/* Initialize cpsw after board detection is completed as board
* information is required for configuring phy address and hence
* should be call only after board detection
*/
- am33xx_cpsw_init();
+ am33xx_cpsw_init(gigabit_enable);
}
static struct at24_platform_data am335x_daughter_board_eeprom_info = {
ARRAY_SIZE(am335x_i2c_boardinfo));
}
+static struct resource am335x_rtc_resources[] = {
+ {
+ .start = AM33XX_RTC_BASE,
+ .end = AM33XX_RTC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ { /* timer irq */
+ .start = AM33XX_IRQ_RTC_TIMER,
+ .end = AM33XX_IRQ_RTC_TIMER,
+ .flags = IORESOURCE_IRQ,
+ },
+ { /* alarm irq */
+ .start = AM33XX_IRQ_RTC_ALARM,
+ .end = AM33XX_IRQ_RTC_ALARM,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device am335x_rtc_device = {
+ .name = "omap_rtc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(am335x_rtc_resources),
+ .resource = am335x_rtc_resources,
+};
+
+static int am335x_rtc_init(void)
+{
+ void __iomem *base;
+ struct clk *clk;
+
+ clk = clk_get(NULL, "rtc_fck");
+ if (IS_ERR(clk)) {
+ pr_err("rtc : Failed to get RTC clock\n");
+ return -1;
+ }
+
+ if (clk_enable(clk)) {
+ pr_err("rtc: Clock Enable Failed\n");
+ return -1;
+ }
+
+ base = ioremap(AM33XX_RTC_BASE, SZ_4K);
+
+ if (WARN_ON(!base))
+ return -ENOMEM;
+
+ /* Unlock the rtc's registers */
+ __raw_writel(0x83e70b13, base + 0x6c);
+ __raw_writel(0x95a4f1e0, base + 0x70);
+
+ /*
+ * Enable the 32K OSc
+ * TODO: Need a better way to handle this
+ * Since we want the clock to be running before mmc init
+ * we need to do it before the rtc probe happens
+ */
+ __raw_writel(0x48, base + 0x54);
+
+ iounmap(base);
+
+ return platform_device_register(&am335x_rtc_device);
+}
+
+/* Enable clkout2 */
+static struct pinmux_config clkout2_pin_mux[] = {
+ {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+};
+
+static void __init clkout2_enable(void)
+{
+ struct clk *ck_32;
+
+ ck_32 = clk_get(NULL, "clkout2_ck");
+ if (IS_ERR(ck_32)) {
+ pr_err("Cannot clk_get ck_32\n");
+ return;
+ }
+
+ clk_enable(ck_32);
+
+ setup_pin_mux(clkout2_pin_mux);
+}
+
static void __init am335x_evm_init(void)
{
am33xx_mux_init(board_mux);
omap_serial_init();
+ am335x_rtc_init();
+ clkout2_enable();
am335x_evm_i2c_init();
omap_sdrc_init(NULL, NULL);
usb_musb_init(&musb_board_data);
omap_board_config = am335x_evm_config;
omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
+ /* Create an alias for icss clock */
+ if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
+ pr_err("failed to create an alias: icss_uart_gclk --> pruss\n");
+ /* Create an alias for gfx/sgx clock */
+ if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
+ pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n");
}
static void __init am335x_evm_map_io(void)
.timer = &omap3_am33xx_timer,
.init_machine = am335x_evm_init,
MACHINE_END
+
+MACHINE_START(AM335XIAEVM, "am335xiaevm")
+ /* Maintainer: Texas Instruments */
+ .atag_offset = 0x100,
+ .map_io = am335x_evm_map_io,
+ .init_irq = ti81xx_init_irq,
+ .init_early = am33xx_init_early,
+ .timer = &omap3_am33xx_timer,
+ .init_machine = am335x_evm_init,
+MACHINE_END