index 9ceddfbb517c5d15d77cb6bbaef2f4139d44a8f8..d688c045177576710df419ddef951d3a9a1170cf 100644 (file)
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/i2c/at24.h>
+#include <linux/gpio.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+/* LCD controller is similar to DA850 */
+#include <video/da8xx-fb.h>
#include <mach/hardware.h>
#include <mach/board-am335xevm.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+#include <asm/hardware/asp.h>
#include <plat/irqs.h>
#include <plat/board.h>
#include <plat/common.h>
+#include <plat/lcdc.h>
+#include <plat/usb.h>
+#include <plat/mmc.h>
+
+#include "board-flash.h"
+#include "mux.h"
+#include "devices.h"
+#include "hsmmc.h"
+
+/* Convert GPIO signal to GPIO pin number */
+#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
+
+static const struct display_panel disp_panel = {
+ WVGA,
+ 32,
+ 32,
+ COLOR_ACTIVE,
+};
+
+static struct lcd_ctrl_config lcd_cfg = {
+ &disp_panel,
+ .ac_bias = 255,
+ .ac_bias_intrpt = 0,
+ .dma_burst_sz = 16,
+ .bpp = 32,
+ .fdd = 0x80,
+ .tft_alt_mode = 0,
+ .stn_565_mode = 0,
+ .mono_8bit_mode = 0,
+ .invert_line_clock = 1,
+ .invert_frm_clock = 1,
+ .sync_edge = 0,
+ .sync_ctrl = 1,
+ .raster_order = 0,
+};
+
+struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
+ .manu_name = "ThreeFive",
+ .controller_data = &lcd_cfg,
+ .type = "TFC_S9700RTWV35TR_01B",
+};
#include "common.h"
-#include "mux.h"
+/* TSc controller */
+#include <linux/input/ti_tscadc.h>
+
+static struct resource tsc_resources[] = {
+ [0] = {
+ .start = AM33XX_TSC_BASE,
+ .end = AM33XX_TSC_BASE + SZ_8K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AM33XX_IRQ_ADC_GEN,
+ .end = AM33XX_IRQ_ADC_GEN,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct tsc_data am335x_touchscreen_data = {
+ .wires = 4,
+ .x_plate_resistance = 200,
+};
+
+static struct platform_device tsc_device = {
+ .name = "tsc",
+ .id = -1,
+ .dev = {
+ .platform_data = &am335x_touchscreen_data,
+ },
+ .num_resources = ARRAY_SIZE(tsc_resources),
+ .resource = tsc_resources,
+};
+
+static u8 am335x_iis_serializer_direction1[] = {
+ INACTIVE_MODE, INACTIVE_MODE, TX_MODE, RX_MODE,
+ INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
+ INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
+ INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
+};
+
+static struct snd_platform_data am335x_evm_snd_data1 = {
+ .tx_dma_offset = 0x46400000, /* McASP1 */
+ .rx_dma_offset = 0x46400000,
+ .op_mode = DAVINCI_MCASP_IIS_MODE,
+ .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
+ .tdm_slots = 2,
+ .serial_dir = am335x_iis_serializer_direction1,
+ .asp_chan_q = EVENTQ_2,
+ .version = MCASP_VERSION_3,
+ .txnumevt = 1,
+ .rxnumevt = 1,
+};
+
+static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
+ {
+ .mmc = 1,
+ .caps = MMC_CAP_4_BIT_DATA,
+ .gpio_cd = GPIO_TO_PIN(0, 6),
+ .gpio_wp = GPIO_TO_PIN(3, 18),
+ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
+ },
+ {
+ .mmc = 0, /* will be set at runtime */
+ },
+ {
+ .mmc = 0, /* will be set at runtime */
+ },
+ {} /* Terminator */
+};
+
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
return val & 0x7;
}
+/* Module pin mux for LCDC */
+static struct pinmux_config lcdc_pin_mux[] = {
+ {"lcd_data0.lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data1.lcd_data1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data2.lcd_data2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data3.lcd_data3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data4.lcd_data4", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data5.lcd_data5", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data6.lcd_data6", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data7.lcd_data7", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data8.lcd_data8", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data9.lcd_data9", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data10.lcd_data10", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data11.lcd_data11", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data12.lcd_data12", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data13.lcd_data13", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data14.lcd_data14", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"lcd_data15.lcd_data15", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
+ | AM33XX_PULL_DISA},
+ {"gpmc_ad8.lcd_data16", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"gpmc_ad9.lcd_data17", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"gpmc_ad10.lcd_data18", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"gpmc_ad11.lcd_data19", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"gpmc_ad12.lcd_data20", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"gpmc_ad13.lcd_data21", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"gpmc_ad14.lcd_data22", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"gpmc_ad15.lcd_data23", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
+ {"lcd_vsync.lcd_vsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"lcd_hsync.lcd_hsync", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"lcd_pclk.lcd_pclk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+};
+
+static struct pinmux_config tsc_pin_mux[] = {
+ {"ain0.ain0", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {"ain1.ain1", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {"ain2.ain2", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {"ain3.ain3", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {"vrefp.vrefp", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {"vrefn.vrefn", OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
+ {NULL, 0},
+};
+
+/* Pin mux for nand flash module */
+static struct pinmux_config nand_pin_mux[] = {
+ {"gpmc_ad0.gpmc_ad0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad1.gpmc_ad1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad2.gpmc_ad2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad3.gpmc_ad3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad4.gpmc_ad4", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad5.gpmc_ad5", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad6.gpmc_ad6", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad7.gpmc_ad7", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_wpn.gpmc_wpn", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_csn0.gpmc_csn0", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ {"gpmc_advn_ale.gpmc_advn_ale", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ {"gpmc_oen_ren.gpmc_oen_ren", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ {"gpmc_wen.gpmc_wen", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ {"gpmc_ben0_cle.gpmc_ben0_cle", OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
+ {NULL, 0},
+};
+
+/* Module pin mux for SPI fash */
+static struct pinmux_config spi0_pin_mux[] = {
+ {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
+ | AM33XX_INPUT_EN},
+ {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
+ | AM33XX_INPUT_EN},
+ {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
+ | AM33XX_INPUT_EN},
+ {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
+ | AM33XX_INPUT_EN},
+ {NULL, 0},
+};
+
+/* Module pin mux for SPI flash */
+static struct pinmux_config spi1_pin_mux[] = {
+ {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
+ | AM33XX_INPUT_EN},
+ {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
+ | AM33XX_PULL_UP | AM33XX_INPUT_EN},
+ {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
+ | AM33XX_INPUT_EN},
+ {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
+ | AM33XX_PULL_UP | AM33XX_INPUT_EN},
+ {NULL, 0},
+};
+
+/* Module pin mux for rgmii1 */
+static struct pinmux_config rgmii1_pin_mux[] = {
+ {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
+ {NULL, 0},
+};
+
+/* Module pin mux for rgmii2 */
+static struct pinmux_config rgmii2_pin_mux[] = {
+ {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
+ {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
+ {NULL, 0},
+};
+
+/* Module pin mux for mii1 */
+static struct pinmux_config mii1_pin_mux[] = {
+ {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
+ {NULL, 0},
+};
+
+static struct pinmux_config i2c1_pin_mux[] = {
+ {"spi0_d1.i2c1_sda", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
+ AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
+ {"spi0_cs0.i2c1_scl", OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
+ AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
+ {NULL, 0},
+};
+
+/* Module pin mux for mcasp1 */
+static struct pinmux_config mcasp1_pin_mux[] = {
+ {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
+ {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
+ AM33XX_PIN_INPUT_PULLDOWN},
+ {NULL, 0},
+};
+
+
+/* Module pin mux for mmc0 */
+static struct pinmux_config mmc0_pin_mux[] = {
+ {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ {"spi0_cs1.mmc0_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
+
+static struct pinmux_config mmc0_no_cd_pin_mux[] = {
+ {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_clk.mmc0_clk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mmc0_cmd.mmc0_cmd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+ {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
+ {NULL, 0},
+};
+
+/* Module pin mux for mmc1 */
+static struct pinmux_config mmc1_pin_mux[] = {
+ {"gpmc_ad7.mmc1_dat7", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad6.mmc1_dat6", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad5.mmc1_dat5", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad4.mmc1_dat4", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad3.mmc1_dat3", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad2.mmc1_dat2", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad1.mmc1_dat1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_ad0.mmc1_dat0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_csn1.mmc1_clk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_csn2.mmc1_cmd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+ {NULL, 0},
+};
+
/*
* @pin_mux - single module pin-mux structure which defines pin-mux
* details for all its pins.
}
}
+#define AM335X_LCD_BL_PIN GPIO_TO_PIN(0, 7)
+
+/* pinmux for usb0 drvvbus */
+static struct pinmux_config usb0_pin_mux[] = {
+ {"usb0_drvvbus.usb0_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+};
+
+/* pinmux for usb1 drvvbus */
+static struct pinmux_config usb1_pin_mux[] = {
+ {"usb1_drvvbus.usb1_drvvbus", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+};
+
+/* Module pin mux for eCAP0 */
+static struct pinmux_config ecap0_pin_mux[] = {
+ {"ecap0_in_pwm0_out.gpio0_7", AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+};
+
+static int backlight_enable;
+
+static void enable_ecap0(int evm_id, int profile)
+{
+ backlight_enable = true;
+}
+
+static int __init ecap0_init(void)
+{
+ int status = 0;
+
+ if (backlight_enable) {
+ setup_pin_mux(ecap0_pin_mux);
+
+ status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n");
+ if (status < 0)
+ pr_warn("Failed to request gpio for LCD backlight\n");
+
+ gpio_direction_output(AM335X_LCD_BL_PIN, 1);
+ }
+ return status;
+}
+late_initcall(ecap0_init);
+
+static int __init conf_disp_pll(int rate)
+{
+ struct clk *disp_pll;
+ int ret = -EINVAL;
+
+ disp_pll = clk_get(NULL, "dpll_disp_ck");
+ if (IS_ERR(disp_pll)) {
+ pr_err("Cannot clk_get disp_pll\n");
+ goto out;
+ }
+
+ ret = clk_set_rate(disp_pll, rate);
+ clk_put(disp_pll);
+out:
+ return ret;
+}
+
+static void lcdc_init(int evm_id, int profile)
+{
+
+ setup_pin_mux(lcdc_pin_mux);
+
+ if (conf_disp_pll(300000000)) {
+ pr_info("Failed configure display PLL, not attempting to"
+ "register LCDC\n");
+ return;
+ }
+
+ if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
+ pr_info("Failed to register LCDC device\n");
+ return;
+}
+
+static void tsc_init(int evm_id, int profile)
+{
+ int err;
+
+ if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
+ am335x_touchscreen_data.analog_input = 1;
+ pr_info("TSC connected to beta GP EVM\n");
+ } else {
+ am335x_touchscreen_data.analog_input = 0;
+ pr_info("TSC connected to alpha GP EVM\n");
+ }
+ setup_pin_mux(tsc_pin_mux);
+ err = platform_device_register(&tsc_device);
+ if (err)
+ pr_err("failed to register touchscreen device\n");
+}
+
+static void rgmii1_init(int evm_id, int profile)
+{
+ setup_pin_mux(rgmii1_pin_mux);
+ return;
+}
+
+static void rgmii2_init(int evm_id, int profile)
+{
+ setup_pin_mux(rgmii2_pin_mux);
+ return;
+}
+
+static void mii1_init(int evm_id, int profile)
+{
+ setup_pin_mux(mii1_pin_mux);
+ return;
+}
+
+static void usb0_init(int evm_id, int profile)
+{
+ setup_pin_mux(usb0_pin_mux);
+ return;
+}
+
+static void usb1_init(int evm_id, int profile)
+{
+ setup_pin_mux(usb1_pin_mux);
+ return;
+}
+
+/* NAND partition information */
+static struct mtd_partition am335x_nand_partitions[] = {
+/* All the partition sizes are listed in terms of NAND block size */
+ {
+ .name = "SPL",
+ .offset = 0, /* Offset = 0x0 */
+ .size = SZ_128K,
+ },
+ {
+ .name = "SPL.backup1",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
+ .size = SZ_128K,
+ },
+ {
+ .name = "SPL.backup2",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x40000 */
+ .size = SZ_128K,
+ },
+ {
+ .name = "SPL.backup3",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
+ .size = SZ_128K,
+ },
+ {
+ .name = "U-Boot",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
+ .size = 15 * SZ_128K,
+ },
+ {
+ .name = "U-Boot Env",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
+ .size = 1 * SZ_128K,
+ },
+ {
+ .name = "Kernel",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
+ .size = 40 * SZ_128K,
+ },
+ {
+ .name = "File System",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+/* SPI 0/1 Platform Data */
+/* SPI flash information */
+static struct mtd_partition am335x_spi_partitions[] = {
+ /* All the partition sizes are listed in terms of erase size */
+ {
+ .name = "SPL",
+ .offset = 0, /* Offset = 0x0 */
+ .size = SZ_128K,
+ },
+ {
+ .name = "U-Boot",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x20000 */
+ .size = 2 * SZ_128K,
+ },
+ {
+ .name = "U-Boot Env",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x60000 */
+ .size = 2 * SZ_4K,
+ },
+ {
+ .name = "Kernel",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x62000 */
+ .size = 28 * SZ_128K,
+ },
+ {
+ .name = "File System",
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x3E2000 */
+ .size = MTDPART_SIZ_FULL, /* size ~= 4.1 MiB */
+ }
+};
+
+static const struct flash_platform_data am335x_spi_flash = {
+ .type = "w25q64",
+ .name = "spi_flash",
+ .parts = am335x_spi_partitions,
+ .nr_parts = ARRAY_SIZE(am335x_spi_partitions),
+};
+
+/*
+ * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
+ * So setup Max speed to be less than that of Controller speed
+ */
+static struct spi_board_info am335x_spi0_slave_info[] = {
+ {
+ .modalias = "m25p80",
+ .platform_data = &am335x_spi_flash,
+ .irq = -1,
+ .max_speed_hz = 24000000,
+ .bus_num = 1,
+ .chip_select = 0,
+ },
+};
+
+static struct spi_board_info am335x_spi1_slave_info[] = {
+ {
+ .modalias = "m25p80",
+ .platform_data = &am335x_spi_flash,
+ .irq = -1,
+ .max_speed_hz = 12000000,
+ .bus_num = 2,
+ .chip_select = 0,
+ },
+};
+
+static void evm_nand_init(int evm_id, int profile)
+{
+ setup_pin_mux(nand_pin_mux);
+ board_nand_init(am335x_nand_partitions,
+ ARRAY_SIZE(am335x_nand_partitions), 0, 0);
+}
+
+static struct i2c_board_info am335x_i2c_boardinfo1[] = {
+ {
+ I2C_BOARD_INFO("tlv320aic3x", 0x1b),
+ },
+};
+
+static void i2c1_init(int evm_id, int profile)
+{
+ setup_pin_mux(i2c1_pin_mux);
+ omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
+ ARRAY_SIZE(am335x_i2c_boardinfo1));
+ return;
+}
+
+/* Setup McASP 1 */
+static void mcasp1_init(int evm_id, int profile)
+{
+ /* Configure McASP */
+ setup_pin_mux(mcasp1_pin_mux);
+ am335x_register_mcasp1(&am335x_evm_snd_data1);
+ return;
+}
+
+static void mmc1_init(int evm_id, int profile)
+{
+ setup_pin_mux(mmc1_pin_mux);
+
+ am335x_mmc[1].mmc = 2;
+ am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
+ am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
+ am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
+ am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
+
+ /* mmc will be initialized when mmc0_init is called */
+ return;
+}
+
+static void mmc0_init(int evm_id, int profile)
+{
+ setup_pin_mux(mmc0_pin_mux);
+
+ omap2_hsmmc_init(am335x_mmc);
+ return;
+}
+
+static void mmc0_no_cd_init(int evm_id, int profile)
+{
+ setup_pin_mux(mmc0_no_cd_pin_mux);
+
+ omap2_hsmmc_init(am335x_mmc);
+ return;
+}
+
+
+/* setup spi0 */
+static void spi0_init(int evm_id, int profile)
+{
+ setup_pin_mux(spi0_pin_mux);
+ spi_register_board_info(am335x_spi0_slave_info,
+ ARRAY_SIZE(am335x_spi0_slave_info));
+ return;
+}
+
+/* setup spi1 */
+static void spi1_init(int evm_id, int profile)
+{
+ setup_pin_mux(spi1_pin_mux);
+ spi_register_board_info(am335x_spi1_slave_info,
+ ARRAY_SIZE(am335x_spi1_slave_info));
+ return;
+}
+
/* Low-Cost EVM */
static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
+ {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
{NULL, 0, 0},
};
/* General Purpose EVM */
static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
+ {enable_ecap0, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
+ PROFILE_2 | PROFILE_7) },
+ {lcdc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
+ PROFILE_2 | PROFILE_7) },
+ {tsc_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
+ PROFILE_2 | PROFILE_7) },
+ {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {rgmii2_init, DEV_ON_DGHTR_BRD, (PROFILE_1 | PROFILE_2 |
+ PROFILE_4 | PROFILE_6) },
+ {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {evm_nand_init, DEV_ON_DGHTR_BRD,
+ (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
+ {i2c1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
+ {mcasp1_init, DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
+ {mmc1_init, DEV_ON_DGHTR_BRD, PROFILE_2},
+ {mmc0_init, DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
+ {mmc0_no_cd_init, DEV_ON_BASEBOARD, PROFILE_5},
+ {spi0_init, DEV_ON_DGHTR_BRD, PROFILE_2},
{NULL, 0, 0},
};
/* Industrial Auto Motor Control EVM */
static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
+ {mii1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
+ {usb0_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {usb1_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+ {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
+ {spi1_init, DEV_ON_DGHTR_BRD, PROFILE_ALL},
{NULL, 0, 0},
};
/* IP-Phone EVM */
static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
+ {enable_ecap0, DEV_ON_DGHTR_BRD, PROFILE_NONE},
+ {lcdc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
+ {tsc_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
+ {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {rgmii2_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
+ {usb0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {usb1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
+ {i2c1_init, DEV_ON_BASEBOARD, PROFILE_NONE},
+ {mcasp1_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
+ {mmc0_init, DEV_ON_BASEBOARD, PROFILE_NONE},
{NULL, 0, 0},
};
else
goto out;
+ /* Initialize cpsw after board detection is completed as board
+ * information is required for configuring phy address and hence
+ * should be call only after board detection
+ */
+ am33xx_cpsw_init();
+
return;
out:
/*
daughter_brd_detected = true;
setup_general_purpose_evm();
+ /* Initialize cpsw after board detection is completed as board
+ * information is required for configuring phy address and hence
+ * should be call only after board detection
+ */
+ am33xx_cpsw_init();
+
}
static struct at24_platform_data am335x_daughter_board_eeprom_info = {
};
+static struct omap_musb_board_data musb_board_data = {
+ .interface_type = MUSB_INTERFACE_ULPI,
+ .mode = MUSB_OTG,
+ .power = 500,
+ .instances = 1,
+};
+
static int cpld_reg_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
ARRAY_SIZE(am335x_i2c_boardinfo));
}
+static struct resource am335x_rtc_resources[] = {
+ {
+ .start = AM33XX_RTC_BASE,
+ .end = AM33XX_RTC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ { /* timer irq */
+ .start = AM33XX_IRQ_RTC_TIMER,
+ .end = AM33XX_IRQ_RTC_TIMER,
+ .flags = IORESOURCE_IRQ,
+ },
+ { /* alarm irq */
+ .start = AM33XX_IRQ_RTC_ALARM,
+ .end = AM33XX_IRQ_RTC_ALARM,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device am335x_rtc_device = {
+ .name = "omap_rtc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(am335x_rtc_resources),
+ .resource = am335x_rtc_resources,
+};
+
+static int am335x_rtc_init(void)
+{
+ void __iomem *base;
+ struct clk *clk;
+
+ clk = clk_get(NULL, "rtc_fck");
+ if (IS_ERR(clk)) {
+ pr_err("rtc : Failed to get RTC clock\n");
+ return -1;
+ }
+
+ if (clk_enable(clk)) {
+ pr_err("rtc: Clock Enable Failed\n");
+ return -1;
+ }
+
+ base = ioremap(AM33XX_RTC_BASE, SZ_4K);
+
+ if (WARN_ON(!base))
+ return -ENOMEM;
+
+ /* Unlock the rtc's registers */
+ __raw_writel(0x83e70b13, base + 0x6c);
+ __raw_writel(0x95a4f1e0, base + 0x70);
+
+ /*
+ * Enable the 32K OSc
+ * TODO: Need a better way to handle this
+ * Since we want the clock to be running before mmc init
+ * we need to do it before the rtc probe happens
+ */
+ __raw_writel(0x48, base + 0x54);
+
+ iounmap(base);
+
+ return platform_device_register(&am335x_rtc_device);
+}
+
+/* Enable clkout2 */
+static struct pinmux_config clkout2_pin_mux[] = {
+ {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
+ {NULL, 0},
+};
+
+static void __init clkout2_enable(void)
+{
+ struct clk *ck_32;
+
+ ck_32 = clk_get(NULL, "clkout2_ck");
+ if (IS_ERR(ck_32)) {
+ pr_err("Cannot clk_get ck_32\n");
+ return;
+ }
+
+ clk_enable(ck_32);
+
+ setup_pin_mux(clkout2_pin_mux);
+}
+
static void __init am335x_evm_init(void)
{
am33xx_mux_init(board_mux);
omap_serial_init();
+ am335x_rtc_init();
+ clkout2_enable();
am335x_evm_i2c_init();
omap_sdrc_init(NULL, NULL);
+ usb_musb_init(&musb_board_data);
omap_board_config = am335x_evm_config;
omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
}