ARM: OMAP: AM33XX: Remove autoidle regs
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / clock33xx_data.c
index db97e62c5ef1b7b5cf117e94aa6dcc79a8508128..43a6d2152373ed169ffda27ef8874b3521d7a5f3 100644 (file)
@@ -94,7 +94,6 @@ static struct dpll_data dpll_per_dd = {
        .clk_ref        = &sys_clkin_ck,
        .control_reg    = AM33XX_CM_CLKMODE_DPLL_PER,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-       .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_PER,
        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_PER,
        .mult_mask      = AM33XX_DPLL_MULT_PERIPH_MASK,
        .div1_mask      = AM33XX_DPLL_PER_DIV_MASK,
@@ -188,7 +187,6 @@ static struct dpll_data dpll_core_dd = {
        .clk_ref        = &sys_clkin_ck,
        .control_reg    = AM33XX_CM_CLKMODE_DPLL_CORE,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-       .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_CORE,
        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_CORE,
        .mult_mask      = AM33XX_DPLL_MULT_MASK,
        .div1_mask      = AM33XX_DPLL_DIV_MASK,
@@ -264,6 +262,7 @@ static struct clk l4ls_fck = {
        .clkdm_name     = "l4ls_clkdm",
        .parent         = &core_100m_ck,
        .recalc         = &followparent_recalc,
+       .flags          = ENABLE_ON_INIT,
 };
 
 static struct clk timer2_ick = {
@@ -384,6 +383,7 @@ static struct clk control_fck = {
        .clkdm_name     = "l4_wkup_clkdm",
        .parent         = &div_l4_wkup_gclk_ck,
        .recalc         = &followparent_recalc,
+       .flags          = ENABLE_ON_INIT,
 };
 
 static struct clk dcan0_fck = {
@@ -450,6 +450,7 @@ static struct clk emif_fw_fck = {
        .clkdm_name     = "l4fw_clkdm",
        .parent         = &core_100m_ck,
        .recalc         = &followparent_recalc,
+       .flags          = ENABLE_ON_INIT,
 };
 
 static struct clk epwmss0_fck = {
@@ -581,6 +582,7 @@ static struct clk ieee5000_fck = {
        .clkdm_name     = "l3s_clkdm",
        .parent         = &core_100m_ck,
        .recalc         = &followparent_recalc,
+       .flags          = ENABLE_ON_INIT,
 };
 
 static struct clk l3_instr_fck = {
@@ -591,6 +593,7 @@ static struct clk l3_instr_fck = {
        .clkdm_name     = "l3_clkdm",
        .parent         = &sysclk_div_ck,
        .recalc         = &followparent_recalc,
+       .flags          = ENABLE_ON_INIT,
 };
 
 static struct clk l3_main_fck = {
@@ -601,6 +604,7 @@ static struct clk l3_main_fck = {
        .clkdm_name     = "l3_clkdm",
        .parent         = &sysclk_div_ck,
        .recalc         = &followparent_recalc,
+       .flags          = ENABLE_ON_INIT,
 };
 
 static struct clk l4_hs_fck = {
@@ -611,6 +615,7 @@ static struct clk l4_hs_fck = {
        .clkdm_name     = "l4hs_clkdm",
        .parent         = &sysclk_div_ck,
        .recalc         = &followparent_recalc,
+       .flags          = ENABLE_ON_INIT,
 };
 
 static struct clk l4fw_fck = {
@@ -621,6 +626,7 @@ static struct clk l4fw_fck = {
        .clkdm_name     = "l4fw_clkdm",
        .parent         = &core_100m_ck,
        .recalc         = &followparent_recalc,
+       .flags          = ENABLE_ON_INIT,
 };
 
 static struct clk l4wkup_fck = {
@@ -631,6 +637,7 @@ static struct clk l4wkup_fck = {
        .clkdm_name     = "l4_wkup_aon_clkdm",
        .parent         = &div_l4_wkup_gclk_ck,
        .recalc         = &followparent_recalc,
+       .flags          = ENABLE_ON_INIT,
 };
 
 static struct clk mailbox0_fck = {
@@ -1189,7 +1196,6 @@ static struct dpll_data dpll_ddr_dd = {
        .clk_ref        = &sys_clkin_ck,
        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DDR,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-       .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_DDR,
        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DDR,
        .mult_mask      = AM33XX_DPLL_MULT_MASK,
        .div1_mask      = AM33XX_DPLL_DIV_MASK,
@@ -1243,6 +1249,7 @@ static struct clk emif_fck = {
        .clkdm_name     = "l3_clkdm",
        .parent         = &ddr_pll_div_clk,
        .recalc         = &followparent_recalc,
+       .flags          = ENABLE_ON_INIT,
 };
 
 static struct clk div_l4_rtc_gclk_ck = {
@@ -1259,7 +1266,6 @@ static struct dpll_data dpll_disp_dd = {
        .clk_ref        = &sys_clkin_ck,
        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DISP,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-       .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_DISP,
        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DISP,
        .mult_mask      = AM33XX_DPLL_MULT_MASK,
        .div1_mask      = AM33XX_DPLL_DIV_MASK,
@@ -1306,7 +1312,6 @@ static struct dpll_data dpll_mpu_dd = {
        .clk_ref        = &sys_clkin_ck,
        .control_reg    = AM33XX_CM_CLKMODE_DPLL_MPU,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-       .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_MPU,
        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_MPU,
        .mult_mask      = AM33XX_DPLL_MULT_MASK,
        .div1_mask      = AM33XX_DPLL_DIV_MASK,
@@ -1323,8 +1328,10 @@ static struct clk dpll_mpu_ck = {
        .parent         = &sys_clkin_ck,
        .dpll_data      = &dpll_mpu_dd,
        .init           = &omap2_init_dpll_parent,
-       .ops            = &clkops_null,
+       .ops            = &clkops_omap3_noncore_dpll_ops,
        .recalc         = &omap3_dpll_recalc,
+       .round_rate     = &omap2_dpll_round_rate,
+       .set_rate       = &omap3_noncore_dpll_set_rate,
 };
 
 
@@ -1704,6 +1711,7 @@ static struct clk vtp_clk_div_ck = {
        .parent         = &sys_clkin_ck,
        .ops            = &clkops_null,
        .recalc         = &followparent_recalc,
+       .flags          = ENABLE_ON_INIT,
 };