ARM: OMAP: AM33XX: Remove autoidle regs
[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / clock33xx_data.c
index fb88543fa4c73e8570d204bdbe10a93656c5467c..43a6d2152373ed169ffda27ef8874b3521d7a5f3 100644 (file)
@@ -94,7 +94,6 @@ static struct dpll_data dpll_per_dd = {
        .clk_ref        = &sys_clkin_ck,
        .control_reg    = AM33XX_CM_CLKMODE_DPLL_PER,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
        .clk_ref        = &sys_clkin_ck,
        .control_reg    = AM33XX_CM_CLKMODE_DPLL_PER,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-       .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_PER,
        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_PER,
        .mult_mask      = AM33XX_DPLL_MULT_PERIPH_MASK,
        .div1_mask      = AM33XX_DPLL_PER_DIV_MASK,
        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_PER,
        .mult_mask      = AM33XX_DPLL_MULT_PERIPH_MASK,
        .div1_mask      = AM33XX_DPLL_PER_DIV_MASK,
@@ -188,7 +187,6 @@ static struct dpll_data dpll_core_dd = {
        .clk_ref        = &sys_clkin_ck,
        .control_reg    = AM33XX_CM_CLKMODE_DPLL_CORE,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
        .clk_ref        = &sys_clkin_ck,
        .control_reg    = AM33XX_CM_CLKMODE_DPLL_CORE,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-       .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_CORE,
        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_CORE,
        .mult_mask      = AM33XX_DPLL_MULT_MASK,
        .div1_mask      = AM33XX_DPLL_DIV_MASK,
        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_CORE,
        .mult_mask      = AM33XX_DPLL_MULT_MASK,
        .div1_mask      = AM33XX_DPLL_DIV_MASK,
@@ -1198,7 +1196,6 @@ static struct dpll_data dpll_ddr_dd = {
        .clk_ref        = &sys_clkin_ck,
        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DDR,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
        .clk_ref        = &sys_clkin_ck,
        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DDR,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-       .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_DDR,
        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DDR,
        .mult_mask      = AM33XX_DPLL_MULT_MASK,
        .div1_mask      = AM33XX_DPLL_DIV_MASK,
        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DDR,
        .mult_mask      = AM33XX_DPLL_MULT_MASK,
        .div1_mask      = AM33XX_DPLL_DIV_MASK,
@@ -1269,7 +1266,6 @@ static struct dpll_data dpll_disp_dd = {
        .clk_ref        = &sys_clkin_ck,
        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DISP,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
        .clk_ref        = &sys_clkin_ck,
        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DISP,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-       .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_DISP,
        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DISP,
        .mult_mask      = AM33XX_DPLL_MULT_MASK,
        .div1_mask      = AM33XX_DPLL_DIV_MASK,
        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DISP,
        .mult_mask      = AM33XX_DPLL_MULT_MASK,
        .div1_mask      = AM33XX_DPLL_DIV_MASK,
@@ -1316,7 +1312,6 @@ static struct dpll_data dpll_mpu_dd = {
        .clk_ref        = &sys_clkin_ck,
        .control_reg    = AM33XX_CM_CLKMODE_DPLL_MPU,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
        .clk_ref        = &sys_clkin_ck,
        .control_reg    = AM33XX_CM_CLKMODE_DPLL_MPU,
        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-       .autoidle_reg   = AM33XX_CM_AUTOIDLE_DPLL_MPU,
        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_MPU,
        .mult_mask      = AM33XX_DPLL_MULT_MASK,
        .div1_mask      = AM33XX_DPLL_DIV_MASK,
        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_MPU,
        .mult_mask      = AM33XX_DPLL_MULT_MASK,
        .div1_mask      = AM33XX_DPLL_DIV_MASK,