arm:omap:am33xx: register edma platform

[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / control.h

diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index d4ef75d5a3823d0f85336e8f416e8d861553f83a..50da5673e26eba0c48470318de9a74b89c6875ad 100644 (file)
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -29,6 +29,8 @@
                OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
 #define OMAP343X_CTRL_REGADDR(reg)                                     \
                OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define AM33XX_CTRL_REGADDR(reg)                                       \
+               AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
 #else
 #define OMAP242X_CTRL_REGADDR(reg)                                     \
                OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -52,8 +54,14 @@
 #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00
 #define OMAP343X_CONTROL_GENERAL_WKUP  0xa60
 
-/* TI816X spefic control submodules */
-#define TI816X_CONTROL_DEVCONF         0x600
+/* TI81XX spefic control submodules */
+#define TI81XX_CONTROL_DEVCONF         0x600
+
+/* TI81XX CONTROL_DEVCONF register offsets */
+#define TI81XX_CONTROL_MAC_ID0_LO       (TI81XX_CONTROL_DEVCONF + 0x030)
+#define TI81XX_CONTROL_MAC_ID0_HI       (TI81XX_CONTROL_DEVCONF + 0x034)
+#define TI81XX_CONTROL_MAC_ID1_LO       (TI81XX_CONTROL_DEVCONF + 0x038)
+#define TI81XX_CONTROL_MAC_ID1_HI       (TI81XX_CONTROL_DEVCONF + 0x03c)
 
 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
 
@@ -244,8 +252,8 @@
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
 
-/* TI816X CONTROL_DEVCONF register offsets */
-#define TI816X_CONTROL_DEVICE_ID       (TI816X_CONTROL_DEVCONF + 0x000)
+/* TI81XX CONTROL_DEVCONF register offsets */
+#define TI81XX_CONTROL_DEVICE_ID       (TI81XX_CONTROL_DEVCONF + 0x000)
 
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
@@ -338,6 +346,21 @@
 #define AM35XX_HECC_SW_RST             BIT(3)
 #define AM35XX_VPFE_PCLK_SW_RST                BIT(4)
 
+/* AM33XX CONTROL_STATUS bits */
+#define AM33XX_SYSBOOT0                        (0xff << 0)
+#define AM33XX_DEVTYPE                 (1 << 8)
+#define AM33XX_GPMC_CS0_BW             (1 << 16)
+#define AM33XX_GPMC_CS0_WAITEN         (1 << 17)
+#define AM33XX_GPMC_CS0_ADMUX          (0x3 << 18)
+#define AM33XX_SYSBOOT1                        (0x3 << 22)
+
+/*
+ * CONTROL AM33XX STATUS register to identify boot-time configurations
+ */
+#define AM33XX_CONTROL_STATUS_OFF      0x040
+#define AM33XX_CONTROL_STATUS          AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE + \
+                                               AM33XX_CONTROL_STATUS_OFF)
+
 /*
  * CONTROL OMAP STATUS register to identify OMAP3 features
  */