index 2f342fbb0e7854ce10eb9087389230b21a3a3cbb..bf5d54c44fda7f1fb1aa74b23d74a1c0b91ba739 100644 (file)
#include <linux/cpsw.h>
#include <linux/etherdevice.h>
#include <linux/dma-mapping.h>
+#include <linux/can/platform/d_can.h>
+#include <linux/platform_data/uio_pruss.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#define L3_MODULES_MAX_LEN 12
#define L3_MODULES 3
-void am33xx_cpsw_init(void);
-
static int __init omap3_l3_init(void)
{
int l;
* To avoid code running on other OMAPs in
* multi-omap builds
*/
- if (!(cpu_is_omap34xx()))
+ if (!(cpu_is_omap34xx()) || (cpu_is_am33xx()))
return -ENODEV;
l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
static void omap_init_audio(void)
{
+ if (cpu_is_am33xx())
+ return;
+
platform_device_register(&omap_mcbsp1);
platform_device_register(&omap_mcbsp2);
if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
{
if (cpu_is_omap24xx())
omap_pmu_device.resource = &omap2_pmu_resource;
- else if (cpu_is_omap34xx())
+ else if (cpu_is_omap34xx() && !cpu_is_am33xx())
omap_pmu_device.resource = &omap3_pmu_resource;
else
return;
if (cpu_is_omap24xx()) {
sham_device.resource = omap2_sham_resources;
sham_device.num_resources = omap2_sham_resources_sz;
- } else if (cpu_is_omap34xx()) {
+ } else if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
sham_device.resource = omap3_sham_resources;
sham_device.num_resources = omap3_sham_resources_sz;
} else {
if (cpu_is_omap24xx()) {
aes_device.resource = omap2_aes_resources;
aes_device.num_resources = omap2_aes_resources_sz;
- } else if (cpu_is_omap34xx()) {
+ } else if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
aes_device.resource = omap3_aes_resources;
aes_device.num_resources = omap3_aes_resources_sz;
} else {
static inline void am33xx_register_edma(void) {}
#endif
+#if defined (CONFIG_SOC_OMAPAM33XX)
+struct uio_pruss_pdata am335x_pruss_uio_pdata = {
+ .pintc_base = 0x20000,
+};
+
+static struct resource am335x_pruss_resources[] = {
+ {
+ .start = AM33XX_ICSS_BASE,
+ .end = AM33XX_ICSS_BASE + AM33XX_ICSS_LEN,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_0,
+ .end = AM33XX_IRQ_ICSS0_0,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_1,
+ .end = AM33XX_IRQ_ICSS0_1,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_2,
+ .end = AM33XX_IRQ_ICSS0_2,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_3,
+ .end = AM33XX_IRQ_ICSS0_3,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_4,
+ .end = AM33XX_IRQ_ICSS0_4,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_5,
+ .end = AM33XX_IRQ_ICSS0_5,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_6,
+ .end = AM33XX_IRQ_ICSS0_6,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = AM33XX_IRQ_ICSS0_7,
+ .end = AM33XX_IRQ_ICSS0_7,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device am335x_pruss_uio_dev = {
+ .name = "pruss_uio",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(am335x_pruss_resources),
+ .resource = am335x_pruss_resources,
+ .dev = {
+ .coherent_dma_mask = 0xffffffff,
+ }
+};
+
+int __init am335x_register_pruss_uio(struct uio_pruss_pdata *config)
+{
+ am335x_pruss_uio_dev.dev.platform_data = config;
+ return platform_device_register(&am335x_pruss_uio_dev);
+}
+#endif
+
/*-------------------------------------------------------------------------*/
static int __init omap2_init_devices(void)
omap_init_vout();
am33xx_register_edma();
am33xx_init_pcm();
-
+#if defined (CONFIG_SOC_OMAPAM33XX)
+ am335x_register_pruss_uio(&am335x_pruss_uio_pdata);
+#endif
return 0;
}
arch_initcall(omap2_init_devices);
-#define AM33XX_CPSW_BASE (0x4A100000)
-#define AM33XX_CPSW_MDIO_BASE (0x4A101000)
-#define AM33XX_CPSW_SS_BASE (0x4A101200)
#define AM33XX_EMAC_MDIO_FREQ (1000000)
static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32);
.flags = IORESOURCE_IRQ,
},
{
- .start = AM33XX_IRQ_CPSW_RX,
- .end = AM33XX_IRQ_CPSW_RX,
+ .start = AM33XX_IRQ_DMTIMER5,
+ .end = AM33XX_IRQ_DMTIMER5,
.flags = IORESOURCE_IRQ,
},
{
- .start = AM33XX_IRQ_CPSW_TX,
- .end = AM33XX_IRQ_CPSW_TX,
+ .start = AM33XX_IRQ_DMTIMER6,
+ .end = AM33XX_IRQ_DMTIMER6,
.flags = IORESOURCE_IRQ,
},
{
return;
}
-void am33xx_cpsw_init(void)
+#define MII_MODE_ENABLE 0x0
+#define RMII_MODE_ENABLE 0x5
+#define RGMII_MODE_ENABLE 0xA
+#define MAC_MII_SEL 0x650
+
+void am33xx_cpsw_init(unsigned int gigen)
{
u32 mac_lo, mac_hi;
u32 i;
am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
}
- if (am33xx_evmid == IND_AUT_MTR_EVM) {
+ if (am33xx_evmid == BEAGLE_BONE_OLD) {
+ __raw_writel(RMII_MODE_ENABLE,
+ AM33XX_CTRL_REGADDR(MAC_MII_SEL));
+ } else if (am33xx_evmid == BEAGLE_BONE_A3) {
+ __raw_writel(MII_MODE_ENABLE,
+ AM33XX_CTRL_REGADDR(MAC_MII_SEL));
+ } else if (am33xx_evmid == IND_AUT_MTR_EVM) {
am33xx_cpsw_slaves[0].phy_id = "0:1e";
am33xx_cpsw_slaves[1].phy_id = "0:00";
+ } else {
+ __raw_writel(RGMII_MODE_ENABLE,
+ AM33XX_CTRL_REGADDR(MAC_MII_SEL));
}
+ am33xx_cpsw_pdata.gigabit_en = gigen;
+
memcpy(am33xx_cpsw_pdata.mac_addr,
am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);
platform_device_register(&am33xx_cpsw_mdiodevice);
NULL, &am33xx_cpsw_device.dev);
}
+#define AM33XX_D_CAN_RAM_BASE 0x1000
+#define AM33XX_D_CAN_NUM_MSG_OBJS 64
+#define AM33XX_CTL_DCAN_RAMINIT_OFFSET 0x644
+#define AM33XX_D_CAN_RAMINIT_START(n) (0x1 << n)
+
+static void d_can_hw_raminit(unsigned int instance)
+{
+ u32 val;
+
+ /* Read the value */
+ val = __raw_readl(AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
+
+ /* Modify by setting "0" */
+ val &= ~AM33XX_D_CAN_RAMINIT_START(instance);
+ __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
+
+ /* Reset to one */
+ val |= AM33XX_D_CAN_RAMINIT_START(instance);
+ __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
+
+ /* Give some time delay for transition from 0 -> 1 */
+ udelay(1);
+}
+
+static struct d_can_platform_data am33xx_evm_d_can0_pdata = {
+ .d_can_offset = 0,
+ .d_can_ram_offset = AM33XX_D_CAN_RAM_BASE,
+ .num_of_msg_objs = AM33XX_D_CAN_NUM_MSG_OBJS,
+ .dma_support = false,
+ .parity_check = false,
+ .fck_name = "dcan0_fck",
+ .ick_name = "dcan0_ick",
+};
+
+static struct resource am33xx_d_can0_resources[] = {
+ {
+ .start = AM33XX_D_CAN0_BASE,
+ .end = AM33XX_D_CAN0_BASE + 0x3FFF,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "int0",
+ .start = AM33XX_IRQ_DCAN0_0,
+ .end = AM33XX_IRQ_DCAN0_0,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "int1",
+ .start = AM33XX_IRQ_DCAN0_1,
+ .end = AM33XX_IRQ_DCAN0_1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device am33xx_d_can0_device = {
+ .dev = {
+ .platform_data = &am33xx_evm_d_can0_pdata,
+ },
+ .name = "d_can",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(am33xx_d_can0_resources),
+ .resource = am33xx_d_can0_resources,
+};
+
+static struct resource am33xx_d_can1_resources[] = {
+ {
+ .start = AM33XX_D_CAN1_BASE,
+ .end = AM33XX_D_CAN1_BASE + 0x3FFF,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "int0",
+ .start = AM33XX_IRQ_DCAN1_0,
+ .end = AM33XX_IRQ_DCAN1_0,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "int1",
+ .start = AM33XX_IRQ_DCAN1_1,
+ .end = AM33XX_IRQ_DCAN1_1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct d_can_platform_data am33xx_evm_d_can1_pdata = {
+ .d_can_offset = 0,
+ .d_can_ram_offset = AM33XX_D_CAN_RAM_BASE,
+ .num_of_msg_objs = AM33XX_D_CAN_NUM_MSG_OBJS,
+ .dma_support = false,
+ .parity_check = false,
+ .fck_name = "dcan1_fck",
+ .ick_name = "dcan1_ick",
+};
+
+static struct platform_device am33xx_d_can1_device = {
+ .dev = {
+ .platform_data = &am33xx_evm_d_can1_pdata,
+ },
+ .name = "d_can",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(am33xx_d_can1_resources),
+ .resource = am33xx_d_can1_resources,
+};
+
+void am33xx_d_can_init(unsigned int instance)
+{
+ switch (instance) {
+ case 0:
+ d_can_hw_raminit(instance);
+ platform_device_register(&am33xx_d_can0_device);
+ break;
+ case 1:
+ d_can_hw_raminit(instance);
+ platform_device_register(&am33xx_d_can1_device);
+ break;
+ default:
+ break;
+ }
+}
#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
static int __init omap_init_wdt(void)