diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 1c8f252a582ad8a8dada2dbd3911bed461068117..a78ddb4358be09f3e68fed9efd5ea2c5bc4d3d99 100644 (file)
* GNU General Public License for more details.
*/
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+
#include <plat/omap_hwmod.h>
#include <plat/cpu.h>
#include <plat/gpio.h>
#include <plat/mmc.h>
#include <plat/mcspi.h>
#include <plat/i2c.h>
+#include <plat/clock.h>
+#include <plat/prcm.h>
#include "omap_hwmod_common_data.h"
#include "control.h"
#include "cm33xx.h"
#include "prm33xx.h"
+#include "common.h"
/* Backward references (IPs with Bus Master capability) */
static struct omap_hwmod am33xx_mpu_hwmod;
static struct omap_hwmod am33xx_tptc0_hwmod;
static struct omap_hwmod am33xx_tptc1_hwmod;
static struct omap_hwmod am33xx_tptc2_hwmod;
+static struct omap_hwmod am33xx_dcan0_hwmod;
+static struct omap_hwmod am33xx_dcan1_hwmod;
static struct omap_hwmod am33xx_gpio0_hwmod;
static struct omap_hwmod am33xx_gpio1_hwmod;
static struct omap_hwmod am33xx_gpio2_hwmod;
static struct omap_hwmod am33xx_adc_tsc_hwmod;
static struct omap_hwmod am33xx_mcasp0_hwmod;
static struct omap_hwmod am33xx_mcasp1_hwmod;
-static struct omap_hwmod am33xx_epwmss0_hwmod;
-static struct omap_hwmod am33xx_epwmss1_hwmod;
-static struct omap_hwmod am33xx_epwmss2_hwmod;
+static struct omap_hwmod am33xx_ehrpwm0_hwmod;
+static struct omap_hwmod am33xx_ehrpwm1_hwmod;
+static struct omap_hwmod am33xx_ehrpwm2_hwmod;
+static struct omap_hwmod am33xx_ecap0_hwmod;
+static struct omap_hwmod am33xx_ecap1_hwmod;
+static struct omap_hwmod am33xx_ecap2_hwmod;
static struct omap_hwmod am33xx_gpmc_hwmod;
static struct omap_hwmod am33xx_lcdc_hwmod;
static struct omap_hwmod am33xx_mailbox_hwmod;
static struct omap_hwmod am33xx_cpgmac0_hwmod;
+static struct omap_hwmod am33xx_mdio_hwmod;
+
+/*
+ * ERRATA: (Yet to conform from IP team)
+ * As per the observation, in order to disable the cpsw clock/module
+ * from already enabled state, module level reset assertion is
+ * required; without reset the clock/module won't enter into
+ * idle state at all.
+ * Also, as per observation (have not conformed yet), we have to
+ * assert reset signal for all cpsw (4) submodules.
+ */
+
+/* OCP SYSSTATUS bit shifts/masks */
+#define SOFT_RESETDONE_SHIFT 0
+#define SOFT_RESETDONE_MASK (1 << SOFT_RESETDONE_SHIFT)
+
+#define MAX_MODULE_SOFTRESET_WAIT 10000
+
+static int am33xx_cpgmac_reset(struct omap_hwmod *oh)
+{
+ int i;
+ int ret = 0;
+
+ pr_debug("%s: resetting via Module SOFTRESET bit\n", oh->name);
+
+ for (i = 0; i < oh->slaves_cnt; i++) {
+ int c = 0;
+ void __iomem *va_start;
+ struct omap_hwmod_ocp_if *os;
+ struct omap_hwmod_addr_space *mem;
+
+ os = oh->slaves[i];
+ /* FIXME: Only first instance's OCP_RST is asserted */
+ mem = &os->addr[0];
+
+ va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
+ if (!va_start) {
+ pr_err("%s: Could not ioremap (%x)\n",
+ oh->name, mem->pa_start);
+ ret = -ENOMEM;
+ break;
+ }
+ /* Assert reset signal */
+ writel(1, va_start + oh->class->sysc->rst_offs);
+ omap_test_timeout(((readl(va_start + oh->class->sysc->rst_offs)
+ & SOFT_RESETDONE_MASK) == 0),
+ MAX_MODULE_SOFTRESET_WAIT, c);
+
+ if (c == MAX_MODULE_SOFTRESET_WAIT) {
+ pr_warning("%s: softreset failed (waited %d usec)\n",
+ oh->name, MAX_MODULE_SOFTRESET_WAIT);
+ ret = -ETIMEDOUT;
+ }
+ }
+
+ return ret;
+}
/*
* Interconnects hwmod structures
.slaves_cnt = ARRAY_SIZE(am33xx_l3_slow_slaves),
};
+/* L4 PER -> DCAN0 */
+static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
+ {
+ .pa_start = 0x481CC000,
+ .pa_end = 0x481CC000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_dcan0_hwmod,
+ .clk = "dcan0_ick",
+ .addr = am33xx_dcan0_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 PER -> DCAN1 */
+static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
+ {
+ .pa_start = 0x481D0000,
+ .pa_end = 0x481D0000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_dcan1_hwmod,
+ .clk = "dcan1_ick",
+ .addr = am33xx_dcan1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* L4 PER -> GPIO2 */
static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
{
/* Master interfaces on the L4_PER interconnect */
static struct omap_hwmod_ocp_if *am33xx_l4_per_masters[] = {
+ &am33xx_l4_per__dcan0,
+ &am33xx_l4_per__dcan1,
&am33xx_l4_per__gpio1,
&am33xx_l4_per__gpio2,
&am33xx_l4_per__gpio3,
{ .irq = -1 }
};
+static struct omap_hwmod_dma_info am33xx_aes0_dma[] = {
+ { .dma_req = AM33XX_DMA_AESEIP36T0_DOUT },
+ { .dma_req = AM33XX_DMA_AESEIP36T0_DIN },
+ { .dma_req = -1 }
+};
+
static struct omap_hwmod am33xx_aes0_hwmod = {
.name = "aes0",
.class = &am33xx_aes_hwmod_class,
.clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_aes0_irqs,
+ .sdma_reqs = am33xx_aes0_dma,
.main_clk = "aes0_fck",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
};
/* control */
.rev_offs = 0x0,
.sysc_offs = 0x8,
.syss_offs = 0x4,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
- SYSS_HAS_RESET_STATUS),
+ .rst_offs = 0x8,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
MSTANDBY_NO),
.sysc_fields = &omap_hwmod_sysc_type3,
};
static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
- .name = "cpgmac0",
+ .name = "cpsw",
.sysc = &am33xx_cpgmac_sysc,
+ .reset = am33xx_cpgmac_reset,
};
+/* Used by driver */
struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
+ /* cpsw ss */
+ {
+ .pa_start = 0x4A100000,
+ .pa_end = 0x4A100000 + SZ_2K - 1,
+ .flags = ADDR_MAP_ON_INIT,
+ },
+ /* cpsw wr */
{
.pa_start = 0x4A101200,
- .pa_end = 0x4A101200 + SZ_8K - 1,
- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ .pa_end = 0x4A101200 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT,
},
{ }
};
.user = OCP_USER_MPU,
};
+struct omap_hwmod_addr_space am33xx_cpsw_sl1_addr_space[] = {
+ /* cpsw sl1 */
+ {
+ .pa_start = 0x4A100D84,
+ .pa_end = 0x4A100D84 + SZ_32 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__cpsw_sl1 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_cpgmac0_hwmod,
+ .addr = am33xx_cpsw_sl1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+struct omap_hwmod_addr_space am33xx_cpsw_sl2_addr_space[] = {
+ /* cpsw sl2 */
+ {
+ .pa_start = 0x4A100DC4,
+ .pa_end = 0x4A100DC4 + SZ_32 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__cpsw_sl2 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_cpgmac0_hwmod,
+ .addr = am33xx_cpsw_sl2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+struct omap_hwmod_addr_space am33xx_cpsw_cpdma_addr_space[] = {
+ /* cpsw cpdma */
+ {
+ .pa_start = 0x4A100814,
+ .pa_end = 0x4A100814 + SZ_32 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__cpsw_cpdma = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_cpgmac0_hwmod,
+ .addr = am33xx_cpsw_cpdma_addr_space,
+ .user = OCP_USER_MPU,
+};
+
static struct omap_hwmod_ocp_if *am33xx_cpgmac0_slaves[] = {
&am33xx_l3_main__cpgmac0,
+ &am33xx_l3_main__cpsw_sl1,
+ &am33xx_l3_main__cpsw_sl2,
+ &am33xx_l3_main__cpsw_cpdma,
};
static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
{ .name = "c0_rx_thresh_pend", .irq = 40 },
- { .name = "c0_rx_pend", .irq = 41 },
- { .name = "c0_tx_pend", .irq = 42 },
+ { .name = "c0_rx_pend", .irq = 93 },
+ { .name = "c0_tx_pend", .irq = 94 },
{ .name = "c0_misc_pend", .irq = 43 },
{ .irq = -1 }
};
},
.slaves = am33xx_cpgmac0_slaves,
.slaves_cnt = ARRAY_SIZE(am33xx_cpgmac0_slaves),
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+ HWMOD_SWSUP_RESET_BEFORE_IDLE),
+};
+
+/* mdio class */
+static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
+ .name = "davinci_mdio",
+};
+
+struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
+ {
+ .pa_start = 0x4A101000,
+ .pa_end = 0x4A101000 + SZ_256 - 1,
+ .flags = ADDR_MAP_ON_INIT,
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
+ .master = &am33xx_cpgmac0_hwmod,
+ .slave = &am33xx_mdio_hwmod,
+ .addr = am33xx_mdio_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_mdio_slaves[] = {
+ &am33xx_cpgmac0__mdio,
+};
+
+static struct omap_hwmod am33xx_mdio_hwmod = {
+ .name = "mdio",
+ .class = &am33xx_mdio_hwmod_class,
+ .clkdm_name = "cpsw_125mhz_clkdm",
+ .main_clk = "cpgmac0_ick",
+ .slaves = am33xx_mdio_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_mdio_slaves),
};
/* 'dcan' class */
static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
- .name = "dcan",
+ .name = "d_can",
+};
+
+/* dcan0 slave ports */
+static struct omap_hwmod_ocp_if *am33xx_dcan0_slaves[] = {
+ &am33xx_l4_per__dcan0,
};
/* dcan0 */
static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
- { .irq = 52 },
+ { .name = "d_can_ms", .irq = 52 },
+ { .name = "d_can_mo", .irq = 53 },
{ .irq = -1 }
};
static struct omap_hwmod am33xx_dcan0_hwmod = {
- .name = "dcan0",
+ .name = "d_can0",
.class = &am33xx_dcan_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_dcan0_irqs,
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .slaves = am33xx_dcan0_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_dcan0_slaves),
+};
+
+/* dcan1 slave ports */
+static struct omap_hwmod_ocp_if *am33xx_dcan1_slaves[] = {
+ &am33xx_l4_per__dcan1,
};
/* dcan1 */
static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
- { .irq = 55 },
+ { .name = "d_can_ms", .irq = 55 },
+ { .name = "d_can_mo", .irq = 56 },
{ .irq = -1 }
};
+
static struct omap_hwmod am33xx_dcan1_hwmod = {
- .name = "dcan1",
+ .name = "d_can1",
.class = &am33xx_dcan_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.mpu_irqs = am33xx_dcan1_irqs,
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .slaves = am33xx_dcan1_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_dcan1_slaves),
};
/* debugss */
/* 'epwmss' class */
static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
.rev_offs = 0x0,
- .sysc_offs = 0x10,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .sysc_offs = 0x4,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
.sysc = &am33xx_epwmss_sysc,
};
-/* epwmss0 */
-static struct omap_hwmod_irq_info am33xx_epwmss0_irqs[] = {
+/* ehrpwm0 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
{ .irq = 86 },
{ .irq = 58 },
- { .irq = 31 },
{ .irq = -1 }
};
-struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
+struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
+/*
+ * Splitting the resources to handle access of PWMSS config space and module
+ * specific part independently
+ */
{
.pa_start = 0x48300000,
- .pa_end = 0x48300000 + SZ_4K - 1,
+ .pa_end = 0x48300000 + SZ_16 - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48300000 + SZ_512,
+ .pa_end = 0x48300000 + SZ_512 + SZ_256 - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
-struct omap_hwmod_ocp_if am33xx_l4_core__epwmss0 = {
+struct omap_hwmod_ocp_if am33xx_l4_core__ehrpwm0 = {
.master = &am33xx_l4per_hwmod,
- .slave = &am33xx_epwmss0_hwmod,
- .addr = am33xx_epwmss0_addr_space,
+ .slave = &am33xx_ehrpwm0_hwmod,
+ .addr = am33xx_ehrpwm0_addr_space,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_ocp_if *am33xx_epwmss0_slaves[] = {
- &am33xx_l4_core__epwmss0,
+static struct omap_hwmod_ocp_if *am33xx_ehrpwm0_slaves[] = {
+ &am33xx_l4_core__ehrpwm0,
+};
+
+static struct omap_hwmod_opt_clk ehrpwm0_opt_clks[] = {
+ { .role = "tbclk", .clk = "ehrpwm0_tbclk" },
};
-static struct omap_hwmod am33xx_epwmss0_hwmod = {
- .name = "epwmss0",
+static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
+ .name = "ehrpwm.0",
+ .mpu_irqs = am33xx_ehrpwm0_irqs,
.class = &am33xx_epwmss_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_epwmss0_irqs,
.main_clk = "epwmss0_fck",
+ .clkdm_name = "l4ls_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = am33xx_epwmss0_slaves,
- .slaves_cnt = ARRAY_SIZE(am33xx_epwmss0_slaves),
+ .slaves = am33xx_ehrpwm0_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_ehrpwm0_slaves),
+ .opt_clks = ehrpwm0_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(ehrpwm0_opt_clks),
};
-/* epwmss1 */
-static struct omap_hwmod_irq_info am33xx_epwmss1_irqs[] = {
+/* ehrpwm1 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
{ .irq = 87 },
{ .irq = 59 },
- { .irq = 47 },
{ .irq = -1 }
};
-struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
+struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
+/*
+ * Splitting the resources to handle access of PWMSS config space and module
+ * specific part independently
+ */
{
.pa_start = 0x48302000,
- .pa_end = 0x48302000 + SZ_4K - 1,
+ .pa_end = 0x48302000 + SZ_16 - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48302000 + SZ_512,
+ .pa_end = 0x48302000 + SZ_512 + SZ_256 - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
-struct omap_hwmod_ocp_if am33xx_l4_core__epwmss1 = {
+struct omap_hwmod_ocp_if am33xx_l4_core__ehrpwm1 = {
.master = &am33xx_l4per_hwmod,
- .slave = &am33xx_epwmss1_hwmod,
- .addr = am33xx_epwmss1_addr_space,
+ .slave = &am33xx_ehrpwm1_hwmod,
+ .addr = am33xx_ehrpwm1_addr_space,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_ocp_if *am33xx_epwmss1_slaves[] = {
- &am33xx_l4_core__epwmss1,
+static struct omap_hwmod_ocp_if *am33xx_ehrpwm1_slaves[] = {
+ &am33xx_l4_core__ehrpwm1,
};
-static struct omap_hwmod am33xx_epwmss1_hwmod = {
- .name = "epwmss1",
+static struct omap_hwmod_opt_clk ehrpwm1_opt_clks[] = {
+ { .role = "tbclk", .clk = "ehrpwm1_tbclk" },
+};
+
+static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
+ .name = "ehrpwm.1",
+ .mpu_irqs = am33xx_ehrpwm1_irqs,
.class = &am33xx_epwmss_hwmod_class,
- .clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_epwmss1_irqs,
.main_clk = "epwmss1_fck",
+ .clkdm_name = "l4ls_clkdm",
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = am33xx_epwmss1_slaves,
- .slaves_cnt = ARRAY_SIZE(am33xx_epwmss1_slaves),
+ .slaves = am33xx_ehrpwm1_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_ehrpwm1_slaves),
+ .opt_clks = ehrpwm1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(ehrpwm1_opt_clks),
};
-/* epwmss2 */
-static struct omap_hwmod_irq_info am33xx_epwmss2_irqs[] = {
+/* ehrpwm2 */
+static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
{ .irq = 39 },
{ .irq = 60 },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
+/*
+ * Splitting the resources to handle access of PWMSS config space and module
+ * specific part independently
+ */
+ {
+ .pa_start = 0x48304000,
+ .pa_end = 0x48304000 + SZ_16 - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48304000 + SZ_512,
+ .pa_end = 0x48304000 + SZ_512 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_core__ehrpwm2 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_ehrpwm2_hwmod,
+ .addr = am33xx_ehrpwm2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_ehrpwm2_slaves[] = {
+ &am33xx_l4_core__ehrpwm2,
+};
+
+static struct omap_hwmod_opt_clk ehrpwm2_opt_clks[] = {
+ { .role = "tbclk", .clk = "ehrpwm2_tbclk" },
+};
+
+static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
+ .name = "ehrpwm.2",
+ .mpu_irqs = am33xx_ehrpwm2_irqs,
+ .class = &am33xx_epwmss_hwmod_class,
+ .main_clk = "epwmss2_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_ehrpwm2_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_ehrpwm2_slaves),
+ .opt_clks = ehrpwm2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(ehrpwm2_opt_clks),
+};
+
+/* ecap0 */
+static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
+ { .irq = 31 },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
+/*
+ * Splitting the resources to handle access of PWMSS config space and module
+ * specific part independently
+ */
+ {
+ .pa_start = 0x48300000,
+ .pa_end = 0x48300000 + SZ_16 - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48300000 + SZ_256,
+ .pa_end = 0x48300000 + SZ_256 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_core__ecap0 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_ecap0_hwmod,
+ .addr = am33xx_ecap0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_ecap0_slaves[] = {
+ &am33xx_l4_core__ecap0,
+};
+
+static struct omap_hwmod am33xx_ecap0_hwmod = {
+ .name = "ecap.0",
+ .mpu_irqs = am33xx_ecap0_irqs,
+ .class = &am33xx_epwmss_hwmod_class,
+ .main_clk = "epwmss0_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_ecap0_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_ecap0_slaves),
+};
+
+/* ecap1 */
+static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
+ { .irq = 47 },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
+/*
+ * Splitting the resources to handle access of PWMSS config space and module
+ * specific part independently
+ */
+ {
+ .pa_start = 0x48302000,
+ .pa_end = 0x48302000 + SZ_16 - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48302000 + SZ_256,
+ .pa_end = 0x48302000 + SZ_256 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_core__ecap1 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_ecap1_hwmod,
+ .addr = am33xx_ecap1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_ecap1_slaves[] = {
+ &am33xx_l4_core__ecap1,
+};
+
+static struct omap_hwmod am33xx_ecap1_hwmod = {
+ .name = "ecap.1",
+ .mpu_irqs = am33xx_ecap1_irqs,
+ .class = &am33xx_epwmss_hwmod_class,
+ .main_clk = "epwmss1_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_ecap1_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_ecap1_slaves),
+};
+
+/* ecap2 */
+static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
{ .irq = 61 },
{ .irq = -1 }
};
-struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
+struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
+/*
+ * Splitting the resources to handle access of PWMSS config space and module
+ * specific part independently
+ */
{
.pa_start = 0x48304000,
- .pa_end = 0x48304000 + SZ_4K - 1,
+ .pa_end = 0x48304000 + SZ_16 - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT
+ },
+ {
+ .pa_start = 0x48304000 + SZ_256,
+ .pa_end = 0x48304000 + SZ_256 + SZ_256 - 1,
.flags = ADDR_TYPE_RT
},
{ }
};
-struct omap_hwmod_ocp_if am33xx_l4_core__epwmss2 = {
+struct omap_hwmod_ocp_if am33xx_l4_core__ecap2 = {
.master = &am33xx_l4per_hwmod,
- .slave = &am33xx_epwmss2_hwmod,
- .addr = am33xx_epwmss2_addr_space,
+ .slave = &am33xx_ecap2_hwmod,
+ .addr = am33xx_ecap2_addr_space,
.user = OCP_USER_MPU,
};
-static struct omap_hwmod_ocp_if *am33xx_epwmss2_slaves[] = {
- &am33xx_l4_core__epwmss2,
+static struct omap_hwmod_ocp_if *am33xx_ecap2_slaves[] = {
+ &am33xx_l4_core__ecap2,
};
-static struct omap_hwmod am33xx_epwmss2_hwmod = {
- .name = "epwmss2",
+static struct omap_hwmod am33xx_ecap2_hwmod = {
+ .name = "ecap.2",
+ .mpu_irqs = am33xx_ecap2_irqs,
.class = &am33xx_epwmss_hwmod_class,
.clkdm_name = "l4ls_clkdm",
- .mpu_irqs = am33xx_epwmss2_irqs,
.main_clk = "epwmss2_fck",
.prcm = {
.omap4 = {
.modulemode = MODULEMODE_SWCTRL,
},
},
- .slaves = am33xx_epwmss2_slaves,
- .slaves_cnt = ARRAY_SIZE(am33xx_epwmss2_slaves),
+ .slaves = am33xx_ecap2_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_ecap2_slaves),
};
static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0114,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1,
.clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = am33xx_gpio0_irqs,
.main_clk = "gpio0_ick",
- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET | HWMOD_INIT_NO_RESET,
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
.sysc_offs = 0x10,
.syss_offs = 0x14,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_MIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
},
.slaves = am33xx_gpmc_slaves,
.slaves_cnt = ARRAY_SIZE(am33xx_gpmc_slaves),
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+ HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
};
/* 'i2c' class */
};
static struct omap_i2c_dev_attr i2c_dev_attr = {
- .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+ .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
+ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
};
static struct omap_hwmod_class i2c_class = {
},
.slaves = am33xx_lcdc_slaves,
.slaves_cnt = ARRAY_SIZE(am33xx_lcdc_slaves),
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
};
/*
};
/* 'mcasp' class */
+
+static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x4,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
- .name = "mcasp",
+ .name = "mcasp",
+ .sysc = &am33xx_mcasp_sysc,
};
/* mcasp0 */
{ .irq = -1 }
};
+static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
+ { .name = "tx", .dma_req = AM33XX_DMA_MCASP0_X, },
+ { .name = "rx", .dma_req = AM33XX_DMA_MCASP0_R, },
+ { .dma_req = -1 }
+};
+
static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
{
.pa_start = 0x48038000,
.class = &am33xx_mcasp_hwmod_class,
.clkdm_name = "l3s_clkdm",
.mpu_irqs = am33xx_mcasp0_irqs,
+ .sdma_reqs = am33xx_mcasp0_edma_reqs,
.main_clk = "mcasp0_fck",
.prcm = {
.omap4 = {
{ .irq = -1 }
};
+static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
+ { .name = "tx", .dma_req = AM33XX_DMA_MCASP1_X, },
+ { .name = "rx", .dma_req = AM33XX_DMA_MCASP1_R, },
+ { .dma_req = -1 }
+};
+
+
static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
{
.pa_start = 0x4803C000,
.class = &am33xx_mcasp_hwmod_class,
.clkdm_name = "l3s_clkdm",
.mpu_irqs = am33xx_mcasp1_irqs,
+ .sdma_reqs = am33xx_mcasp1_edma_reqs,
.main_clk = "mcasp1_fck",
.prcm = {
.omap4 = {
};
static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
- { .irq = 108 },
+ { .irq = AM33XX_IRQ_SHAEIP57t0_P },
{ .irq = -1 }
};
+static struct omap_hwmod_dma_info am33xx_sha0_dma[] = {
+ { .dma_req = AM33XX_DMA_SHAEIP57T0_DIN },
+ { .dma_req = -1 }
+};
+
static struct omap_hwmod am33xx_sha0_hwmod = {
.name = "sha0",
.class = &am33xx_sha0_hwmod_class,
.clkdm_name = "l3_clkdm",
.mpu_irqs = am33xx_sha0_irqs,
+ .sdma_reqs = am33xx_sha0_dma,
.main_clk = "sha0_fck",
.prcm = {
.omap4 = {
},
.slaves = am33xx_timer0_slaves,
.slaves_cnt = ARRAY_SIZE(am33xx_timer0_slaves),
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
};
/* timer1 1ms */
},
.slaves = am33xx_tptc0_slaves,
.slaves_cnt = ARRAY_SIZE(am33xx_tptc0_slaves),
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
};
/* tptc1 */
},
.slaves = am33xx_tptc1_slaves,
.slaves_cnt = ARRAY_SIZE(am33xx_tptc1_slaves),
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
};
/* tptc2 */
},
.slaves = am33xx_tptc2_slaves,
.slaves_cnt = ARRAY_SIZE(am33xx_tptc2_slaves),
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
};
/* 'uart' class */
.omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
.rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
+ .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
},
.slaves = am33xx_usbss_slaves,
.slaves_cnt = ARRAY_SIZE(am33xx_usbss_slaves),
+ .class = &am33xx_usbotg_class,
+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
};
/* gfx */
};
static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
- { .name = "gfx", .rst_shift = 0 },
+ { .name = "gfx", .rst_shift = 0, .st_shift = 0 },
};
static struct omap_hwmod am33xx_gfx_hwmod = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
.rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
+ .rstst_offs = AM33XX_RM_GFX_RSTST_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
.rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
+ .rstst_offs = AM33XX_RM_PER_RSTST_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
};
+/**
+ * HWMOD data for devices accessible across GP and HS/EMU devices.
+ */
static __initdata struct omap_hwmod *am33xx_hwmods[] = {
/* l3 class */
&am33xx_l3_instr_hwmod,
/* emif_fw class */
&am33xx_emif_fw_hwmod,
/* epwmss class */
- &am33xx_epwmss0_hwmod,
- &am33xx_epwmss1_hwmod,
- &am33xx_epwmss2_hwmod,
+ &am33xx_ehrpwm0_hwmod,
+ &am33xx_ehrpwm1_hwmod,
+ &am33xx_ehrpwm2_hwmod,
+ &am33xx_ecap0_hwmod,
+ &am33xx_ecap1_hwmod,
+ &am33xx_ecap2_hwmod,
/* gpio class */
&am33xx_gpio0_hwmod,
&am33xx_gpio1_hwmod,
&am33xx_uart5_hwmod,
&am33xx_uart6_hwmod,
/* timer class */
- &am33xx_timer0_hwmod,
&am33xx_timer1_hwmod,
&am33xx_timer2_hwmod,
&am33xx_timer3_hwmod,
&am33xx_usbss_hwmod,
/* cpgmac0 class */
&am33xx_cpgmac0_hwmod,
+ /* mdio class */
+ &am33xx_mdio_hwmod,
/* tptc class */
&am33xx_tptc0_hwmod,
&am33xx_tptc1_hwmod,
NULL,
};
+
+/**
+ * HWMOD data for devices common accessible only on GP devices.
+ */
+static __initdata struct omap_hwmod *am33xx_hwmods_gp[] = {
+ /* timer class */
+ &am33xx_timer0_hwmod,
+ NULL,
+};
+
int __init am33xx_hwmod_init(void)
{
- return omap_hwmod_register(am33xx_hwmods);
+ int ret = omap_hwmod_register(am33xx_hwmods);
+
+ if (!ret && (OMAP2_DEVICE_TYPE_GP == omap_type()))
+ ret = omap_hwmod_register(am33xx_hwmods_gp);
+
+ return ret;
}