diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index c8fe4334fdba0e6b5a2d734e751aebad3b2ef437..ceaf244bf1859924c0f028c23c94453ed6be4701 100644 (file)
#include <linux/io.h>
#include <plat/omap_hwmod.h>
+#include <plat/i2c.h>
#include <plat/cpu.h>
#include <plat/gpio.h>
#include <plat/dma.h>
#include "omap_hwmod_common_data.h"
#include "control.h"
#include "cm33xx.h"
+#include "prm33xx.h"
/* Backward references (IPs with Bus Master capability) */
static struct omap_hwmod am33xx_mpu_hwmod;
+static struct omap_hwmod am33xx_l3_main_hwmod;
static struct omap_hwmod am33xx_l3slow_hwmod;
static struct omap_hwmod am33xx_l4wkup_hwmod;
static struct omap_hwmod am33xx_l4per_hwmod;
static struct omap_hwmod am33xx_gpio3_hwmod;
static struct omap_hwmod am33xx_i2c1_hwmod;
static struct omap_hwmod am33xx_i2c2_hwmod;
+static struct omap_hwmod am33xx_i2c3_hwmod;
static struct omap_hwmod am33xx_usbss_hwmod;
static struct omap_hwmod am33xx_mmc0_hwmod;
static struct omap_hwmod am33xx_mmc1_hwmod;
static struct omap_hwmod am33xx_spi0_hwmod;
static struct omap_hwmod am33xx_spi1_hwmod;
static struct omap_hwmod am33xx_elm_hwmod;
+static struct omap_hwmod am33xx_adc_tsc_hwmod;
+static struct omap_hwmod am33xx_tpcc_hwmod;
+static struct omap_hwmod am33xx_mcasp0_hwmod;
+static struct omap_hwmod am33xx_mcasp1_hwmod;
+static struct omap_hwmod am33xx_epwmss0_hwmod;
+static struct omap_hwmod am33xx_epwmss1_hwmod;
+static struct omap_hwmod am33xx_epwmss2_hwmod;
+static struct omap_hwmod am33xx_gpmc_hwmod;
+static struct omap_hwmod am33xx_lcdc_hwmod;
/*
* Interconnects hwmod structures
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* L4 WKUP -> ADC_TSC */
+static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
+ {
+ .pa_start = AM33XX_TSC_BASE,
+ .pa_end = AM33XX_TSC_BASE + SZ_8K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_wkup_adc_tsc = {
+ .master = &am33xx_l4wkup_hwmod,
+ .slave = &am33xx_adc_tsc_hwmod,
+ .addr = am33xx_adc_tsc_addrs,
+ .user = OCP_USER_MPU,
+};
+
/* Master interfaces on the L4_WKUP interconnect */
static struct omap_hwmod_ocp_if *am33xx_l4_wkup_masters[] = {
&am33xx_l4_wkup__gpio0,
};
/* 'adc_tsc' class */
+static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
+ .rev_offs = 0x00,
+ .sysc_offs = 0x10,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO |
+ SIDLE_SMART | SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
.name = "adc_tsc",
+ .sysc = &am33xx_adc_tsc_sysc,
};
/* adc_tsc */
{ .irq = -1 }
};
+static struct omap_hwmod_ocp_if *am33xx_adc_tsc_slaves[] = {
+ &am33xx_l4_wkup_adc_tsc,
+};
+
static struct omap_hwmod am33xx_adc_tsc_hwmod = {
.name = "adc_tsc",
.class = &am33xx_adc_tsc_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .flags = HWMOD_INIT_NO_RESET | HWMOD_INIT_NO_IDLE,
+ .slaves = am33xx_adc_tsc_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_adc_tsc_slaves),
};
/* 'aes' class */
.flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
};
-/* 'cpgmac0' class */
+static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x8,
+ .syss_offs = 0x4,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE
+ | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO |
+ MSTANDBY_FORCE | MSTANDBY_NO),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+/* 'cpgmac' class */
static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
.name = "cpgmac0",
+ .sysc = &am33xx_cpgmac_sysc,
+};
+
+/* cpgmac0 - has 4 IRQs */
+#if 0
+static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
+ { .irq = AM33XX_IRQ_TPTC0 },
+ { .irq = -1 }
+};
+#endif
+
+struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
+ {
+ .pa_start = AM33XX_CPSW_SS_BASE,
+ .pa_end = AM33XX_CPSW_SS_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__cpgmac0 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_cpgmac0_hwmod,
+ .addr = am33xx_cpgmac0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_cpgmac0_slaves[] = {
+ &am33xx_l3_main__cpgmac0,
};
/* cpgmac0 */
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .slaves = am33xx_cpgmac0_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_cpgmac0_slaves),
};
/* 'dcan' class */
.sysc_offs = 0x0010,
.syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
};
/* 'epwmss' class */
+static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
.name = "epwmss",
+ .sysc = &am33xx_epwmss_sysc,
};
/* epwmss0 */
+static struct omap_hwmod_irq_info am33xx_epwmss0_irqs[] = {
+ { .irq = AM33XX_IRQ_PWMSS0_EPWM },
+ { .irq = AM33XX_IRQ_PWMSS0 },
+ { .irq = AM33XX_IRQ_PWMSS0_ECAP },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
+ {
+ .pa_start = AM33XX_EPWMSS0_BASE,
+ .pa_end = AM33XX_EPWMSS0_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_core__epwmss0 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_epwmss0_hwmod,
+ .addr = am33xx_epwmss0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_epwmss0_slaves[] = {
+ &am33xx_l4_core__epwmss0,
+};
+
static struct omap_hwmod am33xx_epwmss0_hwmod = {
.name = "epwmss0",
+ .mpu_irqs = am33xx_epwmss0_irqs,
.class = &am33xx_epwmss_hwmod_class,
.main_clk = "epwmss0_fck",
.clkdm_name = "l4ls_clkdm",
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .slaves = am33xx_epwmss0_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_epwmss0_slaves),
};
/* epwmss1 */
+static struct omap_hwmod_irq_info am33xx_epwmss1_irqs[] = {
+ { .irq = AM33XX_IRQ_PWMSS1_EPWM },
+ { .irq = AM33XX_IRQ_PWMSS1 },
+ { .irq = AM33XX_IRQ_PWMSS1_ECAP },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
+ {
+ .pa_start = AM33XX_EPWMSS1_BASE,
+ .pa_end = AM33XX_EPWMSS1_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_core__epwmss1 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_epwmss1_hwmod,
+ .addr = am33xx_epwmss1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_epwmss1_slaves[] = {
+ &am33xx_l4_core__epwmss1,
+};
+
static struct omap_hwmod am33xx_epwmss1_hwmod = {
.name = "epwmss1",
+ .mpu_irqs = am33xx_epwmss1_irqs,
.class = &am33xx_epwmss_hwmod_class,
.main_clk = "epwmss1_fck",
.clkdm_name = "l4ls_clkdm",
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .slaves = am33xx_epwmss1_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_epwmss1_slaves),
};
/* epwmss2 */
+static struct omap_hwmod_irq_info am33xx_epwmss2_irqs[] = {
+ { .irq = AM33XX_IRQ_PWMSS2_EPWM },
+ { .irq = AM33XX_IRQ_PWMSS2 },
+ { .irq = AM33XX_IRQ_PWMSS2_ECAP },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
+ {
+ .pa_start = AM33XX_EPWMSS2_BASE,
+ .pa_end = AM33XX_EPWMSS2_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l4_core__epwmss2 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_epwmss2_hwmod,
+ .addr = am33xx_epwmss2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_epwmss2_slaves[] = {
+ &am33xx_l4_core__epwmss2,
+};
+
static struct omap_hwmod am33xx_epwmss2_hwmod = {
.name = "epwmss2",
+ .mpu_irqs = am33xx_epwmss2_irqs,
.class = &am33xx_epwmss_hwmod_class,
.main_clk = "epwmss2_fck",
.clkdm_name = "l4ls_clkdm",
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .slaves = am33xx_epwmss2_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_epwmss2_slaves),
};
static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x0010,
.syss_offs = 0x0114,
- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSS_HAS_RESET_STATUS),
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
+ SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio0_dbclk" },
+ { .role = "fclk", .clk = "gpio0_fck" },
};
/* gpio0 */
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbclk" },
+ { .role = "fclk", .clk = "gpio1_fck" },
};
static struct omap_hwmod am33xx_gpio1_hwmod = {
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio2_dbclk" },
+ { .role = "fclk", .clk = "gpio2_fck" },
};
/* gpio2 */
.clkdm_name = "l4ls_clkdm",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+ .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio3_dbclk" },
+ { .role = "fclk", .clk = "gpio3_fck" },
};
/* gpio3 */
.clkdm_name = "l4ls_clkdm",
.prcm = {
.omap4 = {
- .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
+ .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
/* 'gpmc' class */
+static struct omap_hwmod_class_sysconfig gpmc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .syss_offs = 0x14,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_MIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type4,
+};
+
+struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
+ {
+ .pa_start = 0x50000000,
+ .pa_end = 0x50000000 + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__gpmc = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_gpmc_hwmod,
+ .addr = am33xx_gpmc_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_gpmc_slaves[] = {
+ &am33xx_l3_main__gpmc,
+};
static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
.name = "gpmc",
+ .sysc = &gpmc_sysc,
};
/* gpmc */
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .slaves = am33xx_gpmc_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_gpmc_slaves),
};
/* 'i2c' class */
.class = &i2c_class,
};
+/* i2c3 */
+/* l4 per -> i2c3 */
+static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
+ {
+ .pa_start = AM33XX_I2C2_BASE,
+ .pa_end = AM33XX_I2C2_BASE + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am335_l4_per_i2c3 = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_i2c3_hwmod,
+ .addr = am33xx_i2c3_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
+ { .irq = AM33XX_IRQ_MSHSI2COCP2 },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
+ { .name = "tx", .dma_req = 0, },
+ { .name = "rx", .dma_req = 0, },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_ocp_if *am33xx_i2c3_slaves[] = {
+ &am335_l4_per_i2c3,
+};
+
+static struct omap_hwmod am33xx_i2c3_hwmod = {
+ .name = "i2c3",
+ .mpu_irqs = i2c3_mpu_irqs,
+ .sdma_reqs = i2c3_edma_reqs,
+ .main_clk = "i2c3_fck",
+ .clkdm_name = "l4ls_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .flags = HWMOD_16BIT_REG,
+ .dev_attr = &i2c_dev_attr,
+ .slaves = am33xx_i2c3_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_i2c3_slaves),
+ .class = &i2c_class,
+};
+
/* 'icss' class */
static struct omap_hwmod_class am33xx_icss_hwmod_class = {
.name = "icss",
},
};
+static struct omap_hwmod_class_sysconfig lcdc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x54,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
/* 'lcdc' class */
static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
.name = "lcdc",
+ .sysc = &lcdc_sysc,
};
/* lcdc */
{ .irq = -1 }
};
+struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
+ {
+ .pa_start = 0x4830E000,
+ .pa_end = 0x4830E000 + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_lcdc_hwmod,
+ .addr = am33xx_lcdc_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_lcdc_slaves[] = {
+ &am33xx_l3_main__lcdc,
+};
+
static struct omap_hwmod am33xx_lcdc_hwmod = {
.name = "lcdc",
.class = &am33xx_lcdc_hwmod_class,
.mpu_irqs = am33xx_lcdc_irqs,
.main_clk = "lcdc_fck",
.clkdm_name = "lcdc_clkdm",
- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .slaves = am33xx_lcdc_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_lcdc_slaves),
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
+ .name = "mailbox",
+ .sysc = &am33xx_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod am33xx_mailbox_hwmod;
+static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
+ { .irq = AM33XX_IRQ_MAILBOX },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
+ {
+ .pa_start = AM33XX_MAILBOX0_BASE,
+ .pa_end = AM33XX_MAILBOX0_BASE + (SZ_4K - 1),
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> mailbox */
+static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_mailbox_hwmod,
+ .addr = am33xx_mailbox_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
+ &am33xx_l4_per__mailbox,
+};
+
+static struct omap_hwmod am33xx_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &am33xx_mailbox_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_mailbox_irqs,
+ .main_clk = "mailbox0_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_mailbox_slaves),
};
/* 'mcasp' class */
/* mcasp0 */
static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
- { .irq = 80 },
+ { .name = "ax", .irq = AM33XX_IRQ_MCASP0_AX, },
+ { .name = "ar", .irq = AM33XX_IRQ_MCASP0_AR, },
{ .irq = -1 }
};
+static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
+ {
+ .pa_start = AM33XX_ASP0_BASE,
+ .pa_end = AM33XX_ASP0_BASE + (SZ_1K * 12) - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp0 = {
+ .master = &am33xx_l3slow_hwmod,
+ .slave = &am33xx_mcasp0_hwmod,
+ .clk = "mcasp0_ick",
+ .addr = am33xx_mcasp0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_mcasp0_slaves[] = {
+ &am33xx_l3_slow__mcasp0,
+};
+
static struct omap_hwmod am33xx_mcasp0_hwmod = {
.name = "mcasp0",
.class = &am33xx_mcasp_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .slaves = am33xx_mcasp0_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_mcasp0_slaves),
+};
+
+/* mcasp1 */
+static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
+ { .name = "ax", .irq = AM33XX_IRQ_MCASP1_AX, },
+ { .name = "ar", .irq = AM33XX_IRQ_MCASP1_AR, },
+ { .irq = -1 }
};
+static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
+ {
+ .pa_start = AM33XX_ASP1_BASE,
+ .pa_end = AM33XX_ASP1_BASE + (SZ_1K * 12) - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_slow__mcasp1 = {
+ .master = &am33xx_l3slow_hwmod,
+ .slave = &am33xx_mcasp1_hwmod,
+ .clk = "mcasp1_ick",
+ .addr = am33xx_mcasp1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_mcasp1_slaves[] = {
+ &am33xx_l3_slow__mcasp1,
+};
+
+static struct omap_hwmod am33xx_mcasp1_hwmod = {
+ .name = "mcasp1",
+ .class = &am33xx_mcasp_hwmod_class,
+ .mpu_irqs = am33xx_mcasp1_irqs,
+ .main_clk = "mcasp1_fck",
+ .clkdm_name = "l3s_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_mcasp1_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_mcasp1_slaves),
+};
+
+
/* 'mmc' class */
static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
{ .dma_req = -1 }
};
-static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
- { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
- { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
- { .dma_req = -1 }
-};
-
static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
{
.pa_start = AM33XX_MMC2_BASE,
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
};
/* 'ocpwp' class */
.mpu_irqs = am33xx_rtc_irqs,
.main_clk = "rtc_fck",
.clkdm_name = "l4_rtc_clkdm",
- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), /* ??? */
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
/* tpcc */
static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
- { .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
+ { .name = "edma0", .irq = AM33XX_IRQ_TPCC0_INT_PO0 },
+ { .name = "edma0_err", .irq = AM33XX_IRQ_TPCC0_ERRINT_PO },
{ .irq = -1 },
};
+/* TODO move this appropriate header. */
+#define AM33XX_TPCC_BASE 0x49000000
+
+static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
+ {
+ .pa_start = AM33XX_TPCC_BASE,
+ .pa_end = AM33XX_TPCC_BASE + SZ_32K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+static struct omap_hwmod_ocp_if am33xx_l3_slow__tpcc = {
+ .master = &am33xx_l3slow_hwmod,
+ .slave = &am33xx_tpcc_hwmod,
+ .addr = am33xx_tpcc_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_tpcc_slaves[] = {
+ &am33xx_l3_slow__tpcc,
+};
+
static struct omap_hwmod am33xx_tpcc_hwmod = {
.name = "tpcc",
.class = &am33xx_tpcc_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .slaves = am33xx_tpcc_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_tpcc_slaves),
+};
+
+static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
+ .rev_offs = 0x0,
+ .sysc_offs = 0x10,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
+ .sysc_fields = &omap_hwmod_sysc_type2,
};
/* 'tptc' class */
static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
.name = "tptc",
+ .sysc = &am33xx_tptc_sysc,
};
/* tptc0 */
{ .irq = -1 }
};
+struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
+ {
+ .pa_start = 0x49800000,
+ .pa_end = 0x49800000 + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tptc0_hwmod,
+ .addr = am33xx_tptc0_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_tptc0_slaves[] = {
+ &am33xx_l3_main__tptc0,
+};
+
static struct omap_hwmod am33xx_tptc0_hwmod = {
.name = "tptc0",
.class = &am33xx_tptc_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .slaves = am33xx_tptc0_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_tptc0_slaves),
};
/* tptc1 */
{ .irq = -1 }
};
+struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
+ {
+ .pa_start = 0x49900000,
+ .pa_end = 0x49900000 + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tptc1_hwmod,
+ .addr = am33xx_tptc1_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_tptc1_slaves[] = {
+ &am33xx_l3_main__tptc1,
+};
+
static struct omap_hwmod am33xx_tptc1_hwmod = {
.name = "tptc1",
.class = &am33xx_tptc_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .slaves = am33xx_tptc1_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_tptc1_slaves),
};
/* tptc2 */
{ .irq = -1 }
};
+struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
+ {
+ .pa_start = 0x49a00000,
+ .pa_end = 0x49a00000 + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
+ .master = &am33xx_l3_main_hwmod,
+ .slave = &am33xx_tptc2_hwmod,
+ .addr = am33xx_tptc2_addr_space,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_tptc2_slaves[] = {
+ &am33xx_l3_main__tptc2,
+};
+
static struct omap_hwmod am33xx_tptc2_hwmod = {
.name = "tptc2",
.class = &am33xx_tptc_hwmod_class,
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .slaves = am33xx_tptc2_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_tptc2_slaves),
};
/* 'uart' class */
.sysc_flags = (SYSC_HAS_SIDLEMODE |
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1,
};
};
/* uart3 */
+static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
+ { .name = "tx", .dma_req = 30, },
+ { .name = "rx", .dma_req = 31, },
+ { .dma_req = -1 }
+};
+
static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
{
.pa_start = AM33XX_UART3_BASE,
.mpu_irqs = am33xx_uart3_irqs,
.main_clk = "uart3_fck",
.clkdm_name = "l4ls_clkdm",
- .sdma_reqs = uart1_edma_reqs,
+ .sdma_reqs = uart3_edma_reqs,
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
.name = "wkup_m3",
};
+static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
+ { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
+};
+
/* wkup_m3 */
static struct omap_hwmod am33xx_wkup_m3_hwmod = {
.name = "wkup_m3",
.class = &am33xx_wkup_m3_hwmod_class,
.clkdm_name = "l4_wkup_aon_clkdm",
.main_clk = "wkup_m3_fck",
+ .rst_lines = am33xx_wkup_m3_resets,
+ .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
.prcm = {
.omap4 = {
.clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
+ .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
+ .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
};
/* L3 SLOW -> USBSS interface */
static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x10,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type4,
};
static struct omap_hwmod_class am33xx_usbotg_class = {
/* i2c class */
&am33xx_i2c1_hwmod,
&am33xx_i2c2_hwmod,
+ &am33xx_i2c3_hwmod,
/* icss class */
&am33xx_icss_hwmod,
/* ieee5000 class */
&am33xx_ieee5000_hwmod,
+ /* mailbox class */
+ &am33xx_mailbox_hwmod,
/* mcasp class */
&am33xx_mcasp0_hwmod,
+ &am33xx_mcasp1_hwmod,
/* mmc class */
&am33xx_mmc0_hwmod,
&am33xx_mmc1_hwmod,
&am33xx_ocmcram_hwmod,
/* ocpwp class */
&am33xx_ocpwp_hwmod,
- /* rtc class */
-#if 0
- &am33xx_rtc_hwmod,
-#endif
/* sha0 class */
&am33xx_sha0_hwmod,
/* smartreflex class */