index 67ec84c34b5ed6475ccecf545bf07fcdbf2c7240..3a00eaa96dd489261013259c51536d27bfb36c09 100644 (file)
int ipc_data1;
int ipc_data2;
} am33xx_lp_ipc;
int ipc_data1;
int ipc_data2;
} am33xx_lp_ipc;
+
+struct am33xx_padconf {
+ int mii1_col;
+ int mii1_crs;
+ int mii1_rxerr;
+ int mii1_txen;
+ int mii1_rxdv;
+ int mii1_txd3;
+ int mii1_txd2;
+ int mii1_txd1;
+ int mii1_txd0;
+ int mii1_txclk;
+ int mii1_rxclk;
+ int mii1_rxd3;
+ int mii1_rxd2;
+ int mii1_rxd1;
+ int mii1_rxd0;
+ int rmii1_refclk;
+ int mdio_data;
+ int mdio_clk;
+};
#endif /* ASSEMBLER */
#define M3_TXEV_EOI (AM33XX_CTRL_BASE + 0x1324)
#define A8_M3_IPC_REGS (AM33XX_CTRL_BASE + 0x1328)
#endif /* ASSEMBLER */
#define M3_TXEV_EOI (AM33XX_CTRL_BASE + 0x1324)
#define A8_M3_IPC_REGS (AM33XX_CTRL_BASE + 0x1328)
-#define DS_RESUME_ADDR 0x40300220
+#define DS_RESUME_ADDR 0x40300340
#define DS_IPC_DEFAULT 0xffffffff
#define M3_UMEM 0x44D00000
#define DS_IPC_DEFAULT 0xffffffff
#define M3_UMEM 0x44D00000