ARM: OMAP: AM33XX: Low power optimizations

[sitara-epos/sitara-epos-kernel.git] / arch / arm / mach-omap2 / pm33xx.h

diff --git a/arch/arm/mach-omap2/pm33xx.h b/arch/arm/mach-omap2/pm33xx.h
index f77b42ce976ad7ed2374c78b16ac05da8c4b6356..3a00eaa96dd489261013259c51536d27bfb36c09 100644 (file)
--- a/arch/arm/mach-omap2/pm33xx.h
+++ b/arch/arm/mach-omap2/pm33xx.h
@@ -15,17 +15,51 @@
 
 #ifndef __ASSEMBLER__
 extern void __iomem *am33xx_get_ram_base(void);
+
+struct a8_wkup_m3_ipc_data {
+       int resume_addr;
+       int sleep_mode;
+       int ipc_data1;
+       int ipc_data2;
+} am33xx_lp_ipc;
+
+struct am33xx_padconf {
+       int     mii1_col;
+       int     mii1_crs;
+       int     mii1_rxerr;
+       int     mii1_txen;
+       int     mii1_rxdv;
+       int     mii1_txd3;
+       int     mii1_txd2;
+       int     mii1_txd1;
+       int     mii1_txd0;
+       int     mii1_txclk;
+       int     mii1_rxclk;
+       int     mii1_rxd3;
+       int     mii1_rxd2;
+       int     mii1_rxd1;
+       int     mii1_rxd0;
+       int     rmii1_refclk;
+       int     mdio_data;
+       int     mdio_clk;
+};
 #endif /* ASSEMBLER */
 
 #define M3_TXEV_EOI                    (AM33XX_CTRL_BASE + 0x1324)
 #define A8_M3_IPC_REGS                 (AM33XX_CTRL_BASE + 0x1328)
-#define DS_RESUME_ADDR                 0x403000A0
+#define DS_RESUME_ADDR                 0x40300340
 #define DS_IPC_DEFAULT                 0xffffffff
 #define M3_UMEM                                0x44D00000
 
 #define        DS0_ID                          0x3
 #define DS1_ID                         0x5
 
+#define M3_STATE_UNKNOWN               -1
+#define M3_STATE_RESET                 0
+#define M3_STATE_INITED                        1
+#define M3_STATE_MSG_FOR_LP            2
+#define M3_STATE_MSG_FOR_RESET         3
+
 /* DDR offsets */
 #define DDR_CMD0_IOCTRL                        (AM33XX_CTRL_BASE + 0x1404)
 #define DDR_CMD1_IOCTRL                        (AM33XX_CTRL_BASE + 0x1408)