author | Patil, Rachna <rachna@ti.com> | |
Mon, 23 Jan 2012 11:26:59 +0000 (16:56 +0530) | ||
committer | Patil, Rachna <rachna@ti.com> | |
Thu, 2 Feb 2012 08:03:48 +0000 (13:33 +0530) | ||
commit | 0e82a6b311ae038dc03f5291c93b42747762dbd7 | |
tree | 3e73f017c1f3518d99012331b171c4ad2923a005 | tree | snapshot (tar.xz tar.gz zip) |
parent | f6a997a1edfc019eb40334f5a11febed345d5752 | commit | diff |
arm: omap: am33xx: update TSC hwmod data
Sysconfig register bits are updated for TSC
hwmod. TSC supports idle mode at bit position 2&3,
hence following omap4 IP's.
Signed-off-by: Patil, Rachna <rachna@ti.com>
Sysconfig register bits are updated for TSC
hwmod. TSC supports idle mode at bit position 2&3,
hence following omap4 IP's.
Signed-off-by: Patil, Rachna <rachna@ti.com>
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | diff | blob | history |