author | Vaibhav Bedia <vaibhav.bedia@ti.com> | |
Wed, 14 Mar 2012 20:19:25 +0000 (01:49 +0530) | ||
committer | Vaibhav Bedia <vaibhav.bedia@ti.com> | |
Wed, 14 Mar 2012 20:19:25 +0000 (01:49 +0530) | ||
commit | 22a284d098501bf49aca4e6f824212035cf4d276 | |
tree | 1ecc760ee9785f81c1c87334b5a5b1731223c8bd | tree | snapshot (tar.xz tar.gz zip) |
parent | 4b5c2055213bf8b6d94cd1cd0f3ca798ee1df1b3 | commit | diff |
ARM: OMAP: AM33XX: NET: cpsw: Set SYSC for NO_IDLE and NO_STDBY
In a successful suspend-resume cycle the register context is
lost and hence SYSC will go back to its default value of
NO_IDLE and NO_STDBY. However, in a suspend failure/abort due
to some or the other reason, the register is set to
FORCE_IDLE and FORCE_STDBY but never cleared.
If the driver had been fully converted to HWMOD this would have
been taken care of in the generic code. For now, after enabling the
CPSW clock explicitly set the SYSC of CPSW to NO_IDLE and NO_STDBY.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
In a successful suspend-resume cycle the register context is
lost and hence SYSC will go back to its default value of
NO_IDLE and NO_STDBY. However, in a suspend failure/abort due
to some or the other reason, the register is set to
FORCE_IDLE and FORCE_STDBY but never cleared.
If the driver had been fully converted to HWMOD this would have
been taken care of in the generic code. For now, after enabling the
CPSW clock explicitly set the SYSC of CPSW to NO_IDLE and NO_STDBY.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
drivers/net/ethernet/ti/davinci_mdio.c | diff | blob | history |