ARM: OMAP: AM33XX: Add EMIF and DDR PHY register offsets and values
authorVaibhav Bedia <vaibhav.bedia@ti.com>
Tue, 17 Jan 2012 06:54:54 +0000 (12:24 +0530)
committerVaibhav Hiremath <hvaibhav@ti.com>
Mon, 23 Jan 2012 19:14:56 +0000 (00:44 +0530)
When coming out of low power state, the EMIF and DDR
PHY registers need to be restored to the old value.

A naive approach of storing the DDR PHY register values during
suspend and restoring it back during resume will not work
due to a silicon errata related to readback of the DDR PHY
registers.

EMIF registers values can be readback and stored but for
now we assume that the code is running on AM335x EVM with DDR2
which is configured to run @266MHz.

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
arch/arm/mach-omap2/pm33xx.h [new file with mode: 0644]
arch/arm/plat-omap/include/plat/emif.h

diff --git a/arch/arm/mach-omap2/pm33xx.h b/arch/arm/mach-omap2/pm33xx.h
new file mode 100644 (file)
index 0000000..830ad20
--- /dev/null
@@ -0,0 +1,108 @@
+/*
+ * AM33XX Power Management Routines
+ *
+ * Copyright (C) 2012 Texas Instruments Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PM33XX_H
+#define __ARCH_ARM_MACH_OMAP2_PM33XX_H
+
+#include <mach/hardware.h>     /* XXX Is this the right one to include? */
+
+#ifndef __ASSEMBLER__
+extern void __iomem *am33xx_get_ram_base(void);
+#endif /* ASSEMBLER */
+
+/* DDR offsets */
+#define DDR_CMD0_IOCTRL                        (AM33XX_CTRL_BASE + 0x1404)
+#define DDR_CMD1_IOCTRL                        (AM33XX_CTRL_BASE + 0x1408)
+#define DDR_CMD2_IOCTRL                        (AM33XX_CTRL_BASE + 0x140C)
+#define DDR_DATA0_IOCTRL               (AM33XX_CTRL_BASE + 0x1440)
+#define DDR_DATA1_IOCTRL               (AM33XX_CTRL_BASE + 0x1444)
+
+#define DDR_IO_CTRL                    (AM33XX_CTRL_BASE + 0x0E04)
+#define VTP0_CTRL_REG                  (AM33XX_CTRL_BASE + 0x0E0C)
+#define DDR_CKE_CTRL                   (AM33XX_CTRL_BASE + 0x131C)
+#define DDR_PHY_BASE_ADDR              (AM33XX_CTRL_BASE + 0x2000)
+
+#define CMD0_CTRL_SLAVE_RATIO_0                (DDR_PHY_BASE_ADDR + 0x01C)
+#define CMD0_CTRL_SLAVE_FORCE_0                (DDR_PHY_BASE_ADDR + 0x020)
+#define CMD0_CTRL_SLAVE_DELAY_0                (DDR_PHY_BASE_ADDR + 0x024)
+#define CMD0_DLL_LOCK_DIFF_0           (DDR_PHY_BASE_ADDR + 0x028)
+#define CMD0_INVERT_CLKOUT_0           (DDR_PHY_BASE_ADDR + 0x02C)
+
+#define CMD1_CTRL_SLAVE_RATIO_0                (DDR_PHY_BASE_ADDR + 0x050)
+#define CMD1_CTRL_SLAVE_FORCE_0                (DDR_PHY_BASE_ADDR + 0x054)
+#define CMD1_CTRL_SLAVE_DELAY_0                (DDR_PHY_BASE_ADDR + 0x058)
+#define CMD1_DLL_LOCK_DIFF_0           (DDR_PHY_BASE_ADDR + 0x05C)
+#define CMD1_INVERT_CLKOUT_0           (DDR_PHY_BASE_ADDR + 0x060)
+
+#define CMD2_CTRL_SLAVE_RATIO_0                (DDR_PHY_BASE_ADDR + 0x084)
+#define CMD2_CTRL_SLAVE_FORCE_0                (DDR_PHY_BASE_ADDR + 0x088)
+#define CMD2_CTRL_SLAVE_DELAY_0                (DDR_PHY_BASE_ADDR + 0x08C)
+#define CMD2_DLL_LOCK_DIFF_0           (DDR_PHY_BASE_ADDR + 0x090)
+#define CMD2_INVERT_CLKOUT_0           (DDR_PHY_BASE_ADDR + 0x094)
+
+#define DATA0_RD_DQS_SLAVE_RATIO_0     (DDR_PHY_BASE_ADDR + 0x0C8)
+#define DATA0_RD_DQS_SLAVE_RATIO_1     (DDR_PHY_BASE_ADDR + 0x0CC)
+
+#define DATA0_WR_DQS_SLAVE_RATIO_0     (DDR_PHY_BASE_ADDR + 0x0DC)
+#define DATA0_WR_DQS_SLAVE_RATIO_1     (DDR_PHY_BASE_ADDR + 0x0E0)
+
+#define DATA0_WRLVL_INIT_RATIO_0       (DDR_PHY_BASE_ADDR + 0x0F0)
+#define DATA0_WRLVL_INIT_RATIO_1       (DDR_PHY_BASE_ADDR + 0x0F4)
+
+#define DATA0_GATELVL_INIT_RATIO_0     (DDR_PHY_BASE_ADDR + 0x0FC)
+#define DATA0_GATELVL_INIT_RATIO_1     (DDR_PHY_BASE_ADDR + 0x100)
+
+#define DATA0_FIFO_WE_SLAVE_RATIO_0    (DDR_PHY_BASE_ADDR + 0x108)
+#define DATA0_FIFO_WE_SLAVE_RATIO_1    (DDR_PHY_BASE_ADDR + 0x10C)
+
+#define DATA0_WR_DATA_SLAVE_RATIO_0    (DDR_PHY_BASE_ADDR + 0x120)
+#define DATA0_WR_DATA_SLAVE_RATIO_1    (DDR_PHY_BASE_ADDR + 0x124)
+
+#define DATA0_DLL_LOCK_DIFF_0          (DDR_PHY_BASE_ADDR + 0x138)
+
+#define DATA0_RANK0_DELAYS_0           (DDR_PHY_BASE_ADDR + 0x134)
+#define DATA1_RANK0_DELAYS_0           (DDR_PHY_BASE_ADDR + 0x1D8)
+
+/* Temp placeholder for the values we want in the registers */
+#define EMIF_READ_LATENCY      0x04
+#define EMIF_TIM1              0x0666B3D6
+#define EMIF_TIM2              0x143731DA
+#define EMIF_TIM3              0x00000347
+#define EMIF_SDCFG             0x43805332
+#define EMIF_SDREF             0x0000081a
+#define EMIF_SDMGT             0x80000000
+#define EMIF_SDRAM             0x00004650
+#define EMIF_PHYCFG            0x2
+
+#define DDR2_DLL_LOCK_DIFF     0x0
+#define DDR2_RD_DQS            0x12
+#define DDR2_PHY_FIFO_WE       0x80
+
+#define DDR_PHY_RESET          (0x1 << 10)
+#define DDR_PHY_READY          (0x1 << 2)
+#define DDR2_RATIO             0x80
+#define CMD_FORCE              0x00
+#define CMD_DELAY              0x00
+
+#define DDR2_INVERT_CLKOUT     0x00
+#define DDR2_WR_DQS            0x00
+#define DDR2_PHY_WRLVL         0x00
+#define DDR2_PHY_GATELVL       0x00
+#define DDR2_PHY_WR_DATA       0x40
+#define PHY_RANK0_DELAY                0x01
+#define PHY_DLL_LOCK_DIFF      0x0
+#define DDR_IOCTRL_VALUE       0x18B
+
+#define VTP_CTRL_READY         (0x1 << 5)
+#define VTP_CTRL_ENABLE                (0x1 << 6)
+#define VTP_CTRL_LOCK_EN       (0x1 << 4)
+#define VTP_CTRL_START_EN      (0x1)
+
+#endif
index e1b39d6078dc862dbb588b92d47752b7c3c3566f..314c1264a493db5c7fa6ba7e6f99a21d742d1216 100644 (file)
 #ifndef __EMIF_H
 #define __EMIF_H
 
 #ifndef __EMIF_H
 #define __EMIF_H
 
-#ifndef __ASSEMBLER__
-extern void __iomem *am33xx_get_ram_base(void);
-#endif /* ASSEMBLER */
-
 #define EMIF_MOD_ID_REV                        (0x0)
 #define EMIF4_0_SDRAM_STATUS            (0x04)
 #define EMIF4_0_SDRAM_CONFIG            (0x08)
 #define EMIF_MOD_ID_REV                        (0x0)
 #define EMIF4_0_SDRAM_STATUS            (0x04)
 #define EMIF4_0_SDRAM_CONFIG            (0x08)