ARM: OMAP2+: epwm: Time base clock tree node.
authorPhilip, Avinash <avinashphilip@ti.com>
Sat, 10 Mar 2012 11:29:55 +0000 (16:59 +0530)
committerPhilip, Avinash <avinashphilip@ti.com>
Tue, 13 Mar 2012 11:02:29 +0000 (16:32 +0530)
pwmssctrl register (in control module) that controls time base clock
needs to be configured for proper working of ePWM. Time base module is
part of ePWM IP, and it's clock enabled through control module.

Enabling time base clock is handled by adding clock tree node and by
flagging it with ENABLE_ON_INIT.

Signed-off-by: Philip, Avinash <avinashphilip@ti.com>
arch/arm/mach-omap2/clock33xx_data.c

index bb340f3c4c4890b1adda2d04eeea3febf858a54f..c88e4cf41a677bcea6938a6af93cfe9b8c67af39 100644 (file)
@@ -1986,6 +1986,35 @@ static struct clk wdt1_fck = {
        .recalc         = &omap2_clksel_recalc,
 };
 
+/*
+ * Provides clock definitions for enabling bits for Time base module in
+ * PWMSS ctrl register.
+ */
+
+static struct clk ehrpwm0_tbclk = {
+       .name           = "ehrpwm0_tbclk",
+       .enable_reg     = AM33XX_CONTROL_PWMSS_CTRL,
+       .enable_bit     = AM33XX_PWMSS0_TBCLKEN,
+       .ops            = &clkops_omap2_dflt,
+       .flags          = ENABLE_ON_INIT,
+};
+
+static struct clk ehrpwm1_tbclk = {
+       .name           = "ehrpwm1_tbclk",
+       .enable_reg     = AM33XX_CONTROL_PWMSS_CTRL,
+       .enable_bit     = AM33XX_PWMSS1_TBCLKEN,
+       .ops            = &clkops_omap2_dflt,
+       .flags          = ENABLE_ON_INIT,
+};
+
+static struct clk ehrpwm2_tbclk = {
+       .name           = "ehrpwm2_tbclk",
+       .enable_reg     = AM33XX_CONTROL_PWMSS_CTRL,
+       .enable_bit     = AM33XX_PWMSS2_TBCLKEN,
+       .ops            = &clkops_omap2_dflt,
+       .flags          = ENABLE_ON_INIT,
+};
+
 
 /*
  * clkdev
@@ -2165,6 +2194,9 @@ static struct omap_clk am33xx_clks[] = {
        CLK(NULL,       "gpt6_ick",             &timer6_ick,            CK_AM33XX),
        CLK(NULL,       "gpt7_ick",             &timer7_ick,            CK_AM33XX),
        CLK(NULL,       "vtp_clk",              &vtp_clk,               CK_AM33XX),
+       CLK(NULL,       "ehrpwm0_tbclk",        &ehrpwm0_tbclk, CK_AM33XX),
+       CLK(NULL,       "ehrpwm1_tbclk",        &ehrpwm1_tbclk, CK_AM33XX),
+       CLK(NULL,       "ehrpwm2_tbclk",        &ehrpwm2_tbclk, CK_AM33XX),
 };
 
 int __init am33xx_clk_init(void)