can: d_can: Add platform data for am33xx device
authorAnilKumar Ch <anilkumar@ti.com>
Sat, 26 Nov 2011 20:41:48 +0000 (02:11 +0530)
committerVaibhav Hiremath <hvaibhav@ti.com>
Mon, 23 Jan 2012 19:14:35 +0000 (00:44 +0530)
This patch adds the platform data needed by the driver. Add the
resources to the difference d_can instances.

Initialization of message ram is necessary to read/write the
message object from/into the message RAM

Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
arch/arm/mach-omap2/board-am335xevm.c
arch/arm/mach-omap2/devices.c
arch/arm/mach-omap2/include/mach/board-am335xevm.h
arch/arm/mach-omap2/mux33xx.c
arch/arm/plat-omap/include/plat/am33xx.h

index 47a5b07d199b11d441b60ac222a67e476d0d47c5..4d2812be4b7f3a6ec9f939c9b28acd4a1b8681a5 100644 (file)
@@ -569,6 +569,18 @@ static struct pinmux_config uart3_pin_mux[] = {
        {NULL, 0},
 };
 
+static struct pinmux_config d_can_gp_pin_mux[] = {
+       {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
+       {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+       {NULL, 0},
+};
+
+static struct pinmux_config d_can_ia_pin_mux[] = {
+       {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
+       {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+       {NULL, 0},
+};
+
 /*
 * @pin_mux - single module pin-mux structure which defines pin-mux
 *                      details for all its pins.
@@ -1030,6 +1042,28 @@ out:
        return;
 }
 
+static void d_can_init(int evm_id, int profile)
+{
+       switch (evm_id) {
+       case IND_AUT_MTR_EVM:
+               if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
+                       setup_pin_mux(d_can_ia_pin_mux);
+                       /* Instance Zero */
+                       am33xx_d_can_init(0);
+               }
+               break;
+       case GEN_PURP_EVM:
+               if (profile == PROFILE_1) {
+                       setup_pin_mux(d_can_gp_pin_mux);
+                       /* Instance One */
+                       am33xx_d_can_init(1);
+               }
+               break;
+       default:
+               break;
+       }
+}
+
 static void mmc0_init(int evm_id, int profile)
 {
        setup_pin_mux(mmc0_pin_mux);
@@ -1168,6 +1202,7 @@ static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
        {uart1_wl12xx_init,     DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
                                                                PROFILE_5)},
        {wl12xx_init,   DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 | PROFILE_5)},
+       {d_can_init,    DEV_ON_DGHTR_BRD, PROFILE_1},
        {NULL, 0, 0},
 };
 
index aa1f0b1342cc627756ced334c92544dc9a7bb423..dceb48061656c4990bffb746bb769479d54bb66a 100644 (file)
@@ -21,6 +21,7 @@
 #include <linux/cpsw.h>
 #include <linux/etherdevice.h>
 #include <linux/dma-mapping.h>
+#include <linux/can/platform/d_can.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -1290,6 +1291,125 @@ void am33xx_cpsw_init(unsigned int gigen)
                        NULL, &am33xx_cpsw_device.dev);
 }
 
+#define AM33XX_D_CAN_RAM_BASE                  0x1000
+#define AM33XX_D_CAN_NUM_MSG_OBJS              64
+#define AM33XX_CTL_DCAN_RAMINIT_OFFSET         0x644
+#define AM33XX_D_CAN_RAMINIT_START(n)          (0x1 << n)
+
+static void d_can_hw_raminit(unsigned int instance)
+{
+       u32 val;
+
+       /* Read the value */
+       val = __raw_readl(AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
+
+       /* Modify by setting "0" */
+       val &= ~AM33XX_D_CAN_RAMINIT_START(instance);
+       __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
+
+       /* Reset to one */
+       val |= AM33XX_D_CAN_RAMINIT_START(instance);
+       __raw_writel(val, AM33XX_CTRL_REGADDR(AM33XX_CTL_DCAN_RAMINIT_OFFSET));
+
+       /* Give some time delay for transition from 0 -> 1 */
+       udelay(1);
+}
+
+static struct d_can_platform_data am33xx_evm_d_can0_pdata = {
+       .d_can_offset           = 0,
+       .d_can_ram_offset       = AM33XX_D_CAN_RAM_BASE,
+       .num_of_msg_objs        = AM33XX_D_CAN_NUM_MSG_OBJS,
+       .dma_support            = false,
+       .parity_check           = false,
+       .fck_name               = "dcan0_fck",
+       .ick_name               = "dcan0_ick",
+};
+
+static struct resource am33xx_d_can0_resources[] = {
+       {
+               .start  = AM33XX_D_CAN0_BASE,
+               .end    = AM33XX_D_CAN0_BASE + 0x3FFF,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "int0",
+               .start  = AM33XX_IRQ_DCAN0_0,
+               .end    = AM33XX_IRQ_DCAN0_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               .name   = "int1",
+               .start  = AM33XX_IRQ_DCAN0_1,
+               .end    = AM33XX_IRQ_DCAN0_1,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device am33xx_d_can0_device = {
+       .dev            = {
+               .platform_data = &am33xx_evm_d_can0_pdata,
+       },
+       .name           = "d_can",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(am33xx_d_can0_resources),
+       .resource       = am33xx_d_can0_resources,
+};
+
+static struct resource am33xx_d_can1_resources[] = {
+       {
+               .start  = AM33XX_D_CAN1_BASE,
+               .end    = AM33XX_D_CAN1_BASE + 0x3FFF,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "int0",
+               .start  = AM33XX_IRQ_DCAN1_0,
+               .end    = AM33XX_IRQ_DCAN1_0,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               .name   = "int1",
+               .start  = AM33XX_IRQ_DCAN1_1,
+               .end    = AM33XX_IRQ_DCAN1_1,
+               .flags  = IORESOURCE_IRQ,
+       },
+};
+
+static struct d_can_platform_data am33xx_evm_d_can1_pdata = {
+       .d_can_offset           = 0,
+       .d_can_ram_offset       = AM33XX_D_CAN_RAM_BASE,
+       .num_of_msg_objs        = AM33XX_D_CAN_NUM_MSG_OBJS,
+       .dma_support            = false,
+       .parity_check           = false,
+       .fck_name               = "dcan1_fck",
+       .ick_name               = "dcan1_ick",
+};
+
+static struct platform_device am33xx_d_can1_device = {
+       .dev            = {
+               .platform_data = &am33xx_evm_d_can1_pdata,
+       },
+       .name           = "d_can",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(am33xx_d_can1_resources),
+       .resource       = am33xx_d_can1_resources,
+};
+
+void am33xx_d_can_init(unsigned int instance)
+{
+       switch (instance) {
+       case 0:
+               d_can_hw_raminit(instance);
+               platform_device_register(&am33xx_d_can0_device);
+               break;
+       case 1:
+               d_can_hw_raminit(instance);
+               platform_device_register(&am33xx_d_can1_device);
+               break;
+       default:
+               break;
+       }
+}
 
 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
 static int __init omap_init_wdt(void)
index fae17511a5d0550670e55ef79f348db97902ce2d..521b872c677b882965a4aa11826d3493eddff483 100644 (file)
@@ -40,5 +40,6 @@
 void am33xx_evmid_fillup(unsigned int evmid);
 void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1);
 void am33xx_cpsw_init(unsigned int gigen);
+void am33xx_d_can_init(unsigned int instance);
 
 #endif
index ef7fe87c960c8793a3e0e3204fdbbb2d848cefbc..8663da56ceff1c8ee0a26e392ad7515944aa4939 100644 (file)
@@ -303,16 +303,16 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
                "ecap0_in_pwm0_out", "uart3_txd", "spi1_cs1", NULL,
                "spi1_sclk", "mmc0_sdwp", NULL, "gpio0_7"),
        _AM33XX_MUXENTRY(UART0_CTSN, 0,
-               "uatr0_ctsn", NULL, NULL, NULL,
+               "uart0_ctsn", NULL, "d_can1_tx", NULL,
                "spi1_d0", NULL, NULL, NULL),
        _AM33XX_MUXENTRY(UART0_RTSN, 0,
-               "uart0_rtsn", NULL, NULL, NULL,
+               "uart0_rtsn", NULL, "d_can1_rx", NULL,
                "spi1_d1", "spi1_cs0", NULL, NULL),
        _AM33XX_MUXENTRY(UART0_RXD, 0,
-               "uart0_rxd", "spi1_cs0", NULL, NULL,
+               "uart0_rxd", "spi1_cs0", "d_can0_tx", NULL,
                NULL, NULL, NULL, NULL),
        _AM33XX_MUXENTRY(UART0_TXD, 0,
-               "uart0_txd", "spi1_cs1", NULL, NULL,
+               "uart0_txd", "spi1_cs1", "d_can0_rx", NULL,
                NULL, NULL, NULL, NULL),
        _AM33XX_MUXENTRY(UART1_CTSN, 0,
                "uart1_ctsn", NULL, NULL, NULL,
index 8daf63e1b17076e50a8e0930555d700f3fe3e93f..e2733b0b8cd575acd1c1d67c2ee7e31d15387f56 100644 (file)
@@ -41,6 +41,9 @@
 #define AM33XX_TSC_BASE                0x44E0D000
 #define AM33XX_RTC_BASE                0x44E3E000
 
+#define AM33XX_D_CAN0_BASE     0x481CC000
+#define AM33XX_D_CAN1_BASE     0x481D0000
+
 #define AM33XX_ASP0_BASE       0x48038000
 #define AM33XX_ASP1_BASE       0x4803C000