arm:omap:am335x: Corrects cpsw sa_lo and sa_hi offset
authorChandan Nath <chandan.nath@ti.com>
Fri, 21 Oct 2011 09:42:06 +0000 (15:12 +0530)
committerVaibhav Hiremath <hvaibhav@ti.com>
Mon, 23 Jan 2012 19:14:33 +0000 (00:44 +0530)
This patch is added to correct register offset of cpgmac
sl1 source low register address and cpgmac sl2 source high
register address. The register offset were 0x21c, 0x220 and
0x31c, 0x320. Instead they are corrected as 0x220, 0x224 and
0x320, 0x324. This is corrected by adding missing P1_TS_SEQ_MTYPE
register in cpsw_slave_reg structure.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
drivers/net/ethernet/ti/cpsw.c

index 080388c533a73d637d47f62995d198f8b7bf5ecc..e47c05c8676b68b29d384bc01e1333d8e6c35f18 100644 (file)
@@ -121,6 +121,7 @@ struct cpsw_slave_regs {
        u32     flow_thresh;
        u32     port_vlan;
        u32     tx_pri_map;
+       u32     ts_seq_mtype;
 #ifdef CONFIG_ARCH_TI814X
        u32     ts_ctl;
        u32     ts_seq_ltype;