arm:omap:am33xx: Register HSMMC Platform on AM335x EVM
authorHebbar, Gururaja <gururaja.hebbar@ti.com>
Tue, 4 Oct 2011 18:19:18 +0000 (23:49 +0530)
committerVaibhav Hiremath <hvaibhav@ti.com>
Mon, 23 Jan 2012 19:14:26 +0000 (00:44 +0530)
This patch adds the hardware info like pin-mux, platform data and
registers the MMC module. AM335x SOC supports 3 HS-MMC instances.
However only 2 HS-MMC (MMC0, 1) instances are supported on EVM.

Signed-off-by: Hebbar, Gururaja <gururaja.hebbar@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
arch/arm/mach-omap2/board-am335xevm.c
arch/arm/mach-omap2/hsmmc.c
arch/arm/mach-omap2/mux33xx.c
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
arch/arm/plat-omap/include/plat/dma-33xx.h

index 7e93a649cf9b612f456393e01f2a10fed84a9ad5..13707b61b0ebf3e4e92fb45d91871fb4f356636a 100644 (file)
 #include <plat/common.h>
 #include <plat/lcdc.h>
 #include <plat/usb.h>
+#include <plat/mmc.h>
 
 #include "board-flash.h"
 #include "mux.h"
 #include "devices.h"
+#include "hsmmc.h"
+
+/* Convert GPIO signal to GPIO pin number */
+#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
 
 static const struct display_panel disp_panel = {
        WVGA,
@@ -129,6 +134,24 @@ static struct snd_platform_data am335x_evm_snd_data1 = {
        .rxnumevt       = 1,
 };
 
+static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
+       {
+               .mmc            = 1,
+               .caps           = MMC_CAP_4_BIT_DATA,
+               .gpio_cd        = GPIO_TO_PIN(0, 6),
+               .gpio_wp        = GPIO_TO_PIN(3, 18),
+               .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
+       },
+       {
+               .mmc            = 0,    /* will be set at runtime */
+       },
+       {
+               .mmc            = 0,    /* will be set at runtime */
+       },
+       {}      /* Terminator */
+};
+
+
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
        AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
@@ -392,6 +415,48 @@ static struct pinmux_config mcasp1_pin_mux[] = {
        {NULL, 0},
 };
 
+
+/* Module pin mux for mmc0 */
+static struct pinmux_config mmc0_pin_mux[] = {
+       {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+       {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+       {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+       {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+       {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+       {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+       {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+       {"spi0_cs1.mmc0_sdcd",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+       {NULL, 0},
+};
+
+static struct pinmux_config mmc0_no_cd_pin_mux[] = {
+       {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+       {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+       {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+       {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+       {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+       {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
+       {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
+       {NULL, 0},
+};
+
+/* Module pin mux for mmc1 */
+static struct pinmux_config mmc1_pin_mux[] = {
+       {"gpmc_ad7.mmc1_dat7",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+       {"gpmc_ad6.mmc1_dat6",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+       {"gpmc_ad5.mmc1_dat5",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+       {"gpmc_ad4.mmc1_dat4",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+       {"gpmc_ad3.mmc1_dat3",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+       {"gpmc_ad2.mmc1_dat2",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+       {"gpmc_ad1.mmc1_dat1",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+       {"gpmc_ad0.mmc1_dat0",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+       {"gpmc_csn1.mmc1_clk",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+       {"gpmc_csn2.mmc1_cmd",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+       {"gpmc_csn0.mmc1_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+       {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+       {NULL, 0},
+};
+
 /*
 * @pin_mux - single module pin-mux structure which defines pin-mux
 *                      details for all its pins.
@@ -446,9 +511,6 @@ static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
        }
 }
 
-/* Convert GPIO signal to GPIO pin number */
-#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
-
 #define AM335X_LCD_BL_PIN      GPIO_TO_PIN(0, 7)
 
 /* pinmux for usb0 drvvbus */
@@ -648,6 +710,37 @@ static void mcasp1_init(int evm_id, int profile)
        return;
 }
 
+static void mmc1_init(int evm_id, int profile)
+{
+       setup_pin_mux(mmc1_pin_mux);
+
+       am335x_mmc[1].mmc = 2;
+       am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
+       am335x_mmc[1].gpio_cd = GPIO_TO_PIN(2, 2);
+       am335x_mmc[1].gpio_wp = GPIO_TO_PIN(1, 29);
+       am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
+
+       /* mmc will be initialized when mmc0_init is called */
+       return;
+}
+
+static void mmc0_init(int evm_id, int profile)
+{
+       setup_pin_mux(mmc0_pin_mux);
+
+       omap2_hsmmc_init(am335x_mmc);
+       return;
+}
+
+static void mmc0_no_cd_init(int evm_id, int profile)
+{
+       setup_pin_mux(mmc0_no_cd_pin_mux);
+
+       omap2_hsmmc_init(am335x_mmc);
+       return;
+}
+
+
 /* Low-Cost EVM */
 static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
        {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
@@ -674,6 +767,9 @@ static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
                (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
        {i2c1_init,     DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
        {mcasp1_init,   DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
+       {mmc1_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
+       {mmc0_init,     DEV_ON_BASEBOARD, (PROFILE_ALL & ~PROFILE_5)},
+       {mmc0_no_cd_init,       DEV_ON_BASEBOARD, PROFILE_5},
        {NULL, 0, 0},
 };
 
@@ -698,6 +794,7 @@ static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
        {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
        {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
        {mcasp1_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
+       {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
        {NULL, 0, 0},
 };
 
index bd844af13af56106d7fe5511dcaa6d2ebf6f7afa..7c12ca34ad32144e8f0e8a74b18f049b74ab4ae3 100644 (file)
@@ -304,6 +304,9 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
                return -ENOMEM;
        }
 
+       if (cpu_is_am33xx())
+               mmc->version = MMC_CTRL_VERSION_2;
+
        if (c->name)
                strncpy(hc_name, c->name, HSMMC_NAME_LEN);
        else
@@ -363,10 +366,11 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
        else
                mmc->slots[0].ocr_mask = c->ocr_mask;
 
-       if (!cpu_is_omap3517() && !cpu_is_omap3505())
+       if (!cpu_is_omap3517() && !cpu_is_omap3505() && !cpu_is_am33xx())
                mmc->slots[0].features |= HSMMC_HAS_PBIAS;
 
-       if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
+       if ((cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) ||
+                                                               cpu_is_am33xx())
                mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
 
        switch (c->mmc) {
@@ -386,7 +390,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
                        }
                }
 
-               if (cpu_is_omap3517() || cpu_is_omap3505())
+               if (cpu_is_omap3517() || cpu_is_omap3505() || cpu_is_am33xx())
                        mmc->slots[0].set_power = nop_mmc_set_power;
 
                /* OMAP3630 HSMMC1 supports only 4-bit */
@@ -450,7 +454,9 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
                pr_err("%s fails!\n", __func__);
                goto done;
        }
-       omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
+
+       if (!cpu_is_am33xx())
+               omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
 
        name = "omap_hsmmc";
 
index 017c18f57b3281678aa73c0f91c3f614a33e2ba5..f4c052b65d384c7373493f3ca744d39b14d08e03 100644 (file)
@@ -124,7 +124,7 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
                NULL, NULL, "mcasp0_aclkr", NULL),
        _AM33XX_MUXENTRY(GPMC_CSN0, 0,
                "gpmc_csn0", NULL, NULL, NULL,
-               NULL, NULL, NULL, NULL),
+               NULL, NULL, NULL, "mmc1_sdwp"),
        _AM33XX_MUXENTRY(GPMC_CSN1, 0,
                "gpmc_csn1", NULL, "mmc1_clk", NULL,
                NULL, NULL, NULL, NULL),
@@ -139,7 +139,7 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
                NULL, NULL, "mcasp0_fsr", NULL),
        _AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0,
                "gpmc_advn_ale", NULL, NULL, NULL,
-               NULL, NULL, NULL, NULL),
+               NULL, NULL, NULL, "mmc1_sdcd"),
        _AM33XX_MUXENTRY(GPMC_OEN_REN, 0,
                "gpmc_oen_ren", NULL, NULL, NULL,
                NULL, NULL, NULL, NULL),
index 7dbcb7ce084fa097aac2d72eac67f5d2a0793093..c847bc1d9c802d28520fd0bee7d4c77a873757fa 100644 (file)
@@ -1178,8 +1178,8 @@ static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
 };
 
 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
-       { .name = "tx", .dma_req = 64, },
-       { .name = "rx", .dma_req = 65, },
+       { .name = "tx", .dma_req = AM33XX_DMA_MMCHS2_W, },
+       { .name = "rx", .dma_req = AM33XX_DMA_MMCHS2_R, },
        { .dma_req = -1 }
 };
 
index f78edb44c8a29540626bec43af611151e8db04b1..bebdaa7f2b4c80fed6a55289b92b7fa96c67cb8b 100644 (file)
@@ -81,5 +81,7 @@
 #define AM33XX_DMA_MSHSI2COCP1_RX                      61
 #define AM33XX_DMA_PWMSS2_ECAP                         62
 #define AM33XX_DMA_PWMSS2_EPW                          63
+#define AM33XX_DMA_MMCHS2_W                            64      /* xBar */
+#define AM33XX_DMA_MMCHS2_R                            65      /* xBar */
 
 #endif