drm/radeon: Add a rmb() in IH processing

We should have a read memory barrier between reading the WPTR from
memory and reading ring entries based on that value (ie, we need to
ensure both loads are done in order by the CPU).

It could be argued that the MMIO reads in r600_ack_irq() might be
enough to get that barrier but I prefer keeping an explicit one just
in case.

[airlied: fix evergreen + r/w mixup]

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 37dd6449f46f7f957f813829f8e4eea5f891a5a7..bcd55917c7cca725105c86e977f2fbaff34cafcd 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2759,6 +2759,9 @@ int evergreen_irq_process(struct radeon_device *rdev)
                return IRQ_NONE;
        }
 restart_ih:
+       /* Order reading of wptr vs. reading of IH ring data */
+       rmb();
+
        /* display interrupts */
        evergreen_irq_ack(rdev);
 

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index f56e65579835d9665c925c9904f1082151b3464f..aa5571b73aa02e947ec590ad6febb624778fc3da 100644 (file)
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3318,6 +3318,9 @@ int r600_irq_process(struct radeon_device *rdev)
        }
 
 restart_ih:
+       /* Order reading of wptr vs. reading of IH ring data */
+       rmb();
+
        /* display interrupts */
        r600_irq_ack(rdev);