ti-sdk-am335x-evm-05.05.00.00 on 04.06.00.07
authorHemant Pedanekar <hemant@athena>
Thu, 13 Sep 2012 14:54:29 +0000 (20:24 +0530)
committerHemant Pedanekar <hemant@athena>
Thu, 13 Sep 2012 14:54:29 +0000 (20:24 +0530)
113 files changed:
arch/arm/common/edma.c
arch/arm/configs/am335x_evm_defconfig
arch/arm/configs/tisdk_am335x-evm_defconfig [new file with mode: 0644]
arch/arm/mach-omap2/Kconfig
arch/arm/mach-omap2/Makefile
arch/arm/mach-omap2/am33xx-smartreflex-class2.c [new file with mode: 0644]
arch/arm/mach-omap2/board-am335xevm.c
arch/arm/mach-omap2/clock33xx_data.c
arch/arm/mach-omap2/control.h
arch/arm/mach-omap2/devices.c
arch/arm/mach-omap2/include/mach/board-am335xevm.h
arch/arm/mach-omap2/irq.c
arch/arm/mach-omap2/mux.c
arch/arm/mach-omap2/mux33xx.c
arch/arm/mach-omap2/omap_hwmod.c
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
arch/arm/mach-omap2/opp3xxx_data.c
arch/arm/mach-omap2/pm.h
arch/arm/mach-omap2/pm33xx.c
arch/arm/mach-omap2/pm33xx.h
arch/arm/mach-omap2/prminst44xx.c
arch/arm/mach-omap2/prminst44xx.h
arch/arm/mach-omap2/sleep33xx.S
arch/arm/plat-omap/Kconfig
arch/arm/plat-omap/devices.c
arch/arm/plat-omap/include/plat/am33xx.h
arch/arm/plat-omap/include/plat/emif.h
arch/arm/plat-omap/include/plat/gpio.h
arch/arm/plat-omap/include/plat/irqs.h
arch/arm/plat-omap/include/plat/omap_hwmod.h
arch/arm/plat-omap/include/plat/smartreflex.h [new file with mode: 0644]
crypto/Kconfig
crypto/Makefile
crypto/ocf/Config.in [new file with mode: 0644]
crypto/ocf/Kconfig [new file with mode: 0644]
crypto/ocf/Makefile [new file with mode: 0644]
crypto/ocf/criov.c [new file with mode: 0644]
crypto/ocf/crypto.c [new file with mode: 0644]
crypto/ocf/cryptodev.c [new file with mode: 0644]
crypto/ocf/cryptodev.h [new file with mode: 0644]
crypto/ocf/cryptosoft.c [new file with mode: 0644]
crypto/ocf/ocf-bench.c [new file with mode: 0644]
crypto/ocf/ocf-compat.h [new file with mode: 0644]
crypto/ocf/ocfnull/Makefile [new file with mode: 0644]
crypto/ocf/ocfnull/ocfnull.c [new file with mode: 0644]
crypto/ocf/random.c [new file with mode: 0644]
crypto/ocf/rndtest.c [new file with mode: 0644]
crypto/ocf/rndtest.h [new file with mode: 0644]
crypto/ocf/uio.h [new file with mode: 0644]
drivers/char/hw_random/Kconfig
drivers/char/hw_random/Makefile
drivers/char/hw_random/omap4-rng.c [new file with mode: 0644]
drivers/char/random.c
drivers/crypto/Kconfig
drivers/crypto/Makefile
drivers/crypto/omap4-aes.c [new file with mode: 0644]
drivers/crypto/omap4-sham.c [new file with mode: 0644]
drivers/crypto/omap4.h [new file with mode: 0644]
drivers/input/touchscreen/ti_tscadc.c
drivers/mmc/card/block.c
drivers/mmc/card/queue.c
drivers/mmc/core/bus.c
drivers/mmc/core/core.c
drivers/mmc/core/core.h
drivers/mmc/core/mmc.c
drivers/mmc/core/sd.c
drivers/mmc/core/sdio.c
drivers/mmc/host/omap_hsmmc.c
drivers/net/ethernet/ti/Kconfig
drivers/net/ethernet/ti/cpsw.c
drivers/net/ethernet/ti/cpsw_ale.c
drivers/net/ethernet/ti/cpsw_ale.h
drivers/net/ethernet/ti/davinci_cpdma.c
drivers/net/ethernet/ti/davinci_cpdma.h
drivers/net/ethernet/ti/davinci_emac.c
drivers/net/ethernet/ti/davinci_mdio.c
drivers/pwm/ecap.c
drivers/regulator/core.c
drivers/regulator/tps65217-regulator.c
drivers/tty/serial/omap-serial.c
drivers/usb/gadget/udc-core.c
drivers/usb/musb/Kconfig
drivers/usb/musb/cppi41.c
drivers/usb/musb/cppi41_dma.c
drivers/usb/musb/cppi41_dma.h
drivers/usb/musb/musb_core.c
drivers/usb/musb/musb_core.h
drivers/usb/musb/musb_gadget.c
drivers/usb/musb/musb_host.c
drivers/usb/musb/musb_procfs.c
drivers/usb/musb/ti81xx.c
drivers/usb/musb/ti81xx.h
drivers/video/da8xx-fb.c
fs/fcntl.c
include/linux/Kbuild
include/linux/cpsw.h
include/linux/input/ti_tscadc.h
include/linux/mfd/tps65217.h
include/linux/miscdevice.h
include/linux/mmc/card.h
include/linux/mmc/core.h
include/linux/mmc/host.h
include/linux/net_switch_config.h [new file with mode: 0644]
include/linux/pwm/pwm.h
include/linux/random.h
include/linux/regulator/driver.h
include/linux/regulator/machine.h
include/linux/sockios.h
kernel/pid.c
net/core/dev.c
sound/soc/codecs/tlv320aic3x.c
sound/soc/codecs/tlv320aic3x.h
sound/soc/davinci/davinci-evm.c

index fe00c927af2c02f179cdeee7071ff3b0a4d8fa23..745b7992ce103fbcf0818e1bb2e3383cce2432d4 100644 (file)
@@ -323,9 +323,10 @@ static int irq2ctlr(int irq)
  *****************************************************************************/
 static irqreturn_t dma_irq_handler(int irq, void *data)
 {
-       int i;
        int ctlr;
-       unsigned int cnt = 0;
+       u32 sh_ier;
+       u32 sh_ipr;
+       u32 bank;
 
        ctlr = irq2ctlr(irq);
        if (ctlr < 0)
@@ -333,41 +334,41 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
 
        dev_dbg(data, "dma_irq_handler\n");
 
-       if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0) &&
-           (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
-               return IRQ_NONE;
+       sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
+       if (!sh_ipr) {
+               sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
+               if (!sh_ipr)
+                       return IRQ_NONE;
+               sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
+               bank = 1;
+       } else {
+               sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
+               bank = 0;
+       }
+
+       do {
+               u32 slot;
+               u32 channel;
+
+               dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
+
+               slot = __ffs(sh_ipr);
+               sh_ipr &= ~(BIT(slot));
+
+               if (sh_ier & BIT(slot)) {
+                       channel = (bank << 5) | slot;
+                       /* Clear the corresponding IPR bits */
+                       edma_shadow0_write_array(ctlr, SH_ICR, bank,
+                                       BIT(slot));
+                       if (edma_cc[ctlr]->intr_data[channel].callback)
+                               edma_cc[ctlr]->intr_data[channel].callback(
+                                       channel, DMA_COMPLETE,
+                                       edma_cc[ctlr]->intr_data[channel].data);
+
 
-       while (1) {
-               int j;
-               if (edma_shadow0_read_array(ctlr, SH_IPR, 0) &
-                               edma_shadow0_read_array(ctlr, SH_IER, 0))
-                       j = 0;
-               else if (edma_shadow0_read_array(ctlr, SH_IPR, 1) &
-                               edma_shadow0_read_array(ctlr, SH_IER, 1))
-                       j = 1;
-               else
-                       break;
-               dev_dbg(data, "IPR%d %08x\n", j,
-                               edma_shadow0_read_array(ctlr, SH_IPR, j));
-               for (i = 0; i < 32; i++) {
-                       int k = (j << 5) + i;
-                       if ((edma_shadow0_read_array(ctlr, SH_IPR, j) & BIT(i))
-                                       && (edma_shadow0_read_array(ctlr,
-                                                       SH_IER, j) & BIT(i))) {
-                               /* Clear the corresponding IPR bits */
-                               edma_shadow0_write_array(ctlr, SH_ICR, j,
-                                                       BIT(i));
-                               if (edma_cc[ctlr]->intr_data[k].callback)
-                                       edma_cc[ctlr]->intr_data[k].callback(
-                                               k, DMA_COMPLETE,
-                                               edma_cc[ctlr]->intr_data[k].
-                                               data);
-                       }
                }
-               cnt++;
-               if (cnt > 10)
-                       break;
-       }
+       } while (sh_ipr);
+
        edma_shadow0_write(ctlr, SH_IEVAL, 1);
        return IRQ_HANDLED;
 }
index a9350a449a7af943484cb53128316149ebf85e5e..a1f95bea1942d85034b3d74ca1cc3a2ce67730de 100644 (file)
@@ -269,6 +269,7 @@ CONFIG_ARCH_OMAP2PLUS=y
 # OMAP Feature Selections
 #
 # CONFIG_OMAP_SMARTREFLEX is not set
+CONFIG_AM33XX_SMARTREFLEX=y
 CONFIG_OMAP_RESET_CLOCKS=y
 CONFIG_OMAP_MUX=y
 CONFIG_OMAP_MUX_DEBUG=y
@@ -325,6 +326,7 @@ CONFIG_MACH_TI8148EVM=y
 CONFIG_MACH_AM335XEVM=y
 CONFIG_MACH_AM335XIAEVM=y
 # CONFIG_OMAP3_EMU is not set
+CONFIG_TI_PM_DISABLE_VT_SWITCH=y
 # CONFIG_OMAP3_SDRC_AC_TIMING is not set
 CONFIG_OMAP3_EDMA=y
 
@@ -1052,7 +1054,7 @@ CONFIG_NET_VENDOR_TI=y
 CONFIG_TI_DAVINCI_MDIO=y
 CONFIG_TI_DAVINCI_CPDMA=y
 CONFIG_TI_CPSW=y
-CONFIG_TLK110_WORKAROUND=y
+CONFIG_TI_CPSW_DUAL_EMAC=y
 CONFIG_PHYLIB=y
 
 #
@@ -1277,6 +1279,9 @@ CONFIG_SERIAL_OMAP_CONSOLE=y
 # CONFIG_SERIAL_XILINX_PS_UART is not set
 # CONFIG_HVC_DCC is not set
 # CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+CONFIG_HW_RANDOM_OMAP4=y
 # CONFIG_HW_RANDOM is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
@@ -1775,7 +1780,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_SMSCUFX is not set
 # CONFIG_FB_UDL is not set
 CONFIG_FB_DA8XX=y
-CONFIG_FB_DA8XX_CONSISTENT_DMA_SIZE=4
+CONFIG_FB_DA8XX_CONSISTENT_DMA_SIZE=5
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FB_METRONOME is not set
 # CONFIG_FB_BROADSHEET is not set
@@ -1983,11 +1988,11 @@ CONFIG_USB_MUSB_TI81XX_GLUE=y
 CONFIG_USB_MUSB_TI81XX=y
 # CONFIG_USB_MUSB_BLACKFIN is not set
 # CONFIG_USB_MUSB_UX500 is not set
-CONFIG_USB_TI_CPPI41_DMA_HW=y
-# CONFIG_MUSB_PIO_ONLY is not set
+# CONFIG_USB_TI_CPPI41_DMA_HW is not set
+CONFIG_MUSB_PIO_ONLY=y
 # CONFIG_USB_INVENTRA_DMA is not set
 # CONFIG_USB_TI_CPPI_DMA is not set
-CONFIG_USB_TI_CPPI41_DMA=y
+# CONFIG_USB_TI_CPPI41_DMA is not set
 # CONFIG_USB_TUSB_OMAP_DMA is not set
 # CONFIG_USB_UX500_DMA is not set
 # CONFIG_USB_RENESAS_USBHS is not set
@@ -2127,7 +2132,12 @@ CONFIG_MMC_OMAP_HS=y
 # CONFIG_MMC_VUB300 is not set
 # CONFIG_MMC_USHC is not set
 # CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 # CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -2467,36 +2477,38 @@ CONFIG_CRYPTO=y
 #
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
 CONFIG_CRYPTO_AEAD2=y
 CONFIG_CRYPTO_BLKCIPHER=y
 CONFIG_CRYPTO_BLKCIPHER2=y
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
 CONFIG_CRYPTO_RNG2=y
 CONFIG_CRYPTO_PCOMP2=y
 CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_MANAGER2=y
 # CONFIG_CRYPTO_USER is not set
-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
 CONFIG_CRYPTO_WORKQUEUE=y
 # CONFIG_CRYPTO_CRYPTD is not set
 # CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_TEST=m
 
 #
 # Authenticated Encryption with Associated Data
 #
 # CONFIG_CRYPTO_CCM is not set
 # CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_SEQIV=y
 
 #
 # Block modes
 #
-# CONFIG_CRYPTO_CBC is not set
-# CONFIG_CRYPTO_CTR is not set
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
 # CONFIG_CRYPTO_CTS is not set
 CONFIG_CRYPTO_ECB=y
 # CONFIG_CRYPTO_LRW is not set
@@ -2506,7 +2518,7 @@ CONFIG_CRYPTO_ECB=y
 #
 # Hash modes
 #
-# CONFIG_CRYPTO_HMAC is not set
+CONFIG_CRYPTO_HMAC=y
 # CONFIG_CRYPTO_XCBC is not set
 # CONFIG_CRYPTO_VMAC is not set
 
@@ -2516,14 +2528,14 @@ CONFIG_CRYPTO_ECB=y
 CONFIG_CRYPTO_CRC32C=y
 # CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
+CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_MICHAEL_MIC=y
 # CONFIG_CRYPTO_RMD128 is not set
 # CONFIG_CRYPTO_RMD160 is not set
 # CONFIG_CRYPTO_RMD256 is not set
 # CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
 # CONFIG_CRYPTO_SHA512 is not set
 # CONFIG_CRYPTO_TGR192 is not set
 # CONFIG_CRYPTO_WP512 is not set
@@ -2538,7 +2550,7 @@ CONFIG_CRYPTO_ARC4=y
 # CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
 # CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
+CONFIG_CRYPTO_DES=y
 # CONFIG_CRYPTO_FCRYPT is not set
 # CONFIG_CRYPTO_KHAZAD is not set
 # CONFIG_CRYPTO_SALSA20 is not set
@@ -2560,7 +2572,19 @@ CONFIG_CRYPTO_LZO=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 # CONFIG_CRYPTO_USER_API_HASH is not set
 # CONFIG_CRYPTO_USER_API_SKCIPHER is not set
-# CONFIG_CRYPTO_HW is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_OMAP4_AES=y
+CONFIG_CRYPTO_DEV_OMAP4_SHAM=y
+
+#
+# OCF Configuration
+#
+CONFIG_OCF_OCF=y
+# CONFIG_OCF_RANDOMHARVEST is not set
+CONFIG_OCF_CRYPTODEV=y
+CONFIG_OCF_CRYPTOSOFT=y
+# CONFIG_OCF_OCFNULL is not set
+# CONFIG_OCF_BENCH is not set
 # CONFIG_BINARY_PRINTF is not set
 
 #
diff --git a/arch/arm/configs/tisdk_am335x-evm_defconfig b/arch/arm/configs/tisdk_am335x-evm_defconfig
new file mode 100644 (file)
index 0000000..30223ae
--- /dev/null
@@ -0,0 +1,2656 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 3.2.0 Kernel Configuration
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_HAVE_SCHED_CLOCK=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_HAVE_IRQ_WORK=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_FHANDLE is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_HAVE_SPARSE_IRQ=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+# CONFIG_SPARSE_IRQ is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TINY_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_CGROUPS is not set
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EXPERT is not set
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+# CONFIG_EMBEDDED is not set
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_HIGHBANK is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_PRIMA2 is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_MXS is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_PICOXCELL is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_TCC_926 is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_ARCH_VT8500 is not set
+# CONFIG_ARCH_ZYNQ is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+
+#
+# TI OMAP Common Features
+#
+# CONFIG_ARCH_OMAP1 is not set
+CONFIG_ARCH_OMAP2PLUS=y
+
+#
+# OMAP Feature Selections
+#
+CONFIG_AM33XX_SMARTREFLEX=y
+# CONFIG_OMAP_SMARTREFLEX is not set
+CONFIG_OMAP_RESET_CLOCKS=y
+CONFIG_OMAP_MUX=y
+CONFIG_OMAP_MUX_DEBUG=y
+CONFIG_OMAP_MUX_WARNINGS=y
+# CONFIG_OMAP_MCBSP is not set
+CONFIG_OMAP_MBOX_FWK=y
+CONFIG_OMAP_MBOX_KFIFO_SIZE=256
+# CONFIG_OMAP_32K_TIMER is not set
+# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_PM_NOOP=y
+CONFIG_MACH_OMAP_GENERIC=y
+
+#
+# TI OMAP2/3/4 Specific Features
+#
+CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+# CONFIG_ARCH_OMAP4 is not set
+# CONFIG_SOC_OMAP3430 is not set
+CONFIG_SOC_OMAPTI81XX=y
+CONFIG_SOC_OMAPAM33XX=y
+CONFIG_OMAP_PACKAGE_CBB=y
+
+#
+# OMAP Board Type
+#
+CONFIG_MACH_OMAP3_BEAGLE=y
+# CONFIG_MACH_DEVKIT8000 is not set
+# CONFIG_MACH_OMAP_LDP is not set
+# CONFIG_MACH_OMAP3530_LV_SOM is not set
+# CONFIG_MACH_OMAP3_TORPEDO is not set
+# CONFIG_MACH_ENCORE is not set
+# CONFIG_MACH_OVERO is not set
+# CONFIG_MACH_OMAP3EVM is not set
+# CONFIG_MACH_OMAP3517EVM is not set
+# CONFIG_MACH_CRANEBOARD is not set
+# CONFIG_MACH_OMAP3_PANDORA is not set
+# CONFIG_MACH_OMAP3_TOUCHBOOK is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+# CONFIG_MACH_NOKIA_RM680 is not set
+# CONFIG_MACH_NOKIA_RX51 is not set
+# CONFIG_MACH_OMAP_ZOOM2 is not set
+# CONFIG_MACH_OMAP_ZOOM3 is not set
+# CONFIG_MACH_CM_T35 is not set
+# CONFIG_MACH_CM_T3517 is not set
+# CONFIG_MACH_IGEP0020 is not set
+# CONFIG_MACH_IGEP0030 is not set
+# CONFIG_MACH_SBC3530 is not set
+# CONFIG_MACH_OMAP_3630SDP is not set
+CONFIG_MACH_TI8168EVM=y
+CONFIG_MACH_TI8148EVM=y
+CONFIG_MACH_AM335XEVM=y
+CONFIG_MACH_AM335XIAEVM=y
+# CONFIG_OMAP3_EMU is not set
+CONFIG_TI_PM_DISABLE_VT_SWITCH=y
+# CONFIG_OMAP3_SDRC_AC_TIMING is not set
+CONFIG_OMAP3_EDMA=y
+
+#
+# System MMU
+#
+
+#
+# Processor Type
+#
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_SWP_EMULATE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_MULTI_IRQ_HANDLER=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_ARM_ERRATA_743622 is not set
+# CONFIG_ARM_ERRATA_751472 is not set
+# CONFIG_ARM_ERRATA_754322 is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HAVE_ARCH_PFN_VALID=y
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_NEED_PER_CPU_KM=y
+# CONFIG_CLEANCACHE is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+# CONFIG_SECCOMP is not set
+# CONFIG_CC_STACKPROTECTOR is not set
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+
+#
+# Boot options
+#
+CONFIG_USE_OF=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+# CONFIG_ARM_APPENDED_DTB is not set
+CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO0,115200"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_FORCE is not set
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+# CONFIG_AUTO_ZRELADDR is not set
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+
+#
+# ARM CPU frequency scaling drivers
+#
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_ADVANCED_DEBUG=y
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_CAN_PM_TRACE=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_HAS_OPP=y
+CONFIG_PM_OPP=y
+CONFIG_PM_CLK=y
+CONFIG_CPU_PM=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+CONFIG_NF_CONNTRACK=y
+# CONFIG_NF_CONNTRACK_MARK is not set
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+# CONFIG_NF_CT_PROTO_DCCP is not set
+# CONFIG_NF_CT_PROTO_SCTP is not set
+# CONFIG_NF_CT_PROTO_UDPLITE is not set
+# CONFIG_NF_CONNTRACK_AMANDA is not set
+# CONFIG_NF_CONNTRACK_FTP is not set
+# CONFIG_NF_CONNTRACK_H323 is not set
+# CONFIG_NF_CONNTRACK_IRC is not set
+# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
+# CONFIG_NF_CONNTRACK_SNMP is not set
+# CONFIG_NF_CONNTRACK_PPTP is not set
+# CONFIG_NF_CONNTRACK_SANE is not set
+# CONFIG_NF_CONNTRACK_SIP is not set
+# CONFIG_NF_CONNTRACK_TFTP is not set
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_XTABLES=y
+
+#
+# Xtables combined modules
+#
+# CONFIG_NETFILTER_XT_MARK is not set
+# CONFIG_NETFILTER_XT_CONNMARK is not set
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+# CONFIG_NETFILTER_XT_TARGET_LED is not set
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+
+#
+# Xtables matches
+#
+# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
+# CONFIG_NETFILTER_XT_MATCH_HL is not set
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+# CONFIG_NETFILTER_XT_MATCH_STATE is not set
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=y
+# CONFIG_IP_NF_MATCH_AH is not set
+# CONFIG_IP_NF_MATCH_ECN is not set
+# CONFIG_IP_NF_MATCH_TTL is not set
+CONFIG_IP_NF_FILTER=y
+# CONFIG_IP_NF_TARGET_REJECT is not set
+CONFIG_IP_NF_TARGET_LOG=y
+# CONFIG_IP_NF_TARGET_ULOG is not set
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+# CONFIG_IP_NF_TARGET_NETMAP is not set
+# CONFIG_IP_NF_TARGET_REDIRECT is not set
+# CONFIG_NF_NAT_FTP is not set
+# CONFIG_NF_NAT_IRC is not set
+# CONFIG_NF_NAT_TFTP is not set
+# CONFIG_NF_NAT_AMANDA is not set
+# CONFIG_NF_NAT_PPTP is not set
+# CONFIG_NF_NAT_H323 is not set
+# CONFIG_NF_NAT_SIP is not set
+# CONFIG_IP_NF_MANGLE is not set
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_SECURITY is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_BCM=y
+# CONFIG_CAN_GW is not set
+
+#
+# CAN Device Drivers
+#
+# CONFIG_CAN_VCAN is not set
+# CONFIG_CAN_SLCAN is not set
+CONFIG_CAN_DEV=y
+CONFIG_CAN_CALC_BITTIMING=y
+# CONFIG_CAN_TI_HECC is not set
+# CONFIG_CAN_MCP251X is not set
+# CONFIG_CAN_SJA1000 is not set
+# CONFIG_CAN_C_CAN is not set
+CONFIG_CAN_D_CAN=y
+CONFIG_CAN_D_CAN_PLATFORM=y
+
+#
+# CAN USB interfaces
+#
+# CONFIG_CAN_EMS_USB is not set
+# CONFIG_CAN_ESD_USB2 is not set
+# CONFIG_CAN_SOFTING is not set
+# CONFIG_CAN_DEBUG_DEVICES is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+CONFIG_RFKILL=y
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL_INPUT=y
+# CONFIG_RFKILL_REGULATOR is not set
+# CONFIG_RFKILL_GPIO is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE="am335x-pm-firmware.bin"
+CONFIG_EXTRA_FIRMWARE_DIR="firmware"
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_SPI=y
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_OF_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+CONFIG_MTD_OOPS=y
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PHYSMAP_OF is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_DOCG3 is not set
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_BCH is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_OMAP2=y
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_ONENAND=y
+# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
+# CONFIG_MTD_ONENAND_GENERIC is not set
+CONFIG_MTD_ONENAND_OMAP2=y
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+# CONFIG_MTD_UBI_DEBUG is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+
+#
+# Device Tree and Open Firmware support
+#
+CONFIG_PROC_DEVICETREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_I2C=y
+CONFIG_OF_NET=y
+CONFIG_OF_SPI=y
+CONFIG_OF_MDIO=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_BLK_DEV_RBD is not set
+CONFIG_SENSORS_LIS3LV02D=y
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ATMEL_PWM is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+CONFIG_SENSORS_TSL2550=y
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_IWMC3200TOP is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+CONFIG_SENSORS_LIS3_I2C=y
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_TARGET_CORE is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_MII=y
+# CONFIG_MACVLAN is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_ETHERNET=y
+CONFIG_NET_VENDOR_BROADCOM=y
+# CONFIG_B44 is not set
+CONFIG_NET_VENDOR_CHELSIO=y
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+CONFIG_NET_VENDOR_FARADAY=y
+# CONFIG_FTMAC100 is not set
+# CONFIG_FTGMAC100 is not set
+CONFIG_NET_VENDOR_INTEL=y
+CONFIG_NET_VENDOR_I825XX=y
+CONFIG_NET_VENDOR_MARVELL=y
+CONFIG_NET_VENDOR_MICREL=y
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+CONFIG_NET_VENDOR_MICROCHIP=y
+# CONFIG_ENC28J60 is not set
+CONFIG_NET_VENDOR_NATSEMI=y
+CONFIG_NET_VENDOR_8390=y
+# CONFIG_AX88796 is not set
+# CONFIG_ETHOC is not set
+CONFIG_NET_VENDOR_SEEQ=y
+# CONFIG_SEEQ8005 is not set
+CONFIG_NET_VENDOR_SMSC=y
+CONFIG_SMC91X=y
+# CONFIG_SMC911X is not set
+CONFIG_SMSC911X=y
+# CONFIG_SMSC911X_ARCH_HOOKS is not set
+CONFIG_NET_VENDOR_STMICRO=y
+# CONFIG_STMMAC_ETH is not set
+CONFIG_NET_VENDOR_TI=y
+# CONFIG_TI_DAVINCI_EMAC is not set
+CONFIG_TI_DAVINCI_MDIO=y
+CONFIG_TI_DAVINCI_CPDMA=y
+CONFIG_TI_CPSW=y
+CONFIG_TI_CPSW_DUAL_EMAC=y
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_AX8817X is not set
+CONFIG_USB_NET_CDCETHER=y
+CONFIG_USB_NET_CDC_EEM=y
+CONFIG_USB_NET_CDC_NCM=y
+CONFIG_USB_NET_DM9601=y
+# CONFIG_USB_NET_SMSC75XX is not set
+# CONFIG_USB_NET_SMSC95XX is not set
+# CONFIG_USB_NET_GL620A is not set
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_MCS7830 is not set
+# CONFIG_USB_NET_RNDIS_HOST is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+# CONFIG_USB_NET_ZAURUS is not set
+# CONFIG_USB_NET_CX82310_ETH is not set
+# CONFIG_USB_NET_KALMIA is not set
+# CONFIG_USB_HSO is not set
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_SIERRA_NET is not set
+# CONFIG_USB_VL600 is not set
+CONFIG_WLAN=y
+CONFIG_USB_ZD1201=y
+# CONFIG_HOSTAP is not set
+CONFIG_WL12XX_PLATFORM_DATA=y
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_TCA6416 is not set
+CONFIG_KEYBOARD_MATRIX=y
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_TWL4030 is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+CONFIG_TOUCHSCREEN_TI_TSCADC=y
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_TWL4030_PWRBUTTON is not set
+# CONFIG_INPUT_TWL4030_VIBRA is not set
+# CONFIG_INPUT_TWL6040_VIBRA is not set
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_CMA3000 is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_OMAP=y
+CONFIG_SERIAL_OMAP_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_HVC_DCC is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_OC_TINY is not set
+CONFIG_SPI_OMAP24XX=y
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+
+#
+# Enable Device Drivers -> PPS to see the PTP clock options.
+#
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO drivers:
+#
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_IT8761E is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_TWL4030 is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_74X164 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+CONFIG_GPIO_TPS65910=y
+CONFIG_GENERIC_PWM=y
+CONFIG_DAVINCI_EHRPWM=y
+CONFIG_ECAP_PWM=y
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_GPIO_FAN is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+CONFIG_SENSORS_LM75=y
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_CORE is not set
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_DW_WATCHDOG is not set
+CONFIG_OMAP_WATCHDOG=y
+# CONFIG_TWL4030_WATCHDOG is not set
+# CONFIG_MAX63XX_WATCHDOG is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+CONFIG_MFD_TPS65217=y
+# CONFIG_MFD_TPS6586X is not set
+CONFIG_MFD_TPS65910=y
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+CONFIG_TWL4030_CORE=y
+# CONFIG_TWL4030_MADC is not set
+CONFIG_TWL4030_POWER=y
+# CONFIG_MFD_TWL4030_AUDIO is not set
+# CONFIG_TWL6030_PWM is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13XXX is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+CONFIG_REGULATOR_DUMMY=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_GPIO is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_TWL4030 is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+CONFIG_REGULATOR_TPS65217=y
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_TPS6524X is not set
+CONFIG_REGULATOR_TPS65910=y
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+# CONFIG_RC_CORE is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA827X=y
+CONFIG_MEDIA_TUNER_TDA18271=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_XC4000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+
+#
+# Encoders, decoders, sensors and other helper chips
+#
+
+#
+# Audio decoders, processors and mixers
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+
+#
+# RDS decoders
+#
+# CONFIG_VIDEO_SAA6588 is not set
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_SAA7110 is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA7191 is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_TVP7002 is not set
+# CONFIG_VIDEO_VPX3220 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_CX25840 is not set
+
+#
+# MPEG video encoders
+#
+# CONFIG_VIDEO_CX2341X is not set
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_AK881X is not set
+
+#
+# Camera sensor devices
+#
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+
+#
+# Flash devices
+#
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+
+#
+# Miscelaneous helper chips
+#
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_VPFE_CAPTURE is not set
+# CONFIG_VIDEO_OMAP2_VOUT is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+# CONFIG_RADIO_ADAPTERS is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_WMT_GE_ROPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+CONFIG_FB_DA8XX=y
+CONFIG_FB_DA8XX_CONSISTENT_DMA_SIZE=5
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_OMAP is not set
+# CONFIG_OMAP2_DSS is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_LCD_S6E63M0 is not set
+# CONFIG_LCD_LD9040 is not set
+# CONFIG_LCD_AMS369FG06 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+CONFIG_BACKLIGHT_TLC59108=y
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=y
+CONFIG_SND_RAWMIDI=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_ALOOP is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=y
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_USB_6FIRE is not set
+CONFIG_SND_SOC=y
+# CONFIG_SND_SOC_CACHE_LZO is not set
+CONFIG_SND_AM33XX_SOC=y
+CONFIG_SND_DAVINCI_SOC_MCASP=y
+CONFIG_SND_AM335X_SOC_EVM=y
+# CONFIG_SND_OMAP_SOC is not set
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_TLV320AIC3X=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_A4TECH=y
+# CONFIG_HID_ACRUX is not set
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+# CONFIG_HID_PRODIKEYS is not set
+CONFIG_HID_CYPRESS=y
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+CONFIG_HID_EZKEY=y
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_KEYTOUCH is not set
+CONFIG_HID_KYE=y
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+CONFIG_HID_KENSINGTON=y
+# CONFIG_HID_LCPOWER is not set
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_LOGITECH_DJ=m
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+# CONFIG_LOGIG940_FF is not set
+# CONFIG_LOGIWHEELS_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB_ARCH_HAS_XHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_DWC3 is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_MUSB_HDRC=y
+
+#
+# Platform Glue Layer
+#
+# CONFIG_USB_MUSB_TUSB6010_GLUE is not set
+# CONFIG_USB_MUSB_OMAP2PLUS_GLUE is not set
+# CONFIG_USB_MUSB_AM35X_GLUE is not set
+CONFIG_USB_MUSB_TI81XX_GLUE=y
+# CONFIG_USB_MUSB_DAVINCI is not set
+# CONFIG_USB_MUSB_DA8XX is not set
+# CONFIG_USB_MUSB_TUSB6010 is not set
+# CONFIG_USB_MUSB_OMAP2PLUS is not set
+# CONFIG_USB_MUSB_AM35X is not set
+CONFIG_USB_MUSB_TI81XX=y
+# CONFIG_USB_MUSB_BLACKFIN is not set
+# CONFIG_USB_MUSB_UX500 is not set
+CONFIG_MUSB_PIO_ONLY=y
+# CONFIG_USB_INVENTRA_DMA is not set
+# CONFIG_USB_TI_CPPI_DMA is not set
+# CONFIG_USB_TI_CPPI41_DMA is not set
+# CONFIG_USB_TUSB_OMAP_DMA is not set
+# CONFIG_USB_UX500_DMA is not set
+# CONFIG_USB_RENESAS_USBHS is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+# CONFIG_USB_UAS is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+# CONFIG_USB_FUSB300 is not set
+# CONFIG_USB_OMAP is not set
+# CONFIG_USB_R8A66597 is not set
+CONFIG_USB_GADGET_MUSB_HDRC=y
+# CONFIG_USB_M66592 is not set
+# CONFIG_USB_NET2272 is not set
+# CONFIG_USB_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+# CONFIG_USB_G_NCM is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FUNCTIONFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_MASS_STORAGE=m
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_ACM_MS is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_WEBCAM is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_TWL6030_USB is not set
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_SDHCI_PXAV3 is not set
+# CONFIG_MMC_SDHCI_PXAV2 is not set
+# CONFIG_MMC_OMAP is not set
+CONFIG_MMC_OMAP_HS=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_MMC_DW is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_PWM is not set
+# CONFIG_LEDS_REGULATOR is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_RENESAS_TPU is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_TWL4030 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_OMAP=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_BALLOON is not set
+# CONFIG_VIRTIO_MMIO is not set
+# CONFIG_STAGING is not set
+CONFIG_CLKDEV_LOOKUP=y
+
+#
+# Hardware Spinlock drivers
+#
+CONFIG_CLKSRC_MMIO=y
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_VIRT_DRIVERS is not set
+# CONFIG_PM_DEVFREQ is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+CONFIG_QUOTA=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QUOTA_DEBUG is not set
+CONFIG_QUOTA_TREE=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_TMPFS_XATTR is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFS_USE_NEW_IDMAPPER is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_LKDTM is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_RING_BUFFER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_STRICT_DEVMEM is not set
+# CONFIG_ARM_UNWIND is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_JTAG_ENABLE=y
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_NETWORK is not set
+# CONFIG_SECURITY_PATH is not set
+# CONFIG_SECURITY_TOMOYO is not set
+# CONFIG_SECURITY_APPARMOR is not set
+# CONFIG_IMA is not set
+# CONFIG_EVM is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_USER is not set
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_OMAP4_AES=y
+CONFIG_CRYPTO_DEV_OMAP4_SHAM=y
+
+#
+# OCF Configuration
+#
+CONFIG_OCF_OCF=y
+# CONFIG_OCF_RANDOMHARVEST is not set
+CONFIG_OCF_CRYPTODEV=y
+CONFIG_OCF_CRYPTOSOFT=y
+# CONFIG_OCF_OCFNULL is not set
+# CONFIG_OCF_BENCH is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+# CONFIG_CRC8 is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_XZ_DEC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_BCJ=y
+# CONFIG_XZ_DEC_TEST is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
+CONFIG_AVERAGE=y
+# CONFIG_CORDIC is not set
index e44e942ca5ce41945a6c70b61daf18e40ca6138c..f13e9dc330173626bfd65501d55112c183fd33fe 100644 (file)
@@ -372,6 +372,15 @@ config OMAP3_EMU
        help
          Say Y here to enable debugging hardware of omap3
 
+config TI_PM_DISABLE_VT_SWITCH
+       bool "TI Disable PM Console Switch"
+       depends on ARCH_OMAP3
+       default y
+       help
+         This option disables the default PM VT switch behavior for TI devices.
+         Some platforms hang during suspend due to a failed attempt to
+         perform the VT switch.  The VT switch is unnecessary on many platforms.
+
 config OMAP3_SDRC_AC_TIMING
        bool "Enable SDRC AC timing register changes"
        depends on ARCH_OMAP3
index f275e746d0625a16e4f9c490a52f8c06f32e345c..c01b62d954044466e539e51d046ab99bb30f0ffa 100644 (file)
@@ -73,6 +73,7 @@ obj-$(CONFIG_SOC_OMAPAM33XX)          += cpuidle33xx.o pm33xx.o \
 obj-$(CONFIG_PM_DEBUG)                 += pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
 obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)  += smartreflex-class3.o
+obj-$(CONFIG_AM33XX_SMARTREFLEX)        += am33xx-smartreflex-class2.o
 
 AFLAGS_sleep24xx.o                     :=-Wa,-march=armv6
 AFLAGS_sleep34xx.o                     :=-Wa,-march=armv7-a$(plus_sec)
diff --git a/arch/arm/mach-omap2/am33xx-smartreflex-class2.c b/arch/arm/mach-omap2/am33xx-smartreflex-class2.c
new file mode 100644 (file)
index 0000000..66f98b7
--- /dev/null
@@ -0,0 +1,1055 @@
+/*
+ * SmartReflex Voltage Control driver
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
+ * Author: Greg Guyotte <gguyotte@ti.com> (modified for AM33xx)
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
+ * Author: AnilKumar Ch <anilkumar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/debugfs.h>
+#include <linux/slab.h>
+#include <linux/regulator/consumer.h>
+#include <linux/cpufreq.h>
+#include <linux/opp.h>
+
+#include <plat/common.h>
+#include <plat/smartreflex.h>
+
+#include "control.h"
+#include "voltage.h"
+
+#define CLK_NAME_LEN           40
+
+static inline void sr_write_reg(struct am33xx_sr *sr, int offset, u32 value,
+                                       u32 srid)
+{
+       writel(value, sr->sen[srid].base + offset);
+}
+
+static inline void sr_modify_reg(struct am33xx_sr *sr, int offset, u32 mask,
+                               u32 value, u32 srid)
+{
+       u32 reg_val;
+
+       reg_val = readl(sr->sen[srid].base + offset);
+       reg_val &= ~mask;
+       reg_val |= (value&mask);
+
+       writel(reg_val, sr->sen[srid].base + offset);
+}
+
+static inline u32 sr_read_reg(struct am33xx_sr *sr, int offset, u32 srid)
+{
+       return readl(sr->sen[srid].base + offset);
+}
+
+static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen) {
+         u32 gn, rn, mul;
+         for (gn = 0; gn < GAIN_MAXLIMIT; gn++) {
+                 mul = 1 << (gn + 8);
+                 rn = mul / sensor;
+                 if (rn < R_MAXLIMIT) {
+                         *sengain = gn;
+                         *rnsen = rn;
+                 }
+         }
+}
+static u32 cal_test_nvalue(u32 sennval, u32 senpval) {
+         u32 senpgain=0, senngain=0;
+         u32 rnsenp=0, rnsenn=0;
+         /* Calculating the gain and reciprocal of the SenN and SenP values */
+         cal_reciprocal(senpval, &senpgain, &rnsenp);
+         cal_reciprocal(sennval, &senngain, &rnsenn);
+         return (senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
+                 (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
+                 (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
+                 (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT);
+}
+
+static unsigned int sr_adjust_efuse_nvalue(unsigned int opp_no,
+                                                 unsigned int orig_opp_nvalue,
+                                                 unsigned int mv_delta) {
+         unsigned int new_opp_nvalue;
+         unsigned int senp_gain, senn_gain, rnsenp, rnsenn, pnt_delta, nnt_delta;
+         unsigned int new_senn, new_senp, senn, senp;
+         /* calculate SenN and SenP from the efuse value */
+         senp_gain = ((orig_opp_nvalue >> 20) & 0xf);
+         senn_gain = ((orig_opp_nvalue >> 16) & 0xf);
+         rnsenp = ((orig_opp_nvalue >> 8) & 0xff);
+         rnsenn = (orig_opp_nvalue & 0xff);
+         senp = ((1<<(senp_gain+8))/(rnsenp));
+         senn = ((1<<(senn_gain+8))/(rnsenn));
+         /* calculate the voltage delta */
+         pnt_delta = (26 * mv_delta)/10;
+         nnt_delta = (3 * mv_delta);
+         /* now lets add the voltage delta to the sensor values */
+         new_senn = senn + nnt_delta;
+         new_senp = senp + pnt_delta;
+         new_opp_nvalue = cal_test_nvalue(new_senn, new_senp);
+         printk("Compensating OPP%d for %dmV Orig nvalue:0x%x New nvalue:0x%x \n",
+                         opp_no, mv_delta, orig_opp_nvalue, new_opp_nvalue);
+         return new_opp_nvalue;
+}
+
+/* irq_sr_reenable - Re-enable SR interrupts (triggered by delayed work queue)
+ * @work:      pointer to work_struct embedded in am33xx_sr_sensor struct
+ *
+ * While servicing the IRQ, this function is added to the delayed work queue.
+ * This gives time for the voltage change to settle before we re-enable 
+ * the interrupt.
+ */
+static void irq_sr_reenable(struct work_struct *work)
+{
+        u32 srid;
+       struct am33xx_sr_sensor *sens;
+        struct am33xx_sr *sr;
+
+        sens = container_of((void *)work, struct am33xx_sr_sensor, 
+                work_reenable);
+
+        srid = sens->sr_id;
+
+        sr = container_of((void *)sens, struct am33xx_sr, sen[srid]);
+
+        dev_dbg(&sr->pdev->dev, "%s: SR %d\n", __func__, srid);
+
+        /* Must clear IRQ status */
+        sens->irq_status = 0;
+
+        /* Re-enable the interrupt */
+       sr_modify_reg(sr, IRQENABLE_SET, IRQENABLE_MCUBOUNDSINT,
+               IRQENABLE_MCUBOUNDSINT, srid);
+
+       /* Restart the module after voltage set */
+       sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
+               SRCONFIG_SRENABLE, srid);
+}
+
+/* get_errvolt - get error voltage from SR error register
+ * @sr:                contains SR driver data
+ * @srid:      contains the srid, indicates which SR moduel lswe are using
+ *
+ * Read the error from SENSOR error register and then convert
+ * to voltage delta, return value is the voltage delta in micro
+ * volt.
+ */
+static int get_errvolt(struct am33xx_sr *sr, s32 srid)
+{
+        struct am33xx_sr_sensor *sens;
+       int senerror_reg;
+       s32 uvoltage;
+       s8 terror;
+
+        sens = &sr->sen[srid];
+
+       senerror_reg = sr_read_reg(sr, SENERROR_V2, srid);
+       senerror_reg = (senerror_reg & 0x0000FF00);
+       terror = (s8)(senerror_reg >> 8);
+
+        /* math defined in SR functional spec */
+       uvoltage = ((terror) * sr->uvoltage_step_size) >> 7;
+       uvoltage = uvoltage * sens->opp_data[sens->curr_opp].e2v_gain;
+
+       return uvoltage;
+}
+
+/* set_voltage - Schedule task for setting the voltage
+ * @work:      pointer to the work structure
+ *
+ * Voltage is set based on previous voltage and calculated
+ * voltage error.
+ *
+ * Generic voltage regulator set voltage is used for changing
+ * the voltage to new value.  Could potentially use voltdm_scale
+ * but at time of testing voltdm was not populated with volt_data.
+ *
+ * Disabling the module before changing the voltage, this is
+ * needed for not generating interrupt during voltage change,
+ * enabling after voltage change. This will also take care of
+ * resetting the SR registers.
+ */
+static void set_voltage(struct work_struct *work)
+{
+       struct am33xx_sr *sr;
+       int prev_volt, new_volt, i, ret;
+       s32 delta_v;
+
+       sr = container_of((void *)work, struct am33xx_sr, work);
+
+        for (i = 0; i < sr->no_of_sens; i++) {
+                if (sr->sen[i].irq_status != 1)
+                        continue;
+
+                /* Get the current voltage from PMIC */
+                prev_volt = regulator_get_voltage(sr->sen[i].reg);
+
+                if (prev_volt < 0) {
+                        dev_err(&sr->pdev->dev, 
+                                "%s: SR %d: regulator_get_voltage error %d\n",
+                                __func__, i, prev_volt);
+
+                        goto reenable;
+                }
+
+               delta_v = get_errvolt(sr, i);
+                new_volt = prev_volt + delta_v;
+
+                /* this is the primary output for debugging SR activity */
+                dev_dbg(&sr->pdev->dev, 
+                        "%s: SR %d: prev volt=%d, delta_v=%d, req_volt=%d\n",
+                         __func__, i, prev_volt, delta_v, new_volt);
+         
+               /* Clear the counter, SR module disable */
+               sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
+                       ~SRCONFIG_SRENABLE, i);
+
+                if (delta_v != 0) {
+                       ret = regulator_set_voltage(sr->sen[i].reg, new_volt, 
+                                new_volt + sr->uvoltage_step_size);
+
+                        if (ret < 0)
+                                dev_err(&sr->pdev->dev, 
+                                "%s: regulator_set_voltage failed! (err %d)\n", 
+                                __func__, ret);
+                }
+reenable:
+                /* allow time for voltage to settle before re-enabling SR 
+                   module and interrupt */        
+                schedule_delayed_work(&sr->sen[i].work_reenable, 
+                        msecs_to_jiffies(sr->irq_delay));
+        }
+}
+
+/* sr_class2_irq - sr irq handling
+ * @irq:       Number of the irq serviced
+ * @data:      data contains the SR driver structure
+ *
+ * Smartreflex IRQ handling for class2 IP, once the IRQ handler
+ * is here then disable the interrupt and re-enable after some
+ * time. This is the work around for handling both interrupts,
+ * while one got satisfied with the voltage change but not the
+ * other. The same logic helps the case where PMIC cannot set
+ * the exact voltage requested by SR IP
+ *
+ * Schedule work only if both interrupts are serviced
+ *
+ * Note that same irq handler is used for both the interrupts,
+ * needed for decision making for voltage change
+ */
+static irqreturn_t sr_class2_irq(int irq, void *data)
+{
+       u32 srid;
+        struct am33xx_sr *sr;
+        struct am33xx_sr_sensor *sr_sensor = (struct am33xx_sr_sensor *)data;
+
+        srid = sr_sensor->sr_id;
+
+        sr = container_of(data, struct am33xx_sr, sen[srid]);
+
+       sr->sen[srid].irq_status = 1;
+
+       /* Clear MCUBounds Interrupt */
+       sr_modify_reg(sr, IRQSTATUS, IRQSTATUS_MCBOUNDSINT,
+                       IRQSTATUS_MCBOUNDSINT, srid);
+
+       /* Disable the interrupt and re-enable in set_voltage() */
+       sr_modify_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUBOUNDSINT,
+                       IRQENABLE_MCUBOUNDSINT, srid);
+
+        /* Causes set_voltage() to get called at a later time.  Set_voltage()
+           will check the irq_status flags to determine which SR needs to
+           be serviced.  This was previously done with schedule_work, but
+           I observed a crash in set_voltage() when changing OPPs on weak
+           silicon, which may have been related to insufficient voltage
+           settling time for OPP change.  This additional delay avoids the
+           crash. */
+        schedule_delayed_work(&sr->work, 
+                        msecs_to_jiffies(250));
+
+       return IRQ_HANDLED;
+}
+
+static int sr_clk_enable(struct am33xx_sr *sr, u32 srid)
+{
+       if (clk_enable(sr->sen[srid].fck) != 0) {
+               dev_err(&sr->pdev->dev, "%s: Could not enable sr_fck\n",
+                                       __func__);
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+static int sr_clk_disable(struct am33xx_sr *sr, u32 srid)
+{
+       clk_disable(sr->sen[srid].fck);
+
+       return 0;
+}
+
+static inline int sr_set_nvalues(struct am33xx_sr *sr, u32 srid)
+{
+        int i;
+        struct am33xx_sr_sensor *sens = &sr->sen[srid];
+
+        for (i = 0; i < sens->no_of_opps; i++) {
+               /* Read nTarget value form EFUSE register*/
+               sens->opp_data[i].nvalue = readl(AM33XX_CTRL_REGADDR
+                       (sens->opp_data[i].efuse_offs)) & 0xFFFFFF;
+
+                /* validate nTarget value */
+                if (sens->opp_data[i].nvalue == 0)
+                        return -EINVAL;
+
+                /* adjust nTarget based on margin in mv */
+                sens->opp_data[i].adj_nvalue = sr_adjust_efuse_nvalue(i, 
+                        sens->opp_data[i].nvalue, 
+                        sens->opp_data[i].margin);
+
+                dev_dbg(&sr->pdev->dev, 
+                        "NValueReciprocal value (from efuse) = %08x\n", 
+                        sens->opp_data[i].nvalue);
+
+                dev_dbg(&sr->pdev->dev, 
+                        "Adjusted NValueReciprocal value = %08x\n", 
+                        sens->opp_data[i].adj_nvalue);
+        }
+       return 0;
+}
+
+/* sr_configure - Configure SR module to work in Error generator mode
+ * @sr:                contains SR driver data
+ * @srid:      contains the srid, specify whether it is CORE or MPU
+ *
+ * Configure the corresponding values to SR module registers for
+ * operating SR module in Error Generator mode.
+ */
+static void sr_configure(struct am33xx_sr *sr, u32 srid)
+{
+        struct am33xx_sr_sensor *sens = &sr->sen[srid];
+
+       /* Configuring the SR module with clock length, enabling the
+        * error generator, enable SR module, enable individual N and P
+        * sensors
+        */
+       sr_write_reg(sr, SRCONFIG, (SRCLKLENGTH_125MHZ_SYSCLK |
+               SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
+               (sens->senn_en << SRCONFIG_SENNENABLE_V2_SHIFT) |
+               (sens->senp_en << SRCONFIG_SENPENABLE_V2_SHIFT)),
+               srid);
+
+       /* Configuring the Error Generator */
+       sr_modify_reg(sr, ERRCONFIG_V2, (SR_ERRWEIGHT_MASK |
+               SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
+               ((sens->opp_data[sens->curr_opp].err_weight << 
+                        ERRCONFIG_ERRWEIGHT_SHIFT) |
+               (sens->opp_data[sens->curr_opp].err_maxlimit << 
+                        ERRCONFIG_ERRMAXLIMIT_SHIFT) |
+               (sens->opp_data[sens->curr_opp].err_minlimit <<          
+                        ERRCONFIG_ERRMINLIMIT_SHIFT)),
+               srid);
+}
+
+/* sr_enable - Enable SR module
+ * @sr:                contains SR driver data
+ * @srid:      contains the srid, specify whether it is CORE or MPU
+ *
+ * Enable SR module by writing nTarget values to corresponding SR
+ * NVALUERECIPROCAL register, enable the interrupt and enable SR
+ */
+static void sr_enable(struct am33xx_sr *sr, u32 srid)
+{
+        struct am33xx_sr_sensor *sens;
+
+        sens = &sr->sen[srid];
+
+       /* Check if SR is already enabled. If yes do nothing */
+       if (sr_read_reg(sr, SRCONFIG, srid) & SRCONFIG_SRENABLE)
+               return;
+
+       if (sens->opp_data[sens->curr_opp].nvalue == 0)
+               dev_err(&sr->pdev->dev, 
+                        "%s: OPP doesn't support SmartReflex\n", __func__);
+
+       /* Writing the nReciprocal value to the register */
+       sr_write_reg(sr, NVALUERECIPROCAL, 
+                sens->opp_data[sens->curr_opp].adj_nvalue, srid);
+
+       /* Enable the interrupt */
+       sr_modify_reg(sr, IRQENABLE_SET, IRQENABLE_MCUBOUNDSINT,
+                               IRQENABLE_MCUBOUNDSINT, srid);
+
+       /* SRCONFIG - enable SR */
+       sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
+                               SRCONFIG_SRENABLE, srid);
+}
+
+/* sr_disable - Disable SR module
+ * @sr:                contains SR driver data
+ * @srid:      contains the srid, specify whether it is CORE or MPU
+ *
+ * Disable SR module by disabling the interrupt and Smartreflex module
+ */
+static void sr_disable(struct am33xx_sr *sr, u32 srid)
+{
+       /* Disable the interrupt */
+       sr_modify_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUBOUNDSINT,
+                               IRQENABLE_MCUBOUNDSINT, srid);
+
+       /* SRCONFIG - disable SR */
+       sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
+                               ~SRCONFIG_SRENABLE, srid);
+}
+
+/* sr_start_vddautocomp - Start VDD auto compensation
+ * @sr:                contains SR driver data
+ *
+ * This is the starting point for AVS enable from user space.
+ * Also used to re-enable SR after OPP change.
+ */
+static void sr_start_vddautocomp(struct am33xx_sr *sr)
+{
+       int i;
+
+       if ((sr->sen[SR_CORE].opp_data[0].nvalue == 0) || 
+                (sr->sen[SR_MPU].opp_data[0].nvalue == 0)) {
+               dev_err(&sr->pdev->dev, "SR module not enabled, nTarget"
+                                       " values are not found\n");
+               return;
+       }
+
+       if (sr->autocomp_active == 1) {
+               dev_warn(&sr->pdev->dev, "SR VDD autocomp already active\n");
+               return;
+       }
+
+       for (i = 0; i < sr->no_of_sens; i++) {
+                       /* Read current regulator value and voltage */
+               sr->sen[i].init_volt_mv = regulator_get_voltage(sr->sen[i].reg);
+
+                dev_dbg(&sr->pdev->dev, "%s: regulator %d, init_volt = %d\n", 
+                        __func__, i, sr->sen[i].init_volt_mv);
+
+               if (sr_clk_enable(sr, i))
+                        return;
+               sr_configure(sr, i);
+               sr_enable(sr, i);
+       }
+
+       sr->autocomp_active = 1;
+}
+
+/* sr_stop_vddautocomp - Stop VDD auto compensation
+ * @sr:                contains SR driver data
+ *
+ * This is the ending point during SR disable from user space.
+ * Also used to disable SR after OPP change.
+ */
+static void sr_stop_vddautocomp(struct am33xx_sr *sr)
+{
+       int i;
+
+       if (sr->autocomp_active == 0) {
+               dev_warn(&sr->pdev->dev, "SR VDD autocomp is not active\n");
+               return;
+       }
+
+        /* cancel bottom half interrupt handlers that haven't run yet */
+       cancel_delayed_work_sync(&sr->work);
+       
+       for (i = 0; i < sr->no_of_sens; i++) {
+                /* cancel any outstanding SR IRQ re-enables on work queue */
+                cancel_delayed_work_sync(&sr->sen[i].work_reenable);
+               sr_disable(sr, i);
+               sr_clk_disable(sr, i);
+       }
+       
+       sr->autocomp_active = 0;
+}
+
+/* am33xx_sr_autocomp_show - Store user input value and stop SR
+ * @data:              contains SR driver data
+ * @val:               pointer to store autocomp_active status
+ *
+ * This is the Debug Fs enteries to show whether SR is enabled
+ * or disabled
+ */
+static int am33xx_sr_autocomp_show(void *data, u64 *val)
+{
+       struct am33xx_sr *sr_info = (struct am33xx_sr *) data;
+
+       *val = (u64) sr_info->autocomp_active;
+
+       return 0;
+}
+
+static int am33xx_sr_margin_show(void *data, u64 *val)
+{
+        struct am33xx_sr_opp_data *sr_opp_data = (struct am33xx_sr_opp_data *)data;
+
+       *val = (u64) sr_opp_data->margin;
+
+       return 0;
+}
+
+static int am33xx_sr_margin_update(void *data, u64 val)
+{
+        struct am33xx_sr_opp_data *sr_opp_data = 
+                (struct am33xx_sr_opp_data *)data;
+        struct am33xx_sr_sensor *sr_sensor;
+        struct am33xx_sr *sr_info;
+
+        /* work back to the sr_info pointer */
+        sr_sensor = container_of((void *)sr_opp_data, struct am33xx_sr_sensor, 
+                opp_data[sr_opp_data->opp_id]); 
+
+        sr_info = container_of((void *)sr_sensor, struct am33xx_sr, 
+                sen[sr_sensor->sr_id]);
+
+        /* store the value of margin */
+        sr_opp_data->margin = (s32)val;
+
+        dev_warn(&sr_info->pdev->dev, "%s: new margin=%d, srid=%d, opp=%d\n",
+                __func__, sr_opp_data->margin, sr_sensor->sr_id, 
+                sr_opp_data->opp_id);
+
+        /* updata ntarget values based upon new margin */
+        if (sr_set_nvalues(sr_info, sr_sensor->sr_id) == -EINVAL)
+                dev_err(&sr_info->pdev->dev,
+                        "%s: Zero NValue read from EFUSE\n", __func__);
+
+        /* restart SmartReflex to adapt to new values */
+        sr_stop_vddautocomp(sr_info);
+        sr_start_vddautocomp(sr_info);
+
+        return 0;
+}
+
+/* am33xx_sr_autocomp_store - Store user input and start SR
+ * @data:              contains SR driver data
+ * @val:               contains the value pased by user
+ *
+ * This is the Debug Fs enteries to store user input and
+ * enable smartreflex.
+ */
+static int am33xx_sr_autocomp_store(void *data, u64 val)
+{
+       struct am33xx_sr *sr_info = (struct am33xx_sr *) data;
+
+       /* Sanity check */
+       if (val && (val != 1)) {
+               dev_warn(&sr_info->pdev->dev, "%s: Invalid argument %llu\n",
+                       __func__, val);
+               return -EINVAL;
+       }
+
+       if (!val) {
+                sr_info->disabled_by_user = 1;
+               sr_stop_vddautocomp(sr_info);
+        }
+       else {
+                sr_info->disabled_by_user = 0;
+               sr_start_vddautocomp(sr_info);
+        }
+
+       return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(sr_fops, am33xx_sr_autocomp_show,
+               am33xx_sr_autocomp_store, "%llu\n");
+
+/* sr_curr_volt_show - Show current voltage value
+ * @data:              contains SR driver data
+ * @val:               pointer to store current voltage value
+ *
+ * Read the current voltage value and display the same on console
+ * This is used in debugfs entries
+ */
+static int am33xx_sr_curr_volt_show(void *data, u64 *val)
+{
+       struct am33xx_sr_sensor *sr_sensor = (struct am33xx_sr_sensor *) data;
+
+       *val = (u64) regulator_get_voltage(sr_sensor->reg);
+
+       return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(curr_volt_fops, am33xx_sr_curr_volt_show,
+               NULL, "%llu\n");
+
+DEFINE_SIMPLE_ATTRIBUTE(margin_fops, am33xx_sr_margin_show,
+               am33xx_sr_margin_update, "%llu\n");
+
+#ifdef CONFIG_DEBUG_FS
+/* sr_debugfs_entries - Create debugfs entries
+ * @sr_info:           contains SR driver data
+ *
+ * Create debugfs entries, which is exposed to user for knowing
+ * the current status. Some of the parameters can change during
+ * run time
+ */
+static int sr_debugfs_entries(struct am33xx_sr *sr_info)
+{
+        struct am33xx_sr_sensor *sens;
+       struct dentry *dbg_dir, *sen_dir, *opp_dir;
+       int i, j;
+
+       dbg_dir = debugfs_create_dir("smartreflex", NULL);
+       if (IS_ERR(dbg_dir)) {
+               dev_err(&sr_info->pdev->dev, "%s: Unable to create debugfs"
+                               " directory\n", __func__);
+               return PTR_ERR(dbg_dir);
+       }
+
+       (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUGO, dbg_dir,
+                               (void *)sr_info, &sr_fops);
+        (void) debugfs_create_u32("interrupt_delay", S_IRUGO | S_IWUGO,
+                               dbg_dir, &sr_info->irq_delay);
+
+       for (i = 0; i < sr_info->no_of_sens; i++) {
+                sens = &sr_info->sen[i];
+               sen_dir = debugfs_create_dir(sens->name, dbg_dir);
+               if (IS_ERR(sen_dir)) {
+                       dev_err(&sr_info->pdev->dev, "%s: Unable to create"
+                               " debugfs directory\n", __func__);
+                       return PTR_ERR(sen_dir);
+               }
+
+                (void)debugfs_create_u32("initial_voltage", S_IRUGO, sen_dir,
+                               &sens->init_volt_mv);
+               (void)debugfs_create_file("current_voltage", S_IRUGO, sen_dir,
+                               (void *)sens, &curr_volt_fops);
+               
+                for (j = 0; j < sr_info->sen[i].no_of_opps; j++) {
+                        char tmp[20];
+
+                        sprintf(&tmp[0], "opp%d", j);
+                        opp_dir = debugfs_create_dir(tmp, sen_dir);
+                        if (IS_ERR(opp_dir)) {
+                               dev_err(&sr_info->pdev->dev, 
+                                        "%s: Unable to create debugfs directory\n", 
+                                        __func__);
+                               return PTR_ERR(opp_dir);
+                       }
+
+                        (void)debugfs_create_file("margin", S_IRUGO | S_IWUGO,
+                              opp_dir, (void *)&sens->opp_data[j], 
+                               &margin_fops);
+                        (void)debugfs_create_x32("err2voltgain", 
+                               S_IRUGO | S_IWUGO,
+                              opp_dir, 
+                               &sens->opp_data[j].e2v_gain);
+                       (void)debugfs_create_x32("nvalue", S_IRUGO,
+                              opp_dir, 
+                               &sens->opp_data[j].nvalue);
+                        (void)debugfs_create_x32("adj_nvalue", S_IRUGO,
+                              opp_dir, 
+                               &sens->opp_data[j].adj_nvalue);
+                }
+       }
+       return 0;
+}
+#else
+static int sr_debugfs_entries(struct am33xx_sr *sr_info)
+{
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_CPU_FREQ
+
+/* Find and return current OPP.  This should change to use system APIs,
+   but voltdm is not currently populated, and opp APIs are also not working. */
+static int get_current_opp(struct am33xx_sr *sr, u32 srid, u32 freq)  {
+        int i;
+
+        for (i = 0; i < sr->sen[srid].no_of_opps; i++) {
+                if (sr->sen[srid].opp_data[i].frequency == freq)
+                        return i;
+        }
+
+        return -EINVAL;
+}
+
+static int am33xx_sr_cpufreq_transition(struct notifier_block *nb,
+                                         unsigned long val, void *data)
+{
+        struct am33xx_sr *sr;
+        struct cpufreq_freqs *cpu;
+
+       sr = container_of(nb, struct am33xx_sr, freq_transition);
+
+        /* We are required to disable SR while OPP change is occurring */
+       if (val == CPUFREQ_PRECHANGE) {
+                dev_dbg(&sr->pdev->dev, "%s: prechange\n", __func__);
+                sr_stop_vddautocomp(sr);
+       } else if (val == CPUFREQ_POSTCHANGE) {
+                cpu = (struct cpufreq_freqs *)data;
+                dev_dbg(&sr->pdev->dev, 
+                        "%s: postchange, cpu=%d, old=%d, new=%d\n", 
+                        __func__, cpu->cpu, cpu->old, cpu->new);
+
+                /* update current OPP */
+                sr->sen[SR_MPU].curr_opp = get_current_opp(sr, SR_MPU, 
+                        cpu->new*1000);
+                if (sr->sen[SR_MPU].curr_opp == -EINVAL) {
+                        dev_err(&sr->pdev->dev, "%s: cannot determine opp\n",
+                                __func__);
+                        return -EINVAL;
+                }
+
+                dev_dbg(&sr->pdev->dev, "%s: postchange, new opp=%d\n", 
+                        __func__, sr->sen[SR_MPU].curr_opp);
+
+                /* this handles the case when the user has disabled SR via 
+                   debugfs, therefore we do not want to enable SR */
+                if (sr->disabled_by_user == 0)
+                        sr_start_vddautocomp(sr);
+       }
+
+       return 0;
+}
+
+static inline int am33xx_sr_cpufreq_register(struct am33xx_sr *sr)
+{
+        sr->freq_transition.notifier_call = am33xx_sr_cpufreq_transition;
+
+       return cpufreq_register_notifier(&sr->freq_transition,
+                                        CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+static inline void am33xx_sr_cpufreq_deregister(struct am33xx_sr *sr)
+{
+       cpufreq_unregister_notifier(&sr->freq_transition,
+                                   CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+#endif
+
+static int __init am33xx_sr_probe(struct platform_device *pdev)
+{
+       struct am33xx_sr *sr_info;
+       struct am33xx_sr_platform_data *pdata;
+       struct resource *res[MAX_SENSORS];
+       int irq;
+       int ret;
+       int i,j;
+
+       sr_info = kzalloc(sizeof(struct am33xx_sr), GFP_KERNEL);
+       if (!sr_info) {
+               dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
+                                       __func__);
+               return -ENOMEM;
+       }
+
+       pdata = pdev->dev.platform_data;
+       if (!pdata) {
+               dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
+               ret = -EINVAL;
+               goto err_free_sr_info;
+       }
+
+       sr_info->pdev = pdev;
+       sr_info->sen[SR_CORE].name = "smartreflex0";
+       sr_info->sen[SR_MPU].name = "smartreflex1";
+       sr_info->ip_type = pdata->ip_type;
+        sr_info->irq_delay = pdata->irq_delay;
+        sr_info->no_of_sens = pdata->no_of_sens;
+        sr_info->no_of_vds = pdata->no_of_vds;
+       sr_info->uvoltage_step_size = pdata->vstep_size_uv;
+       sr_info->autocomp_active = false;
+        sr_info->disabled_by_user = false;
+               
+       for (i = 0; i < sr_info->no_of_sens; i++) {
+                u32 curr_freq=0;
+
+                sr_info->sen[i].reg_name = pdata->vd_name[i];
+
+                /* this should be determined from voltdm or opp layer, but
+                   those approaches are not working */
+                sr_info->sen[i].no_of_opps = pdata->sr_sdata[i].no_of_opps;  
+                sr_info->sen[i].sr_id = i;
+
+                /* Reading per OPP Values */
+                for (j = 0; j < sr_info->sen[i].no_of_opps; j++) {
+                       sr_info->sen[i].opp_data[j].efuse_offs = 
+                                pdata->sr_sdata[i].sr_opp_data[j].efuse_offs;
+                        sr_info->sen[i].opp_data[j].e2v_gain = 
+                                pdata->sr_sdata[i].sr_opp_data[j].e2v_gain;
+                       sr_info->sen[i].opp_data[j].err_weight = 
+                                pdata->sr_sdata[i].sr_opp_data[j].err_weight;
+                       sr_info->sen[i].opp_data[j].err_minlimit = 
+                                pdata->sr_sdata[i].sr_opp_data[j].err_minlimit;
+                       sr_info->sen[i].opp_data[j].err_maxlimit = 
+                                pdata->sr_sdata[i].sr_opp_data[j].err_maxlimit;          
+                        sr_info->sen[i].opp_data[j].margin = 
+                                pdata->sr_sdata[i].sr_opp_data[j].margin; 
+                        sr_info->sen[i].opp_data[j].nominal_volt = 
+                                pdata->sr_sdata[i].sr_opp_data[j].nominal_volt; 
+                        sr_info->sen[i].opp_data[j].frequency = 
+                                pdata->sr_sdata[i].sr_opp_data[j].frequency;  
+                        sr_info->sen[i].opp_data[j].opp_id = j;        
+                }
+
+                if (i == SR_MPU) {
+                        /* hardcoded CPU NR */
+                        curr_freq = cpufreq_get(0); 
+                                
+                        /* update current OPP */
+                        sr_info->sen[i].curr_opp = get_current_opp(sr_info, i, 
+                                        curr_freq*1000);
+                        if (sr_info->sen[i].curr_opp == -EINVAL) {
+                                dev_err(&sr_info->pdev->dev, 
+                                        "%s: cannot determine opp\n",__func__);
+                                ret = -EINVAL;
+                                goto err_free_sr_info;
+                        }
+                } else {
+                        sr_info->sen[i].curr_opp = 
+                                pdata->sr_sdata[i].default_opp;
+                }   
+
+                dev_dbg(&pdev->dev, 
+                        "%s: SR%d, curr_opp=%d, no_of_opps=%d, step_size=%d\n",
+                        __func__, i, sr_info->sen[i].curr_opp, 
+                        sr_info->sen[i].no_of_opps, 
+                        sr_info->uvoltage_step_size);
+
+                ret = sr_set_nvalues(sr_info, i);
+                if (ret == -EINVAL) {
+                        dev_err(&sr_info->pdev->dev,
+                                "%s: Zero NValue read from EFUSE\n", __func__);
+                        goto err_free_sr_info;
+                }
+
+                INIT_DELAYED_WORK(&sr_info->sen[i].work_reenable, 
+                        irq_sr_reenable);
+
+               sr_info->res_name[i] = kzalloc(CLK_NAME_LEN + 1, GFP_KERNEL);
+
+               /* resources */
+               res[i] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+                                       sr_info->sen[i].name);
+               if (!res[i]) {
+                       dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
+                       ret = -ENOENT;
+                       goto err_free_mem;
+               }
+
+               irq = platform_get_irq_byname(pdev, sr_info->sen[i].name);
+               if (irq < 0) {
+                       dev_err(&pdev->dev, "Can't get interrupt resource\n");
+                       ret = irq;
+                       goto err_free_mem;
+               }
+               sr_info->sen[i].irq = irq;
+
+               res[i] = request_mem_region(res[i]->start,
+                               resource_size(res[i]), pdev->name);
+               if (!res[i]) {
+                       dev_err(&pdev->dev, "can't request mem region\n");
+                       ret = -EBUSY;
+                       goto err_free_mem;
+               }
+
+               sr_info->sen[i].base = ioremap(res[i]->start,
+                               resource_size(res[i]));
+               if (!sr_info->sen[i].base) {
+                       dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
+                       ret = -ENOMEM;
+                       goto err_release_mem;
+               }
+
+               strcat(sr_info->res_name[i], sr_info->sen[i].name);
+               strcat(sr_info->res_name[i], "_fck");
+
+               sr_info->sen[i].fck = clk_get(NULL, sr_info->res_name[i]);
+               if (IS_ERR(sr_info->sen[i].fck)) {
+                       dev_err(&pdev->dev, "%s: Could not get sr fck\n",
+                                               __func__);
+                       ret = PTR_ERR(sr_info->sen[i].fck);
+                       goto err_unmap;
+               }
+
+               ret = request_irq(sr_info->sen[i].irq, sr_class2_irq,
+                       IRQF_DISABLED, sr_info->sen[i].name, 
+                        (void *)&sr_info->sen[i]);
+               if (ret) {
+                       dev_err(&pdev->dev, "%s: Could not install SR ISR\n",
+                                               __func__);
+                       goto err_put_clock;
+               }
+
+               sr_info->sen[i].senn_en = pdata->sr_sdata[i].senn_mod;
+               sr_info->sen[i].senp_en = pdata->sr_sdata[i].senp_mod;
+
+                sr_info->sen[i].reg = 
+                        regulator_get(NULL, sr_info->sen[i].reg_name);
+                       if (IS_ERR(sr_info->sen[i].reg)) {
+                        ret = -EINVAL;
+                       goto err_free_irq;
+                }
+
+                       /* Read current regulator value and voltage */
+               sr_info->sen[i].init_volt_mv = 
+                        regulator_get_voltage(sr_info->sen[i].reg);
+
+                dev_dbg(&pdev->dev, "%s: regulator %d, init_volt = %d\n", 
+                        __func__, i, sr_info->sen[i].init_volt_mv);
+       } /* for() */
+
+        /* set_voltage() will be used as the bottom half IRQ handler */
+       INIT_DELAYED_WORK(&sr_info->work, set_voltage);
+
+#ifdef CONFIG_CPU_FREQ
+       ret = am33xx_sr_cpufreq_register(sr_info);
+       if (ret) {
+               dev_err(&pdev->dev, "failed to register cpufreq\n");
+               goto err_reg_put;
+       }
+#endif
+
+       /* debugfs entries */
+       ret = sr_debugfs_entries(sr_info);
+       if (ret)
+               dev_warn(&pdev->dev, "%s: Debugfs entries are not created\n",
+                                               __func__);
+
+       platform_set_drvdata(pdev, sr_info);
+
+       dev_info(&pdev->dev, "%s: Driver initialized\n", __func__);
+
+        /* disabled_by_user used to ensure SR doesn't come on via CPUFREQ
+           scaling if user has disabled SR via debugfs on enable_on_init */
+       if (pdata->enable_on_init)
+               sr_start_vddautocomp(sr_info);
+        else
+                sr_info->disabled_by_user = 1;
+
+       return ret;
+
+#ifdef CONFIG_CPU_FREQ
+       am33xx_sr_cpufreq_deregister(sr_info);
+#endif
+
+err_reg_put:
+        i--; /* back up i by one to walk back through the for loop */
+        regulator_put(sr_info->sen[i].reg);
+err_free_irq:
+       free_irq(sr_info->sen[i].irq, (void *)sr_info);
+err_put_clock:
+       clk_put(sr_info->sen[i].fck);
+err_unmap:
+       iounmap(sr_info->sen[i].base);
+err_release_mem:
+       release_mem_region(res[i]->start, resource_size(res[i]));
+err_free_mem:
+        kfree(sr_info->res_name[i]);
+        /* unwind back through the for loop */
+        if (i != 0) {
+                goto err_reg_put;
+        }
+        
+err_free_sr_info:
+       kfree(sr_info);
+       return ret;
+}
+
+static int __devexit am33xx_sr_remove(struct platform_device *pdev)
+{
+       struct am33xx_sr *sr_info;
+       struct resource *res[MAX_SENSORS];
+       int irq;
+       int i;
+
+       sr_info = dev_get_drvdata(&pdev->dev);
+       if (!sr_info) {
+               dev_err(&pdev->dev, "%s: sr_info missing\n", __func__);
+               return -EINVAL;
+       }
+
+       if (sr_info->autocomp_active)
+               sr_stop_vddautocomp(sr_info);
+
+#ifdef CONFIG_CPU_FREQ
+       am33xx_sr_cpufreq_deregister(sr_info);
+#endif
+
+       for (i = 0; i < sr_info->no_of_sens; i++) {
+                regulator_put(sr_info->sen[i].reg);
+                irq = platform_get_irq_byname(pdev, sr_info->sen[i].name);
+               free_irq(irq, (void *)sr_info);
+               clk_put(sr_info->sen[i].fck);
+               iounmap(sr_info->sen[i].base);
+               res[i] = platform_get_resource_byname(pdev,
+                               IORESOURCE_MEM, sr_info->sen[i].name);
+               release_mem_region(res[i]->start, resource_size(res[i]));
+                kfree(sr_info->res_name[i]);
+       }
+
+       kfree(sr_info);
+
+        dev_info(&pdev->dev, "%s: SR has been removed\n", __func__);
+       return 0;
+}
+
+static struct platform_driver smartreflex_driver = {
+       .driver         = {
+               .name   = "smartreflex",
+               .owner  = THIS_MODULE,
+       },
+       .remove         = am33xx_sr_remove,
+};
+
+static int __init sr_init(void)
+{
+       int ret;
+
+       ret = platform_driver_probe(&smartreflex_driver, am33xx_sr_probe);
+       if (ret) {
+               pr_err("%s: platform driver register failed\n", __func__);
+               return ret;
+       }
+
+       return 0;
+}
+
+static void __exit sr_exit(void)
+{
+       platform_driver_unregister(&smartreflex_driver);
+}
+late_initcall(sr_init);
+module_exit(sr_exit);
+
+MODULE_DESCRIPTION("AM33XX Smartreflex Class2 Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
+MODULE_AUTHOR("Texas Instruments Inc");
index 9fc88fba6702c169052a8e632d5b054345942460..f263f84a5adae7dff4942c5e97c412f9894f1ca4 100644 (file)
@@ -30,6 +30,7 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/export.h>
 #include <linux/wl12xx.h>
 #include <linux/ethtool.h>
 #include <linux/mfd/tps65910.h>
@@ -38,6 +39,7 @@
 #include <linux/input/ti_tscadc.h>
 #include <linux/reboot.h>
 #include <linux/pwm/pwm.h>
+#include <linux/opp.h>
 
 /* LCD controller is similar to DA850 */
 #include <video/da8xx-fb.h>
@@ -50,6 +52,7 @@
 #include <asm/mach/map.h>
 #include <asm/hardware/asp.h>
 
+#include <plat/omap_device.h>
 #include <plat/irqs.h>
 #include <plat/board.h>
 #include <plat/common.h>
 /* Convert GPIO signal to GPIO pin number */
 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
 
-/* TLK PHY IDs */
-#define TLK110_PHY_ID          0x2000A201
-#define TLK110_PHY_MASK                0xfffffff0
-
 /* BBB PHY IDs */
 #define BBB_PHY_ID             0x7c0f1
 #define BBB_PHY_MASK           0xfffffffe
 
-/* TLK110 PHY register offsets */
-#define TLK110_COARSEGAIN_REG  0x00A3
-#define TLK110_LPFHPF_REG      0x00AC
-#define TLK110_SPAREANALOG_REG 0x00B9
-#define TLK110_VRCR_REG                0x00D0
-#define TLK110_SETFFE_REG      0x0107
-#define TLK110_FTSP_REG                0x0154
-#define TLK110_ALFATPIDL_REG   0x002A
-#define TLK110_PSCOEF21_REG    0x0096
-#define TLK110_PSCOEF3_REG     0x0097
-#define TLK110_ALFAFACTOR1_REG 0x002C
-#define TLK110_ALFAFACTOR2_REG 0x0023
-#define TLK110_CFGPS_REG       0x0095
-#define TLK110_FTSPTXGAIN_REG  0x0150
-#define TLK110_SWSCR3_REG      0x000B
-#define TLK110_SCFALLBACK_REG  0x0040
-#define TLK110_PHYRCR_REG      0x001F
-
-/* TLK110 register writes values */
-#define TLK110_COARSEGAIN_VAL  0x0000
-#define TLK110_LPFHPF_VAL      0x8000
-#define TLK110_SPANALOG_VAL    0x0000
-#define TLK110_VRCR_VAL                0x0008
-#define TLK110_SETFFE_VAL      0x0605
-#define TLK110_FTSP_VAL                0x0255
-#define TLK110_ALFATPIDL_VAL   0x7998
-#define TLK110_PSCOEF21_VAL    0x3A20
-#define TLK110_PSCOEF3_VAL     0x003F
-#define TLK110_ALFACTOR1_VAL   0xFF80
-#define TLK110_ALFACTOR2_VAL   0x021C
-#define TLK110_CFGPS_VAL       0x0000
-#define TLK110_FTSPTXGAIN_VAL  0x6A88
-#define TLK110_SWSCR3_VAL      0x0000
-#define TLK110_SCFALLBACK_VAL  0xC11D
-#define TLK110_PHYRCR_VAL      0x4000
-
-#if defined(CONFIG_TLK110_WORKAROUND) || \
-               defined(CONFIG_TLK110_WORKAROUND_MODULE)
-#define am335x_tlk110_phy_init()\
-       do {    \
-               phy_register_fixup_for_uid(TLK110_PHY_ID,\
-                                       TLK110_PHY_MASK,\
-                                       am335x_tlk110_phy_fixup);\
-       } while (0);
-#else
-#define am335x_tlk110_phy_init() do { } while (0);
-#endif
+/* AM335X EVM Phy ID and Debug Registers */
+#define AM335X_EVM_PHY_ID              0x4dd074
+#define AM335X_EVM_PHY_MASK            0xfffffffe
+#define AR8051_PHY_DEBUG_ADDR_REG      0x1d
+#define AR8051_PHY_DEBUG_DATA_REG      0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
+#define AR8051_RGMII_TX_CLK_DLY                BIT(8)
 
 static const struct display_panel disp_panel = {
        WVGA,
@@ -136,10 +95,17 @@ static const struct display_panel disp_panel = {
 #define AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS    100
 #define AM335X_PWM_PERIOD_NANO_SECONDS        (5000 * 10)
 
-#define PWM_DEVICE_ID   "ecap.0"
+static struct platform_pwm_backlight_data am335x_backlight_data0 = {
+       .pwm_id         = "ecap.0",
+       .ch             = -1,
+       .lth_brightness = 21,
+       .max_brightness = AM335X_BACKLIGHT_MAX_BRIGHTNESS,
+       .dft_brightness = AM335X_BACKLIGHT_DEFAULT_BRIGHTNESS,
+       .pwm_period_ns  = AM335X_PWM_PERIOD_NANO_SECONDS,
+};
 
-static struct platform_pwm_backlight_data am335x_backlight_data = {
-       .pwm_id         = PWM_DEVICE_ID,
+static struct platform_pwm_backlight_data am335x_backlight_data2 = {
+       .pwm_id         = "ecap.2",
        .ch             = -1,
        .lth_brightness = 21,
        .max_brightness = AM335X_BACKLIGHT_MAX_BRIGHTNESS,
@@ -170,6 +136,12 @@ struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
        .type                   = "TFC_S9700RTWV35TR_01B",
 };
 
+struct da8xx_lcdc_platform_data  NHD_480272MF_ATXI_pdata = {
+       .manu_name              = "NHD",
+       .controller_data        = &lcd_cfg,
+       .type                   = "NHD-4.3-ATXI#-T-1",
+};
+
 #include "common.h"
 
 #include <linux/lis3lv02d.h>
@@ -200,6 +172,25 @@ static struct snd_platform_data am335x_evm_snd_data1 = {
        .rxnumevt       = 1,
 };
 
+static u8 am335x_evm_sk_iis_serializer_direction1[] = {
+       INACTIVE_MODE,  INACTIVE_MODE,  TX_MODE,        INACTIVE_MODE,
+       INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
+       INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
+       INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
+};
+
+static struct snd_platform_data am335x_evm_sk_snd_data1 = {
+       .tx_dma_offset  = 0x46400000,   /* McASP1 */
+       /*.rx_dma_offset        = 0x46400000,*/
+       .op_mode        = DAVINCI_MCASP_IIS_MODE,
+       .num_serializer = ARRAY_SIZE(am335x_evm_sk_iis_serializer_direction1),
+       .tdm_slots      = 2,
+       .serial_dir     = am335x_evm_sk_iis_serializer_direction1,
+       .asp_chan_q     = EVENTQ_2,
+       .version        = MCASP_VERSION_3,
+       .txnumevt       = 1,
+};
+
 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
        {
                .mmc            = 1,
@@ -220,6 +211,16 @@ static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+       /*
+        * Setting SYSBOOT[5] should set xdma_event_intr0 pin to mode 3 thereby
+        * allowing clkout1 to be available on xdma_event_intr0.
+        * However, on some boards (like EVM-SK), SYSBOOT[5] isn't properly
+        * latched.
+        * To be extra cautious, setup the pin-mux manually.
+        * If any modules/usecase requries it in different mode, then subsequent
+        * module init call will change the mux accordingly.
+        */
+       AM33XX_MUX(XDMA_EVENT_INTR0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT),
        AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
                        AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
        AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
@@ -272,11 +273,10 @@ static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
 *  Header              4       0xAA, 0x55, 0x33, 0xEE
 *
 *  Board Name          8       Name for board in ASCII.
-*                              example "A33515BB" = "AM335X
-                               Low Cost EVM board"
+*                              Example "A33515BB" = "AM335x 15x15 Base Board"
 *
-*  Version             4       Hardware version code for board in
-*                              in ASCII. "1.0A" = rev.01.0A
+*  Version             4       Hardware version code for board in ASCII.
+*                              "1.0A" = rev.01.0A
 *
 *  Serial Number       12      Serial number of the board. This is a 12
 *                              character string which is WWYY4P16nnnn, where
@@ -287,8 +287,7 @@ static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
 *  Configuration option        32      Codes(TBD) to show the configuration
 *                              setup on this board.
 *
-*  Available           32720   Available space for other non-volatile
-*                              data.
+*  Available           32720   Available space for other non-volatile data.
 */
 struct am335x_evm_eeprom_config {
        u32     header;
@@ -340,24 +339,38 @@ static struct am335x_evm_eeprom_config config;
 static struct am335x_eeprom_config1 config1;
 static bool daughter_brd_detected;
 
-#define GP_EVM_REV_IS_1_0              0x1
-#define GP_EVM_REV_IS_1_1A             0x2
-#define GP_EVM_REV_IS_UNKNOWN          0xFF
-static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
-
-#define CPLD_REV_1_0A                  0x1
-#define CPLD_REV_1_1A                  0x2
-#define CPLD_UNKNOWN                   0xFF
-static unsigned int cpld_version = CPLD_UNKNOWN;
-
-unsigned int gigabit_enable = 1;
-
 #define EEPROM_MAC_ADDRESS_OFFSET      60 /* 4+8+4+12+32 */
 #define EEPROM_NO_OF_MAC_ADDR          3
 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
 
 #define AM335X_EEPROM_HEADER           0xEE3355AA
 
+static int am33xx_evmid = -EINVAL;
+
+/*
+* am335x_evm_set_id - set up board evmid
+* @evmid - evm id which needs to be configured
+*
+* This function is called to configure board evm id.
+*/
+void am335x_evm_set_id(unsigned int evmid)
+{
+       am33xx_evmid = evmid;
+       return;
+}
+
+/*
+* am335x_evm_get_id - returns Board Type (EVM/BB/EVM-SK ...)
+*
+* Note:
+*      returns -EINVAL if Board detection hasn't happened yet.
+*/
+int am335x_evm_get_id(void)
+{
+       return am33xx_evmid;
+}
+EXPORT_SYMBOL(am335x_evm_get_id);
+
 /* current profile if exists else PROFILE_0 on error */
 static u32 am335x_get_profile_selection(void)
 {
@@ -587,43 +600,52 @@ static struct pinmux_config mcasp1_pin_mux[] = {
 
 
 /* Module pin mux for mmc0 */
-static struct pinmux_config mmc0_pin_mux[] = {
+static struct pinmux_config mmc0_common_pin_mux[] = {
        {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
        {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
        {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
        {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
        {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
        {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-       {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
-       {"spi0_cs1.mmc0_sdcd",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
        {NULL, 0},
 };
 
-static struct pinmux_config mmc0_no_cd_pin_mux[] = {
-       {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-       {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-       {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-       {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-       {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-       {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
-       {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
+static struct pinmux_config mmc0_wp_only_pin_mux[] = {
+       {"mcasp0_aclkr.gpio3_18", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+       {NULL, 0},
+};
+
+static struct pinmux_config mmc0_cd_only_pin_mux[] = {
+       {"spi0_cs1.gpio0_6",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
        {NULL, 0},
 };
 
 /* Module pin mux for mmc1 */
-static struct pinmux_config mmc1_pin_mux[] = {
-       {"gpmc_ad7.mmc1_dat7",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
-       {"gpmc_ad6.mmc1_dat6",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
-       {"gpmc_ad5.mmc1_dat5",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
-       {"gpmc_ad4.mmc1_dat4",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+static struct pinmux_config mmc1_common_pin_mux[] = {
        {"gpmc_ad3.mmc1_dat3",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
        {"gpmc_ad2.mmc1_dat2",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
        {"gpmc_ad1.mmc1_dat1",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
        {"gpmc_ad0.mmc1_dat0",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
        {"gpmc_csn1.mmc1_clk",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
        {"gpmc_csn2.mmc1_cmd",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
+       {NULL, 0},
+};
+
+static struct pinmux_config mmc1_dat4_7_pin_mux[] = {
+       {"gpmc_ad7.mmc1_dat7",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+       {"gpmc_ad6.mmc1_dat6",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+       {"gpmc_ad5.mmc1_dat5",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+       {"gpmc_ad4.mmc1_dat4",  OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLUP},
+       {NULL, 0},
+};
+
+static struct pinmux_config mmc1_wp_only_pin_mux[] = {
        {"gpmc_csn0.gpio1_29",  OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
-       {"gpmc_advn_ale.mmc1_sdcd", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
+       {NULL, 0},
+};
+
+static struct pinmux_config mmc1_cd_only_pin_mux[] = {
+       {"gpmc_advn_ale.gpio2_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
        {NULL, 0},
 };
 
@@ -656,6 +678,28 @@ static struct pinmux_config uart2_pin_mux[] = {
        {NULL, 0},
 };
 
+/* pinmux for gpio based key */
+static struct pinmux_config gpio_keys_pin_mux[] = {
+       {"gpmc_wait0.gpio0_30", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+       {"gpmc_oen_ren.gpio2_3", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+       {"gpmc_advn_ale.gpio2_2", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+       {"gpmc_ben0_cle.gpio2_5", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+       {NULL, 0},
+};
+
+/* pinmux for led device */
+static struct pinmux_config gpio_led_mux[] = {
+       {"gpmc_ad4.gpio1_4", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+       {"gpmc_ad5.gpio1_5", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+       {"gpmc_ad6.gpio1_6", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+       {"gpmc_ad7.gpio1_7", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+       {NULL, 0},
+};
+
+static struct pinmux_config gpio_ddr_vtt_enb_pin_mux[] = {
+       {"ecap0_in_pwm0_out.gpio0_7", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+       {NULL, 0},
+};
 
 /*
 * @pin_mux - single module pin-mux structure which defines pin-mux
@@ -799,6 +843,8 @@ static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
 {
        int i;
 
+       am335x_evm_set_id(evm_id);
+
        /*
        * Only General Purpose & Industrial Auto Motro Control
        * EVM has profiles. So check if this evm has profile.
@@ -856,14 +902,21 @@ static struct pinmux_config ecap0_pin_mux[] = {
        {NULL, 0},
 };
 
-static int backlight_enable;
+/* Module pin mux for eCAP */
+static struct pinmux_config ecap2_pin_mux[] = {
+       {"mcasp0_ahclkr.ecap2_in_pwm2_out", AM33XX_PIN_OUTPUT},
+       {NULL, 0},
+};
 
 #define AM335XEVM_WLAN_PMENA_GPIO      GPIO_TO_PIN(1, 30)
 #define AM335XEVM_WLAN_IRQ_GPIO                GPIO_TO_PIN(3, 17)
+#define AM335XEVM_SK_WLAN_IRQ_GPIO      GPIO_TO_PIN(0, 31)
 
 struct wl12xx_platform_data am335xevm_wlan_data = {
        .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
        .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
+       .bt_enable_gpio = GPIO_TO_PIN(3, 21),
+       .wlan_enable_gpio = GPIO_TO_PIN(1, 16),
 };
 
 /* Module pin mux for wlan and bluetooth */
@@ -885,19 +938,21 @@ static struct pinmux_config uart1_wl12xx_pin_mux[] = {
        {NULL, 0},
 };
 
-static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
+static struct pinmux_config wl12xx_pin_mux[] = {
        {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
        {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-       {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+       {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT_PULLUP},
        {NULL, 0},
  };
 
-static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
-       {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
-       {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
-       {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
+static struct pinmux_config wl12xx_pin_mux_sk[] = {
+       {"gpmc_wpn.gpio0_31", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
+       {"gpmc_csn0.gpio1_29", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT_PULLUP},
+       {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
        {NULL, 0},
- };
+};
+
+static bool backlight_enable;
 
 static void enable_ecap0(int evm_id, int profile)
 {
@@ -905,13 +960,19 @@ static void enable_ecap0(int evm_id, int profile)
        setup_pin_mux(ecap0_pin_mux);
 }
 
+static void enable_ecap2(int evm_id, int profile)
+{
+       backlight_enable = true;
+       setup_pin_mux(ecap2_pin_mux);
+}
+
 /* Setup pwm-backlight */
 static struct platform_device am335x_backlight = {
        .name           = "pwm-backlight",
        .id             = -1,
-       .dev            = {
-               .platform_data  = &am335x_backlight_data,
-       }
+       .dev            = {
+               .platform_data = &am335x_backlight_data0,
+       },
 };
 
 static struct pwmss_platform_data  pwm_pdata[3] = {
@@ -926,17 +987,39 @@ static struct pwmss_platform_data  pwm_pdata[3] = {
        },
 };
 
-static int __init ecap0_init(void)
+static int __init backlight_init(void)
 {
        int status = 0;
 
        if (backlight_enable) {
-               am33xx_register_ecap(0, &pwm_pdata[0]);
+               int ecap_index = 0;
+
+               switch (am335x_evm_get_id()) {
+               case GEN_PURP_EVM:
+                       ecap_index = 0;
+                       break;
+               case EVM_SK:
+                       /*
+                        * Invert polarity of PWM wave from ECAP to handle
+                        * backlight intensity to pwm brightness
+                        */
+                       ecap_index = 2;
+                       pwm_pdata[ecap_index].chan_attrib[0].inverse_pol = true;
+                       am335x_backlight.dev.platform_data =
+                               &am335x_backlight_data2;
+                       break;
+               default:
+                       pr_err("%s: Error on attempting to enable backlight,"
+                               " not supported\n", __func__);
+                       return -EINVAL;
+               }
+
+               am33xx_register_ecap(ecap_index, &pwm_pdata[ecap_index]);
                platform_device_register(&am335x_backlight);
        }
        return status;
 }
-late_initcall(ecap0_init);
+late_initcall(backlight_init);
 
 static int __init conf_disp_pll(int rate)
 {
@@ -957,7 +1040,7 @@ out:
 
 static void lcdc_init(int evm_id, int profile)
 {
-
+       struct da8xx_lcdc_platform_data *lcdc_pdata;
        setup_pin_mux(lcdc_pin_mux);
 
        if (conf_disp_pll(300000000)) {
@@ -965,9 +1048,21 @@ static void lcdc_init(int evm_id, int profile)
                                "register LCDC\n");
                return;
        }
+       switch (evm_id) {
+       case GEN_PURP_EVM:
+               lcdc_pdata = &TFC_S9700RTWV35TR_01B_pdata;
+               break;
+       case EVM_SK:
+               lcdc_pdata = &NHD_480272MF_ATXI_pdata;
+               break;
+       default:
+               pr_err("LCDC not supported on this evm (%d)\n",evm_id);
+               return;
+       }
 
-       if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
+       if (am33xx_register_lcdc(lcdc_pdata))
                pr_info("Failed to register LCDC device\n");
+
        return;
 }
 
@@ -975,15 +1070,7 @@ static void tsc_init(int evm_id, int profile)
 {
        int err;
 
-       if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
-               am335x_touchscreen_data.analog_input = 1;
-               pr_info("TSC connected to beta GP EVM\n");
-       } else {
-               am335x_touchscreen_data.analog_input = 0;
-               pr_info("TSC connected to alpha GP EVM\n");
-       }
        setup_pin_mux(tsc_pin_mux);
-
        err = am33xx_register_tsc(&am335x_touchscreen_data);
        if (err)
                pr_err("failed to register touchscreen device\n");
@@ -1039,6 +1126,17 @@ static void uart2_init(int evm_id, int profile)
        return;
 }
 
+/*
+ * gpio0_7 was driven HIGH in u-boot before DDR configuration
+ *
+ * setup gpio0_7 for EVM-SK 1.2
+ */
+static void gpio_ddr_vtt_enb_init(int evm_id, int profile)
+{
+       setup_pin_mux(gpio_ddr_vtt_enb_pin_mux);
+       return;
+}
+
 /* setup haptics */
 #define HAPTICS_MAX_FREQ 250
 static void haptics_init(int evm_id, int profile)
@@ -1288,6 +1386,20 @@ static struct regulator_consumer_supply tps65217_ldo4_consumers[] = {
        },
 };
 
+/*
+ * FIXME: Some BeagleBones reuire a ramp_delay to settle down the set
+ * voltage from 0.95v to 1.25v. By default a minimum of 70msec is set
+ * based on experimentation. This will be removed/modified to exact
+ * value, once the root cause is known.
+ *
+ * The reason for extended ramp time requirement on BeagleBone is not
+ * known and the delay varies from board - board, if the board hangs
+ * with this 70msec delay then try to increase the value.
+ */
+static struct tps65217_rdelay dcdc2_ramp_delay = {
+       .ramp_delay = 70000,
+};
+
 static struct regulator_init_data tps65217_regulator_data[] = {
        /* dcdc1 */
        {
@@ -1313,6 +1425,8 @@ static struct regulator_init_data tps65217_regulator_data[] = {
                },
                .num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc2_consumers),
                .consumer_supplies = tps65217_dcdc2_consumers,
+               .driver_data = &dcdc2_ramp_delay,
+               .ignore_check_consumers = 1,
        },
 
        /* dcdc3 */
@@ -1327,6 +1441,7 @@ static struct regulator_init_data tps65217_regulator_data[] = {
                },
                .num_consumer_supplies = ARRAY_SIZE(tps65217_dcdc3_consumers),
                .consumer_supplies = tps65217_dcdc3_consumers,
+               .ignore_check_consumers = 1,
        },
 
        /* ldo1 */
@@ -1410,14 +1525,49 @@ static struct lis3lv02d_platform_data lis331dlh_pdata = {
        .st_max_limits[2] = 750,
 };
 
-static struct i2c_board_info am335x_i2c_boardinfo1[] = {
-       {
-               I2C_BOARD_INFO("tlv320aic3x", 0x1b),
-       },
+static struct i2c_board_info lis331dlh_i2c_boardinfo[] = {
        {
                I2C_BOARD_INFO("lis331dlh", 0x18),
                .platform_data = &lis331dlh_pdata,
        },
+};
+
+static void lis331dlh_init(int evm_id, int profile)
+{
+       struct i2c_adapter *adapter;
+       struct i2c_client *client;
+       unsigned int i2c_instance;
+
+       switch (evm_id) {
+       case GEN_PURP_EVM:
+               i2c_instance = 2;
+               break;
+       case EVM_SK:
+               i2c_instance = 1;
+               break;
+       default:
+               pr_err("lis331dlh is not supported on this evm (%d)\n", evm_id);
+               return;
+       }
+
+       /* I2C adapter request */
+       adapter = i2c_get_adapter(i2c_instance);
+       if (!adapter) {
+               pr_err("failed to get adapter i2c%u\n", i2c_instance);
+               return;
+       }
+
+       client = i2c_new_device(adapter, lis331dlh_i2c_boardinfo);
+       if (!client)
+               pr_err("failed to register lis331dlh to i2c%u\n", i2c_instance);
+
+       i2c_put_adapter(adapter);
+}
+
+static struct i2c_board_info am335x_i2c1_boardinfo[] = {
+       {
+               I2C_BOARD_INFO("tlv320aic3x", 0x1b),
+       },
        {
                I2C_BOARD_INFO("tsl2550", 0x39),
        },
@@ -1429,20 +1579,19 @@ static struct i2c_board_info am335x_i2c_boardinfo1[] = {
 static void i2c1_init(int evm_id, int profile)
 {
        setup_pin_mux(i2c1_pin_mux);
-       omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
-                       ARRAY_SIZE(am335x_i2c_boardinfo1));
+       omap_register_i2c_bus(2, 100, am335x_i2c1_boardinfo,
+                       ARRAY_SIZE(am335x_i2c1_boardinfo));
        return;
 }
 
-
-static struct i2c_board_info am335x_i2c_boardinfo2[] = {
+static struct i2c_board_info am335x_i2c2_boardinfo[] = {
 };
 
 static void i2c2_init(int evm_id, int profile)
 {
        setup_pin_mux(i2c2_pin_mux);
-       omap_register_i2c_bus(3, 100, am335x_i2c_boardinfo2,
-                       ARRAY_SIZE(am335x_i2c_boardinfo2));
+       omap_register_i2c_bus(3, 100, am335x_i2c2_boardinfo,
+                       ARRAY_SIZE(am335x_i2c2_boardinfo));
        return;
 }
 
@@ -1451,13 +1600,23 @@ static void mcasp1_init(int evm_id, int profile)
 {
        /* Configure McASP */
        setup_pin_mux(mcasp1_pin_mux);
-       am335x_register_mcasp(&am335x_evm_snd_data1, 1);
+       switch (evm_id) {
+       case EVM_SK:
+               am335x_register_mcasp(&am335x_evm_sk_snd_data1, 1);
+               break;
+       default:
+               am335x_register_mcasp(&am335x_evm_snd_data1, 1);
+       }
+
        return;
 }
 
 static void mmc1_init(int evm_id, int profile)
 {
-       setup_pin_mux(mmc1_pin_mux);
+       setup_pin_mux(mmc1_common_pin_mux);
+       setup_pin_mux(mmc1_dat4_7_pin_mux);
+       setup_pin_mux(mmc1_wp_only_pin_mux);
+       setup_pin_mux(mmc1_cd_only_pin_mux);
 
        am335x_mmc[1].mmc = 2;
        am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
@@ -1469,14 +1628,26 @@ static void mmc1_init(int evm_id, int profile)
        return;
 }
 
+static void mmc1_wl12xx_init(int evm_id, int profile)
+{
+       setup_pin_mux(mmc1_common_pin_mux);
+       am335x_mmc[1].mmc = 2;
+       am335x_mmc[1].name = "wl1271";
+       am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD;
+       am335x_mmc[1].nonremovable = true;
+       am335x_mmc[1].pm_caps = MMC_PM_KEEP_POWER;
+       am335x_mmc[1].gpio_cd = -EINVAL;
+       am335x_mmc[1].gpio_wp = -EINVAL;
+       am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
+}
+
 static void mmc2_wl12xx_init(int evm_id, int profile)
 {
        setup_pin_mux(mmc2_wl12xx_pin_mux);
 
        am335x_mmc[1].mmc = 3;
        am335x_mmc[1].name = "wl1271";
-       am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
-                               | MMC_PM_KEEP_POWER;
+       am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD;
        am335x_mmc[1].nonremovable = true;
        am335x_mmc[1].gpio_cd = -EINVAL;
        am335x_mmc[1].gpio_wp = -EINVAL;
@@ -1502,14 +1673,36 @@ static void wl12xx_bluetooth_enable(void)
        gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
 }
 
+#define AM33XX_CTRL_REGADDR(reg)                                       \
+               AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
+
+/* wlan enable pin */
+#define AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET                0x087C
 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
 {
+       int pad_mux_value;
+
        if (on) {
-               gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
+               gpio_direction_output(am335xevm_wlan_data.wlan_enable_gpio, 1);
+
+               /* Enable pullup on the WLAN enable pin for keeping wlan active during suspend
+                  in wowlan mode */
+               if ( am335x_evm_get_id() == EVM_SK ) {
+                       pad_mux_value = readl(AM33XX_CTRL_REGADDR(AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET));
+                       pad_mux_value &= (~AM33XX_PULL_DISA);
+                       writel(pad_mux_value, AM33XX_CTRL_REGADDR(AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET));
+               }
+
                mdelay(70);
+       } else {
+               gpio_direction_output(am335xevm_wlan_data.wlan_enable_gpio, 0);
+               /* Disable pullup on the WLAN enable when WLAN is off */
+               if ( am335x_evm_get_id() == EVM_SK ) {
+                       pad_mux_value = readl(AM33XX_CTRL_REGADDR(AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET));
+                       pad_mux_value |= AM33XX_PULL_DISA;
+                       writel(pad_mux_value, AM33XX_CTRL_REGADDR(AM33XX_CONTROL_PADCONF_GPMC_CSN0_OFFSET));
+               }
        }
-       else
-               gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
 
        return 0;
 }
@@ -1520,16 +1713,16 @@ static void wl12xx_init(int evm_id, int profile)
        struct omap_mmc_platform_data *pdata;
        int ret;
 
-       /* Register WLAN and BT enable pins based on the evm board revision */
-       if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
-               am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
+       if (evm_id == EVM_SK) {
+               am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 29);
                am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
+               am335xevm_wlan_data.irq =
+                               OMAP_GPIO_IRQ(AM335XEVM_SK_WLAN_IRQ_GPIO);
+               setup_pin_mux(wl12xx_pin_mux_sk);
+       } else {
+               setup_pin_mux(wl12xx_pin_mux);
        }
-       else {
-               am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
-               am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
-       }
-
+       am335xevm_wlan_data.platform_quirks = WL12XX_PLATFORM_QUIRK_EDGE_IRQ;
        wl12xx_bluetooth_enable();
 
        if (wl12xx_set_platform_data(&am335xevm_wlan_data))
@@ -1554,10 +1747,6 @@ static void wl12xx_init(int evm_id, int profile)
                goto out;
        }
 
-       if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
-               setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
-       else
-               setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
 
        pdata->slots[0].set_power = wl12xx_set_power;
 out:
@@ -1588,7 +1777,19 @@ static void d_can_init(int evm_id, int profile)
 
 static void mmc0_init(int evm_id, int profile)
 {
-       setup_pin_mux(mmc0_pin_mux);
+       switch (evm_id) {
+       case BEAGLE_BONE_A3:
+       case BEAGLE_BONE_OLD:
+       case EVM_SK:
+               setup_pin_mux(mmc0_common_pin_mux);
+               setup_pin_mux(mmc0_cd_only_pin_mux);
+               break;
+       default:
+               setup_pin_mux(mmc0_common_pin_mux);
+               setup_pin_mux(mmc0_cd_only_pin_mux);
+               setup_pin_mux(mmc0_wp_only_pin_mux);
+               break;
+       }
 
        omap2_hsmmc_init(am335x_mmc);
        return;
@@ -1605,6 +1806,14 @@ static void tps65217_init(int evm_id, int profile)
 {
        struct i2c_adapter *adapter;
        struct i2c_client *client;
+       struct device *mpu_dev;
+       struct tps65217 *tps;
+       unsigned int val;
+       int ret;
+
+       mpu_dev = omap_device_get_by_hwmod_name("mpu");
+       if (!mpu_dev)
+               pr_warning("%s: unable to get the mpu device\n", __func__);
 
        /* I2C1 adapter request */
        adapter = i2c_get_adapter(1);
@@ -1618,16 +1827,130 @@ static void tps65217_init(int evm_id, int profile)
                pr_err("failed to register tps65217 to i2c1\n");
 
        i2c_put_adapter(adapter);
+
+       tps = (struct tps65217 *)i2c_get_clientdata(client);
+
+       ret = tps65217_reg_read(tps, TPS65217_REG_STATUS, &val);
+       if (ret) {
+               pr_err("failed to read tps65217 status reg\n");
+               return;
+       }
+
+       if (!(val & TPS65217_STATUS_ACPWR)) {
+               /* If powered by USB then disable OPP120 and OPPTURBO */
+               pr_info("Maximum current provided by the USB port is 500mA"
+                       " which is not sufficient\nwhen operating @OPP120 and"
+                       " OPPTURBO. The current requirement for some\nuse-cases"
+                       " using OPP100 might also exceed the maximum current"
+                       " that the\nUSB port can provide. Unless you are fully"
+                       " confident that the current\nrequirements for OPP100"
+                       " use-case don't exceed the USB limits, switching\nto"
+                       " AC power is recommended.\n");
+               opp_disable(mpu_dev, 600000000);
+               opp_disable(mpu_dev, 720000000);
+       }
 }
 
 static void mmc0_no_cd_init(int evm_id, int profile)
 {
-       setup_pin_mux(mmc0_no_cd_pin_mux);
+       setup_pin_mux(mmc0_common_pin_mux);
+       setup_pin_mux(mmc0_wp_only_pin_mux);
 
        omap2_hsmmc_init(am335x_mmc);
        return;
 }
 
+/* Configure GPIOs for GPIO Keys */
+static struct gpio_keys_button am335x_evm_gpio_buttons[] = {
+       {
+               .code                   = BTN_0,
+               .gpio                   = GPIO_TO_PIN(2, 3),
+               .desc                   = "SW1",
+       },
+       {
+               .code                   = BTN_1,
+               .gpio                   = GPIO_TO_PIN(2, 2),
+               .desc                   = "SW2",
+       },
+       {
+               .code                   = BTN_2,
+               .gpio                   = GPIO_TO_PIN(0, 30),
+               .desc                   = "SW3",
+               .wakeup                 = 1,
+       },
+       {
+               .code                   = BTN_3,
+               .gpio                   = GPIO_TO_PIN(2, 5),
+               .desc                   = "SW4",
+       },
+};
+
+static struct gpio_keys_platform_data am335x_evm_gpio_key_info = {
+       .buttons        = am335x_evm_gpio_buttons,
+       .nbuttons       = ARRAY_SIZE(am335x_evm_gpio_buttons),
+};
+
+static struct platform_device am335x_evm_gpio_keys = {
+       .name   = "gpio-keys",
+       .id     = -1,
+       .dev    = {
+               .platform_data  = &am335x_evm_gpio_key_info,
+       },
+};
+
+static void gpio_keys_init(int evm_id, int profile)
+{
+       int err;
+
+       setup_pin_mux(gpio_keys_pin_mux);
+       err = platform_device_register(&am335x_evm_gpio_keys);
+       if (err)
+               pr_err("failed to register gpio key device\n");
+}
+
+static struct gpio_led gpio_leds[] = {
+       {
+               .name                   = "am335x:EVM_SK:usr0",
+               .gpio                   = GPIO_TO_PIN(1, 4),    /* D1 */
+       },
+       {
+               .name                   = "am335x:EVM_SK:usr1",
+               .gpio                   = GPIO_TO_PIN(1, 5),    /* D2 */
+       },
+       {
+               .name                   = "am335x:EVM_SK:mmc0",
+               .gpio                   = GPIO_TO_PIN(1, 7),    /* D3 */
+               .default_trigger        = "mmc0",
+       },
+       {
+               .name                   = "am335x:EVM_SK:heartbeat",
+               .gpio                   = GPIO_TO_PIN(1, 6),    /* D4 */
+               .default_trigger        = "heartbeat",
+       },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+       .leds           = gpio_leds,
+       .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+       .name   = "leds-gpio",
+       .id     = -1,
+       .dev    = {
+               .platform_data  = &gpio_led_info,
+       },
+};
+
+static void gpio_led_init(int evm_id, int profile)
+{
+       int err;
+
+       setup_pin_mux(gpio_led_mux);
+       err = platform_device_register(&leds_gpio);
+       if (err)
+               pr_err("failed to register gpio led device\n");
+}
 
 /* setup spi0 */
 static void spi0_init(int evm_id, int profile)
@@ -1656,80 +1979,12 @@ static int beaglebone_phy_fixup(struct phy_device *phydev)
        return 0;
 }
 
-#if defined(CONFIG_TLK110_WORKAROUND) || \
-                       defined(CONFIG_TLK110_WORKAROUND_MODULE)
-static int am335x_tlk110_phy_fixup(struct phy_device *phydev)
-{
-       unsigned int val;
-
-       /* This is done as a workaround to support TLK110 rev1.0 phy */
-       val = phy_read(phydev, TLK110_COARSEGAIN_REG);
-       phy_write(phydev, TLK110_COARSEGAIN_REG, (val | TLK110_COARSEGAIN_VAL));
-
-       val = phy_read(phydev, TLK110_LPFHPF_REG);
-       phy_write(phydev, TLK110_LPFHPF_REG, (val | TLK110_LPFHPF_VAL));
-
-       val = phy_read(phydev, TLK110_SPAREANALOG_REG);
-       phy_write(phydev, TLK110_SPAREANALOG_REG, (val | TLK110_SPANALOG_VAL));
-
-       val = phy_read(phydev, TLK110_VRCR_REG);
-       phy_write(phydev, TLK110_VRCR_REG, (val | TLK110_VRCR_VAL));
-
-       val = phy_read(phydev, TLK110_SETFFE_REG);
-       phy_write(phydev, TLK110_SETFFE_REG, (val | TLK110_SETFFE_VAL));
-
-       val = phy_read(phydev, TLK110_FTSP_REG);
-       phy_write(phydev, TLK110_FTSP_REG, (val | TLK110_FTSP_VAL));
-
-       val = phy_read(phydev, TLK110_ALFATPIDL_REG);
-       phy_write(phydev, TLK110_ALFATPIDL_REG, (val | TLK110_ALFATPIDL_VAL));
-
-       val = phy_read(phydev, TLK110_PSCOEF21_REG);
-       phy_write(phydev, TLK110_PSCOEF21_REG, (val | TLK110_PSCOEF21_VAL));
-
-       val = phy_read(phydev, TLK110_PSCOEF3_REG);
-       phy_write(phydev, TLK110_PSCOEF3_REG, (val | TLK110_PSCOEF3_VAL));
-
-       val = phy_read(phydev, TLK110_ALFAFACTOR1_REG);
-       phy_write(phydev, TLK110_ALFAFACTOR1_REG, (val | TLK110_ALFACTOR1_VAL));
-
-       val = phy_read(phydev, TLK110_ALFAFACTOR2_REG);
-       phy_write(phydev, TLK110_ALFAFACTOR2_REG, (val | TLK110_ALFACTOR2_VAL));
-
-       val = phy_read(phydev, TLK110_CFGPS_REG);
-       phy_write(phydev, TLK110_CFGPS_REG, (val | TLK110_CFGPS_VAL));
-
-       val = phy_read(phydev, TLK110_FTSPTXGAIN_REG);
-       phy_write(phydev, TLK110_FTSPTXGAIN_REG, (val | TLK110_FTSPTXGAIN_VAL));
-
-       val = phy_read(phydev, TLK110_SWSCR3_REG);
-       phy_write(phydev, TLK110_SWSCR3_REG, (val | TLK110_SWSCR3_VAL));
-
-       val = phy_read(phydev, TLK110_SCFALLBACK_REG);
-       phy_write(phydev, TLK110_SCFALLBACK_REG, (val | TLK110_SCFALLBACK_VAL));
-
-       val = phy_read(phydev, TLK110_PHYRCR_REG);
-       phy_write(phydev, TLK110_PHYRCR_REG, (val | TLK110_PHYRCR_VAL));
-
-       return 0;
-}
-#endif
-
 static void profibus_init(int evm_id, int profile)
 {
        setup_pin_mux(profibus_pin_mux);
        return;
 }
 
-/* Low-Cost EVM */
-static struct evm_dev_cfg low_cost_evm_dev_cfg[] = {
-       {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
-       {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
-       {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
-       {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_NONE},
-       {NULL, 0, 0},
-};
-
 /* General Purpose EVM */
 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
        {enable_ecap0,  DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_1 |
@@ -1746,6 +2001,7 @@ static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
        {evm_nand_init, DEV_ON_DGHTR_BRD,
                (PROFILE_ALL & ~PROFILE_2 & ~PROFILE_3)},
        {i2c1_init,     DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
+       {lis331dlh_init, DEV_ON_DGHTR_BRD, (PROFILE_ALL & ~PROFILE_2)},
        {mcasp1_init,   DEV_ON_DGHTR_BRD, (PROFILE_0 | PROFILE_3 | PROFILE_7)},
        {mmc1_init,     DEV_ON_DGHTR_BRD, PROFILE_2},
        {mmc2_wl12xx_init,      DEV_ON_BASEBOARD, (PROFILE_0 | PROFILE_3 |
@@ -1778,22 +2034,6 @@ static struct evm_dev_cfg ind_auto_mtrl_evm_dev_cfg[] = {
        {NULL, 0, 0},
 };
 
-/* IP-Phone EVM */
-static struct evm_dev_cfg ip_phn_evm_dev_cfg[] = {
-       {enable_ecap0,  DEV_ON_DGHTR_BRD, PROFILE_NONE},
-       {lcdc_init,     DEV_ON_DGHTR_BRD, PROFILE_NONE},
-       {tsc_init,      DEV_ON_DGHTR_BRD, PROFILE_NONE},
-       {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_NONE},
-       {rgmii2_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
-       {usb0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
-       {usb1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
-       {evm_nand_init, DEV_ON_DGHTR_BRD, PROFILE_NONE},
-       {i2c1_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
-       {mcasp1_init,   DEV_ON_DGHTR_BRD, PROFILE_NONE},
-       {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_NONE},
-       {NULL, 0, 0},
-};
-
 /* Beaglebone < Rev A3 */
 static struct evm_dev_cfg beaglebone_old_dev_cfg[] = {
        {rmii1_init,    DEV_ON_BASEBOARD, PROFILE_NONE},
@@ -1815,11 +2055,32 @@ static struct evm_dev_cfg beaglebone_dev_cfg[] = {
        {NULL, 0, 0},
 };
 
-static void setup_low_cost_evm(void)
+/* EVM - Starter Kit */
+static struct evm_dev_cfg evm_sk_dev_cfg[] = {
+       {mmc1_wl12xx_init,      DEV_ON_BASEBOARD, PROFILE_ALL},
+       {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
+       {rgmii1_init,   DEV_ON_BASEBOARD, PROFILE_ALL},
+       {rgmii2_init,   DEV_ON_BASEBOARD, PROFILE_ALL},
+       {lcdc_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
+       {enable_ecap2,     DEV_ON_BASEBOARD, PROFILE_ALL},
+       {tsc_init,      DEV_ON_BASEBOARD, PROFILE_ALL},
+       {gpio_keys_init,  DEV_ON_BASEBOARD, PROFILE_ALL},
+       {gpio_led_init,  DEV_ON_BASEBOARD, PROFILE_ALL},
+       {lis331dlh_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+       {mcasp1_init,   DEV_ON_BASEBOARD, PROFILE_ALL},
+       {uart1_wl12xx_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+       {wl12xx_init,       DEV_ON_BASEBOARD, PROFILE_ALL},
+       {gpio_ddr_vtt_enb_init, DEV_ON_BASEBOARD, PROFILE_ALL},
+       {NULL, 0, 0},
+};
+
+static int am33xx_evm_tx_clk_dly_phy_fixup(struct phy_device *phydev)
 {
-       pr_info("The board is a AM335x Low Cost EVM.\n");
+       phy_write(phydev, AR8051_PHY_DEBUG_ADDR_REG,
+                 AR8051_DEBUG_RGMII_CLK_DLY_REG);
+       phy_write(phydev, AR8051_PHY_DEBUG_DATA_REG, AR8051_RGMII_TX_CLK_DLY);
 
-       _configure_device(LOW_COST_EVM, low_cost_evm_dev_cfg, PROFILE_NONE);
+       return 0;
 }
 
 static void setup_general_purpose_evm(void)
@@ -1827,21 +2088,12 @@ static void setup_general_purpose_evm(void)
        u32 prof_sel = am335x_get_profile_selection();
        pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
 
-       if (!strncmp("1.1A", config.version, 4)) {
-               gp_evm_revision = GP_EVM_REV_IS_1_1A;
-       } else if (!strncmp("1.0", config.version, 3)) {
-               gp_evm_revision = GP_EVM_REV_IS_1_0;
-       } else {
-               pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
-               gp_evm_revision = GP_EVM_REV_IS_1_1A;
-       }
-
-       if (gp_evm_revision == GP_EVM_REV_IS_1_0)
-               gigabit_enable = 0;
-       else if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
-               gigabit_enable = 1;
-
        _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
+
+       am33xx_cpsw_init(AM33XX_CPSW_MODE_RGMII, NULL, NULL);
+       /* Atheros Tx Clk delay Phy fixup */
+       phy_register_fixup_for_uid(AM335X_EVM_PHY_ID, AM335X_EVM_PHY_MASK,
+                                  am33xx_evm_tx_clk_dly_phy_fixup);
 }
 
 static void setup_ind_auto_motor_ctrl_evm(void)
@@ -1861,20 +2113,7 @@ static void setup_ind_auto_motor_ctrl_evm(void)
        _configure_device(IND_AUT_MTR_EVM, ind_auto_mtrl_evm_dev_cfg,
                PROFILE_0);
 
-       /* Fillup global evmid */
-       am33xx_evmid_fillup(IND_AUT_MTR_EVM);
-
-       /* Initialize TLK110 PHY registers for phy version 1.0 */
-       am335x_tlk110_phy_init();
-
-
-}
-
-static void setup_ip_phone_evm(void)
-{
-       pr_info("The board is an IP phone EVM\n");
-
-       _configure_device(IP_PHN_EVM, ip_phn_evm_dev_cfg, PROFILE_NONE);
+       am33xx_cpsw_init(AM33XX_CPSW_MODE_MII, "0:1e", "0:00");
 }
 
 /* BeagleBone < Rev A3 */
@@ -1885,13 +2124,13 @@ static void setup_beaglebone_old(void)
        /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
        am335x_mmc[0].gpio_wp = -EINVAL;
 
-       _configure_device(LOW_COST_EVM, beaglebone_old_dev_cfg, PROFILE_NONE);
+       _configure_device(BEAGLE_BONE_OLD, beaglebone_old_dev_cfg,
+                                                               PROFILE_NONE);
 
        phy_register_fixup_for_uid(BBB_PHY_ID, BBB_PHY_MASK,
                                        beaglebone_phy_fixup);
 
-       /* Fill up global evmid */
-       am33xx_evmid_fillup(BEAGLE_BONE_OLD);
+       am33xx_cpsw_init(AM33XX_CPSW_MODE_RMII, NULL, NULL);
 }
 
 /* BeagleBone after Rev A3 */
@@ -1902,24 +2141,37 @@ static void setup_beaglebone(void)
        /* Beagle Bone has Micro-SD slot which doesn't have Write Protect pin */
        am335x_mmc[0].gpio_wp = -EINVAL;
 
-       _configure_device(LOW_COST_EVM, beaglebone_dev_cfg, PROFILE_NONE);
+       _configure_device(BEAGLE_BONE_A3, beaglebone_dev_cfg, PROFILE_NONE);
 
        /* TPS65217 regulator has full constraints */
        regulator_has_full_constraints();
 
-       /* Fill up global evmid */
-       am33xx_evmid_fillup(BEAGLE_BONE_A3);
+       am33xx_cpsw_init(AM33XX_CPSW_MODE_MII, NULL, NULL);
 }
 
+/* EVM - Starter Kit */
+static void setup_starterkit(void)
+{
+       pr_info("The board is a AM335x Starter Kit.\n");
+
+       /* Starter Kit has Micro-SD slot which doesn't have Write Protect pin */
+       am335x_mmc[0].gpio_wp = -EINVAL;
+
+       _configure_device(EVM_SK, evm_sk_dev_cfg, PROFILE_NONE);
+
+       am33xx_cpsw_init(AM33XX_CPSW_MODE_RGMII, NULL, NULL);
+       /* Atheros Tx Clk delay Phy fixup */
+       phy_register_fixup_for_uid(AM335X_EVM_PHY_ID, AM335X_EVM_PHY_MASK,
+                                  am33xx_evm_tx_clk_dly_phy_fixup);
+}
 
 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
 {
        int ret;
 
        /*
-        * Read from the EEPROM to see the presence
-        * of daughter board. If present, get daughter board
-        * specific data.
+        * Read from the EEPROM to see the presence of daughter board.
+        * If present, print the cpld version.
         */
 
        ret = m->read(m, (char *)&config1, 0, sizeof(config1));
@@ -1933,14 +2185,10 @@ static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
                return;
        }
 
-       if (!strncmp("CPLD1.0A", config1.cpld_ver, 8))
-               cpld_version = CPLD_REV_1_0A;
-       else if (!strncmp("CPLD1.1A", config1.cpld_ver, 8))
-               cpld_version = CPLD_REV_1_1A;
-       else {
-               pr_err("Unknown CPLD version found, falling back to 1.0A\n");
-               cpld_version = CPLD_REV_1_0A;
-       }
+       if (!strncmp("CPLD", config1.cpld_ver, 4))
+               pr_info("CPLD version: %s\n", config1.cpld_ver);
+       else
+               pr_err("Unknown CPLD version found\n");
 }
 
 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
@@ -1993,27 +2241,24 @@ static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
                        setup_beaglebone_old();
                else
                        setup_beaglebone();
+       } else if (!strncmp("A335X_SK", config.name, 8)) {
+               daughter_brd_detected = false;
+               setup_starterkit();
        } else {
                /* only 6 characters of options string used for now */
                snprintf(tmp, 7, "%s", config.opt);
                pr_info("SKU: %s\n", tmp);
 
-               if (!strncmp("SKU#00", config.opt, 6))
-                       setup_low_cost_evm();
-               else if (!strncmp("SKU#01", config.opt, 6))
+               if (!strncmp("SKU#01", config.opt, 6))
                        setup_general_purpose_evm();
                else if (!strncmp("SKU#02", config.opt, 6))
                        setup_ind_auto_motor_ctrl_evm();
-               else if (!strncmp("SKU#03", config.opt, 6))
-                       setup_ip_phone_evm();
                else
                        goto out;
        }
-       /* Initialize cpsw after board detection is completed as board
-        * information is required for configuring phy address and hence
-        * should be call only after board detection
-        */
-       am33xx_cpsw_init(gigabit_enable);
+
+       /* SmartReflex also requires board information. */
+       am33xx_sr_init();
 
        return;
 
@@ -2066,6 +2311,7 @@ static struct regulator_init_data am335x_vdd1 = {
        },
        .num_consumer_supplies  = ARRAY_SIZE(am335x_vdd1_supply),
        .consumer_supplies      = am335x_vdd1_supply,
+       .ignore_check_consumers = 1,
 };
 
 static struct regulator_consumer_supply am335x_vdd2_supply[] = {
@@ -2082,6 +2328,7 @@ static struct regulator_init_data am335x_vdd2 = {
        },
        .num_consumer_supplies  = ARRAY_SIZE(am335x_vdd2_supply),
        .consumer_supplies      = am335x_vdd2_supply,
+       .ignore_check_consumers = 1,
 };
 
 static struct tps65910_board am335x_tps65910_info = {
@@ -2109,7 +2356,7 @@ static struct tps65910_board am335x_tps65910_info = {
 *         the below struct. Daughter boards eeprom are probed 1st. Baseboard
 *         eeprom probe is called last.
 */
-static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
+static struct i2c_board_info __initdata am335x_i2c0_boardinfo[] = {
        {
                /* Daughter Board EEPROM */
                I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
@@ -2130,6 +2377,9 @@ static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
                I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
                .platform_data  = &am335x_tps65910_info,
        },
+       {
+               I2C_BOARD_INFO("tlv320aic3x", 0x1b),
+       },
 };
 
 static struct omap_musb_board_data musb_board_data = {
@@ -2178,13 +2428,13 @@ static void evm_init_cpld(void)
 
 static void __init am335x_evm_i2c_init(void)
 {
-       /* Initially assume Low Cost EVM Config */
-       am335x_evm_id = LOW_COST_EVM;
+       /* Initially assume General Purpose EVM Config */
+       am335x_evm_id = GEN_PURP_EVM;
 
        evm_init_cpld();
 
-       omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
-                               ARRAY_SIZE(am335x_i2c_boardinfo));
+       omap_register_i2c_bus(1, 100, am335x_i2c0_boardinfo,
+                               ARRAY_SIZE(am335x_i2c0_boardinfo));
 }
 
 static struct resource am335x_rtc_resources[] = {
@@ -2289,6 +2539,15 @@ void __iomem *am33xx_get_ram_base(void)
        return am33xx_emif_base;
 }
 
+void __iomem *am33xx_gpio0_base;
+
+void __iomem *am33xx_get_gpio0_base(void)
+{
+       am33xx_gpio0_base = ioremap(AM33XX_GPIO0_BASE, SZ_4K);
+
+       return am33xx_gpio0_base;
+}
+
 static struct resource am33xx_cpuidle_resources[] = {
        {
                .start          = AM33XX_EMIF0_BASE,
index a3d7776f7892e77cd68b9d64304f41e3ed5a717b..2dcd4525ec5a62306c51e79877714db878aeb2eb 100644 (file)
@@ -1573,7 +1573,7 @@ static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
 static struct clk cpsw_cpts_rft_clk = {
        .name           = "cpsw_cpts_rft_clk",
        .clkdm_name     = "l3_clkdm",
-       .parent         = &dpll_core_m5_ck,
+       .parent         = &sysclk2_ck,
        .clksel         = cpsw_cpts_rft_clkmux_sel,
        .clksel_reg     = AM33XX_CM_CPTS_RFT_CLKSEL,
        .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
index 4aeefbdb26a4ec39709c829571b74330d72596ae..9b75204c9034258ae3b52c5c01d39748dcf62e83 100644 (file)
 #define AM33XX_SGX_SHIFT               29
 #define AM33XX_SGX_MASK                        (1 << AM33XX_SGX_SHIFT)
 
+/*
+ * CONTROL AM33XX GMII_SEL register for MII mode selection
+ */
+#define AM33XX_CONTROL_GMII_SEL_OFFSET 0x650
+#define AM33XX_RGMII_DISABLE_INT_DLY   (BIT(4) | BIT(5))
+#define AM33XX_MII_MODE_EN             0x0
+#define AM33XX_RMII_MODE_EN            ((1 << 0) | (1 << 2))
+#define AM33XX_RGMII_MODE_EN           ((0x2 << 0) | (0x2 << 2) | \
+                                       (AM33XX_RGMII_DISABLE_INT_DLY))
+
 /*
  * CONTROL AM33XX PWMSS_CTRL register to enable time base clock Enable
  */
index 9e029da4f9a0d049039559319922508467999828..156e3639d53255f28d78432c7b18368ca97a5fb2 100644 (file)
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/export.h>
 #include <linux/slab.h>
 #include <linux/of.h>
 #include <linux/davinci_emac.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/omap4-keypad.h>
+#include <plat/am33xx.h>
 #include <plat/config_pwm.h>
 #include <plat/cpu.h>
 #include <plat/gpmc.h>
+#include <plat/smartreflex.h>
+#include <plat/am33xx.h>
 
 /* LCD controller similar DA8xx */
 #include <video/da8xx-fb.h>
 #include "mux.h"
 #include "control.h"
 #include "devices.h"
+#include "omap_opp_data.h"
 
 #define L3_MODULES_MAX_LEN 12
 #define L3_MODULES 3
 
+static unsigned int   am33xx_evmid;
+
+/*
+ * am33xx_evmid_fillup - set up board evmid
+ * @evmid - evm id which needs to be configured
+ *
+ * This function is called to configure board evm id.
+ * IA Motor Control EVM needs special setting of MAC PHY Id.
+ * This function is called when IA Motor Control EVM is detected
+ * during boot-up.
+ */
+void am33xx_evmid_fillup(unsigned int evmid)
+{
+       am33xx_evmid = evmid;
+       return;
+}
+
 static int __init omap3_l3_init(void)
 {
        int l;
@@ -702,6 +724,74 @@ static void omap_init_sham(void)
        }
        platform_device_register(&sham_device);
 }
+
+#elif defined(CONFIG_CRYPTO_DEV_OMAP4_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP4_SHAM_MODULE)
+
+static struct resource omap4_sham_resources[] = {
+       {
+               .start  = AM33XX_SHA1MD5_P_BASE,
+               .end    = AM33XX_SHA1MD5_P_BASE + 0x120,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .start  = AM33XX_IRQ_SHAEIP57t0_P,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               .start  = AM33XX_DMA_SHAEIP57T0_DIN,
+               .flags  = IORESOURCE_DMA,
+       }
+};
+
+static int omap4_sham_resources_sz = ARRAY_SIZE(omap4_sham_resources);
+
+
+static struct platform_device sham_device = {
+       .name           = "omap4-sham",
+       .id             = -1,
+};
+
+#if 0
+static void omap_init_sham(void)
+{
+       sham_device.resource = omap4_sham_resources;
+       sham_device.num_resources = omap4_sham_resources_sz;
+
+       platform_device_register(&sham_device);
+}
+#endif
+
+int __init omap_init_sham(void)
+{
+       int id = -1;
+       struct platform_device *pdev;
+       struct omap_hwmod *oh;
+       char *oh_name = "sha0";
+       char *name = "omap4-sham";
+
+       oh = omap_hwmod_lookup(oh_name);
+       if (!oh) {
+               pr_err("Could not look up %s\n", oh_name);
+               return -ENODEV;
+       }
+
+       pdev = omap_device_build(name, id, oh, NULL, 0, NULL, 0, 0);
+       //pdev.resource = omap4_sham_resources;
+       //pdev.num_resources = omap4_sham_resources_sz;
+
+       if (IS_ERR(pdev)) {
+               WARN(1, "Can't build omap_device for %s:%s.\n",
+                                               name, oh->name);
+               return PTR_ERR(pdev);
+       }
+
+       return 0;
+}
+
+
+
+
+
 #else
 static inline void omap_init_sham(void) { }
 #endif
@@ -772,6 +862,70 @@ static void omap_init_aes(void)
        platform_device_register(&aes_device);
 }
 
+#elif defined(CONFIG_CRYPTO_DEV_OMAP4_AES) || defined(CONFIG_CRYPTO_DEV_OMAP4_AES_MODULE)
+
+static struct resource omap4_aes_resources[] = {
+       {
+               .start  = AM33XX_AES0_P_BASE,
+               .end    = AM33XX_AES0_P_BASE + 0x4C,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .start  = AM33XX_DMA_AESEIP36T0_DOUT,
+               .flags  = IORESOURCE_DMA,
+       },
+       {
+               .start  = AM33XX_DMA_AESEIP36T0_DIN,
+               .flags  = IORESOURCE_DMA,
+       }
+};
+static int omap4_aes_resources_sz = ARRAY_SIZE(omap4_aes_resources);
+
+static struct platform_device aes_device = {
+       .name           = "omap4-aes",
+       .id             = -1,
+};
+
+#if 0
+static void omap_init_aes(void)
+{
+       aes_device.resource = omap4_aes_resources;
+       aes_device.num_resources = omap4_aes_resources_sz;
+       platform_device_register(&aes_device);
+}
+#endif
+
+int __init omap_init_aes(void)
+{
+       int id = -1;
+       struct platform_device *pdev;
+       struct omap_hwmod *oh;
+       char *oh_name = "aes0";
+       char *name = "omap4-aes";
+
+       oh = omap_hwmod_lookup(oh_name);
+       if (!oh) {
+               pr_err("Could not look up %s\n", oh_name);
+               return -ENODEV;
+       }
+
+       pdev = omap_device_build(name, id, oh, NULL, 0, NULL, 0, 0);
+       //pdev.resource = omap4_sham_resources;
+       //pdev.num_resources = omap4_sham_resources_sz;
+
+       if (IS_ERR(pdev)) {
+               WARN(1, "Can't build omap_device for %s:%s.\n",
+                                               name, oh->name);
+               return PTR_ERR(pdev);
+       }
+
+       return 0;
+}
+
+
+
+
+
 #else
 static inline void omap_init_aes(void) { }
 #endif
@@ -1157,6 +1311,256 @@ static struct platform_device am335x_sgx = {
 
 #endif
 
+#ifdef CONFIG_AM33XX_SMARTREFLEX
+
+/* smartreflex platform data */
+
+/* The values below are based upon silicon characterization data.  
+ * Each OPP and sensor combination potentially has different values.
+ * The values of ERR2VOLT_GAIN and ERR_MIN_LIMIT also change based on
+ * the PMIC step size.  Values have been given to cover the AM335 EVM
+ * (12.5mV step) and the Beaglebone (25mV step).  If the step
+ * size changes, you should update these values, and don't forget to
+ * change the step size in the platform data structure, am33xx_sr_pdata.
+ */
+
+#define AM33XX_SR0_OPP50_CNTRL_OFFSET          0x07B8
+#define AM33XX_SR0_OPP50_EVM_ERR2VOLT_GAIN     0xC
+#define AM33XX_SR0_OPP50_EVM_ERR_MIN_LIMIT     0xF5
+#define AM33XX_SR0_OPP50_BB_ERR2VOLT_GAIN      0x6
+#define AM33XX_SR0_OPP50_BB_ERR_MIN_LIMIT      0xEA
+#define AM33XX_SR0_OPP50_ERR_MAX_LIMIT         0x2
+#define AM33XX_SR0_OPP50_ERR_WEIGHT             0x4
+#define AM33XX_SR0_OPP50_MARGIN                 0
+
+#define AM33XX_SR0_OPP100_CNTRL_OFFSET         0x07BC
+#define AM33XX_SR0_OPP100_EVM_ERR2VOLT_GAIN     0x12
+#define AM33XX_SR0_OPP100_EVM_ERR_MIN_LIMIT    0xF8
+#define AM33XX_SR0_OPP100_BB_ERR2VOLT_GAIN      0x9
+#define AM33XX_SR0_OPP100_BB_ERR_MIN_LIMIT     0xF1
+#define AM33XX_SR0_OPP100_ERR_MAX_LIMIT                0x2
+#define AM33XX_SR0_OPP100_ERR_WEIGHT            0x4
+#define AM33XX_SR0_OPP100_MARGIN                0
+
+#define AM33XX_SR1_OPP50_CNTRL_OFFSET          0x0770
+#define AM33XX_SR1_OPP50_EVM_ERR2VOLT_GAIN     0x5
+#define AM33XX_SR1_OPP50_EVM_ERR_MIN_LIMIT     0xE6
+#define AM33XX_SR1_OPP50_BB_ERR2VOLT_GAIN      0x2
+#define AM33XX_SR1_OPP50_BB_ERR_MIN_LIMIT      0xC0
+#define AM33XX_SR1_OPP50_ERR_MAX_LIMIT         0x2
+#define AM33XX_SR1_OPP50_ERR_WEIGHT             0x4
+#define AM33XX_SR1_OPP50_MARGIN                 0
+
+#define AM33XX_SR1_OPP100_CNTRL_OFFSET         0x0774
+#define AM33XX_SR1_OPP100_EVM_ERR2VOLT_GAIN    0x8
+#define AM33XX_SR1_OPP100_EVM_ERR_MIN_LIMIT    0xF0
+#define AM33XX_SR1_OPP100_BB_ERR2VOLT_GAIN     0x4
+#define AM33XX_SR1_OPP100_BB_ERR_MIN_LIMIT     0xDF
+#define AM33XX_SR1_OPP100_ERR_MAX_LIMIT                0x2
+#define AM33XX_SR1_OPP100_ERR_WEIGHT            0x4
+#define AM33XX_SR1_OPP100_MARGIN                0
+
+#define AM33XX_SR1_OPP120_CNTRL_OFFSET         0x0778
+#define AM33XX_SR1_OPP120_EVM_ERR2VOLT_GAIN    0xB
+#define AM33XX_SR1_OPP120_EVM_ERR_MIN_LIMIT    0xF4
+#define AM33XX_SR1_OPP120_BB_ERR2VOLT_GAIN     0x5
+#define AM33XX_SR1_OPP120_BB_ERR_MIN_LIMIT     0xE6
+#define AM33XX_SR1_OPP120_ERR_MAX_LIMIT                0x2
+#define AM33XX_SR1_OPP120_ERR_WEIGHT            0x4
+#define AM33XX_SR1_OPP120_MARGIN                0
+
+#define AM33XX_SR1_OPPTURBO_CNTRL_OFFSET        0x077C
+#define AM33XX_SR1_OPPTURBO_EVM_ERR2VOLT_GAIN  0xC
+#define AM33XX_SR1_OPPTURBO_EVM_ERR_MIN_LIMIT  0xF5
+#define AM33XX_SR1_OPPTURBO_BB_ERR2VOLT_GAIN   0x6
+#define AM33XX_SR1_OPPTURBO_BB_ERR_MIN_LIMIT   0xEA
+#define AM33XX_SR1_OPPTURBO_ERR_MAX_LIMIT      0x2
+#define AM33XX_SR1_OPPTURBO_ERR_WEIGHT          0x4
+#define AM33XX_SR1_OPPTURBO_MARGIN              0
+
+/* the voltages and frequencies should probably be defined in opp3xxx_data.c.
+   Once SR is integrated to the mainline driver, and voltdm is working
+   correctly in AM335x, these can be removed.  */
+#define AM33XX_VDD_MPU_OPP50_UV                950000
+#define AM33XX_VDD_MPU_OPP100_UV       1100000
+#define AM33XX_VDD_MPU_OPP120_UV       1200000
+#define AM33XX_VDD_MPU_OPPTURBO_UV     1260000
+#define AM33XX_VDD_CORE_OPP50_UV        950000
+#define AM33XX_VDD_CORE_OPP100_UV       1100000
+
+#define AM33XX_VDD_MPU_OPP50_FREQ      275000000
+#define AM33XX_VDD_MPU_OPP100_FREQ     500000000
+#define AM33XX_VDD_MPU_OPP120_FREQ     600000000
+#define AM33XX_VDD_MPU_OPPTURBO_FREQ   720000000
+
+static struct am33xx_sr_opp_data sr1_opp_data[] = {
+        {
+                .efuse_offs    = AM33XX_SR1_OPP50_CNTRL_OFFSET,
+               .e2v_gain       = AM33XX_SR1_OPP50_EVM_ERR2VOLT_GAIN,
+               .err_minlimit   = AM33XX_SR1_OPP50_EVM_ERR_MIN_LIMIT,
+               .err_maxlimit   = AM33XX_SR1_OPP50_ERR_MAX_LIMIT,
+               .err_weight     = AM33XX_SR1_OPP50_ERR_WEIGHT,
+                .margin         = AM33XX_SR1_OPP50_MARGIN,
+                .nominal_volt   = AM33XX_VDD_MPU_OPP50_UV,
+                .frequency      = AM33XX_VDD_MPU_OPP50_FREQ,
+        },
+        {
+                .efuse_offs    = AM33XX_SR1_OPP100_CNTRL_OFFSET,
+               .e2v_gain       = AM33XX_SR1_OPP100_EVM_ERR2VOLT_GAIN,
+               .err_minlimit   = AM33XX_SR1_OPP100_EVM_ERR_MIN_LIMIT,
+               .err_maxlimit   = AM33XX_SR1_OPP100_ERR_MAX_LIMIT,
+               .err_weight     = AM33XX_SR1_OPP100_ERR_WEIGHT,
+                .margin         = AM33XX_SR1_OPP100_MARGIN,
+                .nominal_volt   = AM33XX_VDD_MPU_OPP100_UV,
+                .frequency      = AM33XX_VDD_MPU_OPP100_FREQ,
+        },
+        {
+                .efuse_offs    = AM33XX_SR1_OPP120_CNTRL_OFFSET,
+               .e2v_gain       = AM33XX_SR1_OPP120_EVM_ERR2VOLT_GAIN,
+               .err_minlimit   = AM33XX_SR1_OPP120_EVM_ERR_MIN_LIMIT,
+               .err_maxlimit   = AM33XX_SR1_OPP120_ERR_MAX_LIMIT,
+               .err_weight     = AM33XX_SR1_OPP120_ERR_WEIGHT,
+                .margin         = AM33XX_SR1_OPP120_MARGIN,
+                .nominal_volt   = AM33XX_VDD_MPU_OPP120_UV,
+                .frequency      = AM33XX_VDD_MPU_OPP120_FREQ,
+        },
+        {
+                .efuse_offs    = AM33XX_SR1_OPPTURBO_CNTRL_OFFSET,
+               .e2v_gain       = AM33XX_SR1_OPPTURBO_EVM_ERR2VOLT_GAIN,
+               .err_minlimit   = AM33XX_SR1_OPPTURBO_EVM_ERR_MIN_LIMIT,
+               .err_maxlimit   = AM33XX_SR1_OPPTURBO_ERR_MAX_LIMIT,
+               .err_weight     = AM33XX_SR1_OPPTURBO_ERR_WEIGHT,
+                .margin         = AM33XX_SR1_OPPTURBO_MARGIN,
+                .nominal_volt   = AM33XX_VDD_MPU_OPPTURBO_UV,
+                .frequency      = AM33XX_VDD_MPU_OPPTURBO_FREQ,
+        },
+};
+
+static struct am33xx_sr_opp_data sr0_opp_data[] = {
+        {
+                .efuse_offs    = AM33XX_SR0_OPP50_CNTRL_OFFSET,
+               .e2v_gain       = AM33XX_SR0_OPP50_EVM_ERR2VOLT_GAIN,
+               .err_minlimit   = AM33XX_SR0_OPP50_EVM_ERR_MIN_LIMIT,
+               .err_maxlimit   = AM33XX_SR0_OPP50_ERR_MAX_LIMIT,
+               .err_weight     = AM33XX_SR0_OPP50_ERR_WEIGHT,
+                .margin         = AM33XX_SR0_OPP50_MARGIN,
+                .nominal_volt   = AM33XX_VDD_CORE_OPP50_UV,
+        },
+        {
+                .efuse_offs    = AM33XX_SR0_OPP100_CNTRL_OFFSET,
+               .e2v_gain       = AM33XX_SR0_OPP100_EVM_ERR2VOLT_GAIN,
+               .err_minlimit   = AM33XX_SR0_OPP100_EVM_ERR_MIN_LIMIT,
+               .err_maxlimit   = AM33XX_SR0_OPP100_ERR_MAX_LIMIT,
+               .err_weight     = AM33XX_SR0_OPP100_ERR_WEIGHT,
+                .margin         = AM33XX_SR0_OPP100_MARGIN,
+                .nominal_volt   = AM33XX_VDD_CORE_OPP100_UV,
+        },
+};
+
+static struct am33xx_sr_sdata sr_sensor_data[] = {
+       {
+                .sr_opp_data    = sr0_opp_data,
+                /* note that OPP50 is NOT used in Linux kernel for AM335x */
+                .no_of_opps     = 0x2,
+                .default_opp    = 0x1,
+               .senn_mod       = 0x1,
+               .senp_mod       = 0x1,
+       },
+       {
+               .sr_opp_data    = sr1_opp_data,
+                /* the opp data below should be determined 
+                   dynamically during SR probe */
+                .no_of_opps     = 0x4,
+                .default_opp    = 0x3,
+               .senn_mod       = 0x1,
+               .senp_mod       = 0x1,
+       },
+};
+
+static struct am33xx_sr_platform_data am33xx_sr_pdata = {
+       .vd_name[0]             = "vdd_core",
+        .vd_name[1]             = "vdd_mpu",
+       .ip_type                = 2,
+        .irq_delay              = 1000,
+       .no_of_vds              = 2,
+       .no_of_sens             = ARRAY_SIZE(sr_sensor_data),
+       .vstep_size_uv          = 12500,
+       .enable_on_init         = true,
+       .sr_sdata               = sr_sensor_data,
+};
+
+static struct resource am33xx_sr_resources[] = {
+       {
+               .name   =       "smartreflex0",
+               .start  =       AM33XX_SR0_BASE,
+               .end    =       AM33XX_SR0_BASE + SZ_4K - 1,
+               .flags  =       IORESOURCE_MEM,
+       },
+       {
+               .name   =       "smartreflex0",
+               .start  =       AM33XX_IRQ_SMARTREFLEX0,
+               .end    =       AM33XX_IRQ_SMARTREFLEX0,
+               .flags  =       IORESOURCE_IRQ,
+       },
+       {
+               .name   =       "smartreflex1",
+               .start  =       AM33XX_SR1_BASE,
+               .end    =       AM33XX_SR1_BASE + SZ_4K - 1,
+               .flags  =       IORESOURCE_MEM,
+       },
+       {
+               .name   =       "smartreflex1",
+               .start  =       AM33XX_IRQ_SMARTREFLEX1,
+               .end    =       AM33XX_IRQ_SMARTREFLEX1,
+               .flags  =       IORESOURCE_IRQ,
+       },
+};
+
+/* VCORE for SR regulator init */
+static struct platform_device am33xx_sr_device = {
+       .name           = "smartreflex",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(am33xx_sr_resources),
+       .resource       = am33xx_sr_resources,
+       .dev = {
+               .platform_data = &am33xx_sr_pdata,
+       },
+};
+
+void __init am33xx_sr_init(void)
+{
+        /* For beaglebone, update voltage step size and related parameters 
+           appropriately.  All other AM33XX platforms are good with the 
+           structure defaults as initialized above. */
+        if ((am33xx_evmid == BEAGLE_BONE_OLD) || 
+                        (am33xx_evmid == BEAGLE_BONE_A3)) {
+                printk(KERN_ERR "address of pdata = %08x\n", (u32)&am33xx_sr_pdata);
+                am33xx_sr_pdata.vstep_size_uv = 25000;
+                /* CORE */
+                sr0_opp_data[0].e2v_gain     = AM33XX_SR0_OPP50_BB_ERR2VOLT_GAIN;
+                sr0_opp_data[0].err_minlimit = AM33XX_SR0_OPP50_BB_ERR_MIN_LIMIT;
+                sr0_opp_data[1].e2v_gain     = AM33XX_SR0_OPP100_BB_ERR2VOLT_GAIN;
+                sr0_opp_data[1].err_minlimit = AM33XX_SR0_OPP100_BB_ERR_MIN_LIMIT;
+                /* MPU */
+                sr1_opp_data[0].e2v_gain     = AM33XX_SR1_OPP50_BB_ERR2VOLT_GAIN;
+                sr1_opp_data[0].err_minlimit = AM33XX_SR1_OPP50_BB_ERR_MIN_LIMIT;
+                sr1_opp_data[1].e2v_gain     = AM33XX_SR1_OPP100_BB_ERR2VOLT_GAIN;
+                sr1_opp_data[1].err_minlimit = AM33XX_SR1_OPP100_BB_ERR_MIN_LIMIT;
+                sr1_opp_data[2].e2v_gain     = AM33XX_SR1_OPP120_BB_ERR2VOLT_GAIN;
+                sr1_opp_data[2].err_minlimit = AM33XX_SR1_OPP120_BB_ERR_MIN_LIMIT;
+                sr1_opp_data[3].e2v_gain     = AM33XX_SR1_OPPTURBO_BB_ERR2VOLT_GAIN;
+                sr1_opp_data[3].err_minlimit = AM33XX_SR1_OPPTURBO_BB_ERR_MIN_LIMIT;
+        }
+
+       if (platform_device_register(&am33xx_sr_device))
+               printk(KERN_ERR "failed to register am33xx_sr device\n");
+       else
+               printk(KERN_INFO "registered am33xx_sr device\n");
+}
+#else
+inline void am33xx_sr_init(void) {}
+#endif
+
 /*-------------------------------------------------------------------------*/
 
 static int __init omap2_init_devices(void)
@@ -1189,19 +1593,23 @@ static int __init omap2_init_devices(void)
 arch_initcall(omap2_init_devices);
 
 #define AM33XX_EMAC_MDIO_FREQ          (1000000)
+/* Port Vlan IDs for Dual Mac Mode */
+#define CPSW_PORT_VLAN_SLAVE_0         2
+#define CPSW_PORT_VLAN_SLAVE_1         3
 
-static u64 am33xx_cpsw_dmamask = DMA_BIT_MASK(32);
 /* TODO : Verify the offsets */
 static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
        {
                .slave_reg_ofs  = 0x208,
                .sliver_reg_ofs = 0xd80,
                .phy_id         = "0:00",
+               .dual_emac_reserved_vlan = CPSW_PORT_VLAN_SLAVE_0,
        },
        {
                .slave_reg_ofs  = 0x308,
                .sliver_reg_ofs = 0xdc0,
                .phy_id         = "0:01",
+               .dual_emac_reserved_vlan = CPSW_PORT_VLAN_SLAVE_1,
        },
 };
 
@@ -1229,85 +1637,8 @@ static struct mdio_platform_data am33xx_cpsw_mdiopdata = {
        .bus_freq       = AM33XX_EMAC_MDIO_FREQ,
 };
 
-static struct resource am33xx_cpsw_mdioresources[] = {
-       {
-               .start  = AM33XX_CPSW_MDIO_BASE,
-               .end    = AM33XX_CPSW_MDIO_BASE + SZ_256 - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-};
-
-static struct platform_device am33xx_cpsw_mdiodevice = {
-       .name           = "davinci_mdio",
-       .id             = 0,
-       .num_resources  = ARRAY_SIZE(am33xx_cpsw_mdioresources),
-       .resource       = am33xx_cpsw_mdioresources,
-       .dev.platform_data = &am33xx_cpsw_mdiopdata,
-};
-
-static struct resource am33xx_cpsw_resources[] = {
-       {
-               .start  = AM33XX_CPSW_BASE,
-               .end    = AM33XX_CPSW_BASE + SZ_2K - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       {
-               .start  = AM33XX_CPSW_SS_BASE,
-               .end    = AM33XX_CPSW_SS_BASE + SZ_256 - 1,
-               .flags  = IORESOURCE_MEM,
-       },
-       {
-               .start  = AM33XX_IRQ_CPSW_C0_RX,
-               .end    = AM33XX_IRQ_CPSW_C0_RX,
-               .flags  = IORESOURCE_IRQ,
-       },
-       {
-               .start  = AM33XX_IRQ_DMTIMER5,
-               .end    = AM33XX_IRQ_DMTIMER5,
-               .flags  = IORESOURCE_IRQ,
-       },
-       {
-               .start  = AM33XX_IRQ_DMTIMER6,
-               .end    = AM33XX_IRQ_DMTIMER6,
-               .flags  = IORESOURCE_IRQ,
-       },
-       {
-               .start  = AM33XX_IRQ_CPSW_C0,
-               .end    = AM33XX_IRQ_CPSW_C0,
-               .flags  = IORESOURCE_IRQ,
-       },
-};
-
-static struct platform_device am33xx_cpsw_device = {
-       .name           =       "cpsw",
-       .id             =       0,
-       .num_resources  =       ARRAY_SIZE(am33xx_cpsw_resources),
-       .resource       =       am33xx_cpsw_resources,
-       .dev            =       {
-                                       .platform_data  = &am33xx_cpsw_pdata,
-                                       .dma_mask       = &am33xx_cpsw_dmamask,
-                                       .coherent_dma_mask = DMA_BIT_MASK(32),
-                               },
-};
-
 static unsigned char  am33xx_macid0[ETH_ALEN];
 static unsigned char  am33xx_macid1[ETH_ALEN];
-static unsigned int   am33xx_evmid;
-
-/*
-* am33xx_evmid_fillup - set up board evmid
-* @evmid - evm id which needs to be configured
-*
-* This function is called to configure board evm id.
-* IA Motor Control EVM needs special setting of MAC PHY Id.
-* This function is called when IA Motor Control EVM is detected
-* during boot-up.
-*/
-void am33xx_evmid_fillup(unsigned int evmid)
-{
-       am33xx_evmid = evmid;
-       return;
-}
 
 /*
 * am33xx_cpsw_macidfillup - setup mac adrresses
@@ -1333,14 +1664,12 @@ void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1)
        return;
 }
 
-#define MII_MODE_ENABLE                0x0
-#define RMII_MODE_ENABLE       0x5
-#define RGMII_MODE_ENABLE      0xA
-#define MAC_MII_SEL            0x650
-
-void am33xx_cpsw_init(unsigned int gigen)
+int am33xx_cpsw_init(enum am33xx_cpsw_mac_mode mode, unsigned char *phy_id0,
+                    unsigned char *phy_id1)
 {
-       u32 mac_lo, mac_hi;
+       struct omap_hwmod *oh;
+       struct platform_device *pdev;
+       u32 mac_lo, mac_hi, gmii_sel;
        u32 i;
 
        mac_lo = omap_ctrl_readl(TI81XX_CONTROL_MAC_ID0_LO);
@@ -1373,28 +1702,54 @@ void am33xx_cpsw_init(unsigned int gigen)
                        am33xx_cpsw_slaves[1].mac_addr[i] = am33xx_macid1[i];
        }
 
-       if (am33xx_evmid == BEAGLE_BONE_OLD) {
-               __raw_writel(RMII_MODE_ENABLE,
-                               AM33XX_CTRL_REGADDR(MAC_MII_SEL));
-       } else if (am33xx_evmid == BEAGLE_BONE_A3) {
-               __raw_writel(MII_MODE_ENABLE,
-                               AM33XX_CTRL_REGADDR(MAC_MII_SEL));
-       } else if (am33xx_evmid == IND_AUT_MTR_EVM) {
-               am33xx_cpsw_slaves[0].phy_id = "0:1e";
-               am33xx_cpsw_slaves[1].phy_id = "0:00";
-       } else {
-               __raw_writel(RGMII_MODE_ENABLE,
-                               AM33XX_CTRL_REGADDR(MAC_MII_SEL));
+       switch (mode) {
+       case AM33XX_CPSW_MODE_MII:
+               gmii_sel = AM33XX_MII_MODE_EN;
+               break;
+       case AM33XX_CPSW_MODE_RMII:
+               gmii_sel = AM33XX_RMII_MODE_EN;
+               break;
+       case AM33XX_CPSW_MODE_RGMII:
+               gmii_sel = AM33XX_RGMII_MODE_EN;
+               break;
+       default:
+               return -EINVAL;
        }
 
-       am33xx_cpsw_pdata.gigabit_en = gigen;
+       writel(gmii_sel, AM33XX_CTRL_REGADDR(AM33XX_CONTROL_GMII_SEL_OFFSET));
+
+       if (phy_id0 != NULL)
+               am33xx_cpsw_slaves[0].phy_id = phy_id0;
+
+       if (phy_id1 != NULL)
+               am33xx_cpsw_slaves[1].phy_id = phy_id1;
 
        memcpy(am33xx_cpsw_pdata.mac_addr,
                        am33xx_cpsw_slaves[0].mac_addr, ETH_ALEN);
-       platform_device_register(&am33xx_cpsw_mdiodevice);
-       platform_device_register(&am33xx_cpsw_device);
-       clk_add_alias(NULL, dev_name(&am33xx_cpsw_mdiodevice.dev),
-                       NULL, &am33xx_cpsw_device.dev);
+
+       oh = omap_hwmod_lookup("mdio");
+       if (!oh) {
+               pr_err("could not find cpgmac0 hwmod data\n");
+               return -ENODEV;
+       }
+
+       pdev = omap_device_build("davinci_mdio", 0, oh, &am33xx_cpsw_mdiopdata,
+                       sizeof(am33xx_cpsw_mdiopdata), NULL, 0, 0);
+       if (IS_ERR(pdev))
+               pr_err("could not build omap_device for cpsw\n");
+
+       oh = omap_hwmod_lookup("cpgmac0");
+       if (!oh) {
+               pr_err("could not find cpgmac0 hwmod data\n");
+               return -ENODEV;
+       }
+
+       pdev = omap_device_build("cpsw", -1, oh, &am33xx_cpsw_pdata,
+                       sizeof(am33xx_cpsw_pdata), NULL, 0, 0);
+       if (IS_ERR(pdev))
+               pr_err("could not build omap_device for cpsw\n");
+
+       return 0;
 }
 
 #define AM33XX_DCAN_NUM_MSG_OBJS               64
index a8fe93a223d01cf9d13b0d6549f1d57b64319406..4bec4349bc2f6c9b376f5d8256e56291f6689e34 100644 (file)
 #define DAUG_BOARD_I2C_ADDR    0x51
 #define LCD_BOARD_I2C_ADDR     0x52
 
-#define LOW_COST_EVM           0
-#define GEN_PURP_EVM           1
-#define IND_AUT_MTR_EVM                2
-#define IP_PHN_EVM             3
-#define BEAGLE_BONE_OLD                4
-#define BEAGLE_BONE_A3         5
+#define GEN_PURP_EVM           0
+#define IND_AUT_MTR_EVM                1
+#define BEAGLE_BONE_OLD                2
+#define BEAGLE_BONE_A3         3
+#define EVM_SK                 4
 
 /* REVIST : check posibility of PROFILE_(x) syntax usage */
 #define PROFILE_NONE   -1      /* Few EVM doesn't have profiles */
 #define PROFILE_7              (0x1 << 7)
 #define PROFILE_ALL            0xFF
 
-void am33xx_evmid_fillup(unsigned int evmid);
+#ifndef __ASSEMBLER__
+void am335x_evm_set_id(unsigned int evmid);
+int am335x_evm_get_id(void);
 void am33xx_cpsw_macidfillup(char *eeprommacid0, char *eeprommacid1);
-void am33xx_cpsw_init(unsigned int gigen);
+void am33xx_sr_init(void);
 void am33xx_d_can_init(unsigned int instance);
 
 #endif
+#endif
index 1fef061f7927929be28987d7ca10b270f05f04d3..e6504202a64e3ae346ff501f0e65bb4df84c3f0f 100644 (file)
 static struct omap_irq_bank {
        void __iomem *base_reg;
        unsigned int nr_irqs;
+       unsigned int nr_regs_req;
 } __attribute__ ((aligned(4))) irq_banks[] = {
        {
                /* MPU INTC */
                .nr_irqs        = 96,
+               .nr_regs_req    = 3,
        },
 };
 
@@ -63,8 +65,8 @@ struct omap3_intc_regs {
        u32 protection;
        u32 idle;
        u32 threshold;
-       u32 ilr[INTCPS_NR_IRQS];
-       u32 mir[INTCPS_NR_MIR_REGS];
+       u32 ilr[INTCPS_MAX_NR_IRQS];
+       u32 mir[INTCPS_MAX_NR_REGS_REQ];
 };
 
 /* INTC bank register get/set */
@@ -162,6 +164,7 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
                struct omap_irq_bank *bank = irq_banks + i;
 
                bank->nr_irqs = nr_irqs;
+               bank->nr_regs_req = 0;
 
                /* Static mapping, never released */
                bank->base_reg = ioremap(base, SZ_4K);
@@ -172,8 +175,10 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
 
                omap_irq_bank_init_one(bank);
 
-               for (j = 0; j < bank->nr_irqs; j += 32)
+               for (j = 0; j < bank->nr_irqs; j += 32) {
                        omap_alloc_gc(bank->base_reg + j, j, 32);
+                       bank->nr_regs_req++;
+               }
 
                nr_of_irqs += bank->nr_irqs;
                nr_banks++;
@@ -198,25 +203,19 @@ void __init ti81xx_init_irq(void)
        omap_init_irq(OMAP34XX_IC_BASE, 128);
 }
 
-static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
+static inline void omap_intc_handle_irq(void __iomem *base_addr,
+               unsigned int no_regs_req, struct pt_regs *regs)
 {
-       u32 irqnr;
+       u32 irqnr = 0;
 
        do {
-               irqnr = readl_relaxed(base_addr + 0x98);
-               if (irqnr)
-                       goto out;
-
-               irqnr = readl_relaxed(base_addr + 0xb8);
-               if (irqnr)
-                       goto out;
+               int i = 0;
 
-               irqnr = readl_relaxed(base_addr + 0xd8);
-#ifdef CONFIG_SOC_OMAPTI816X
-               if (irqnr)
-                       goto out;
-               irqnr = readl_relaxed(base_addr + 0xf8);
-#endif
+               for (i = 0; i < no_regs_req; i++) {
+                       irqnr = readl_relaxed(base_addr + 0x98 + (0x20 * i));
+                       if (irqnr)
+                               goto out;
+               }
 
 out:
                if (!irqnr)
@@ -233,7 +232,7 @@ out:
 asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
 {
        void __iomem *base_addr = OMAP2_IRQ_BASE;
-       omap_intc_handle_irq(base_addr, regs);
+       omap_intc_handle_irq(base_addr, irq_banks[0].nr_regs_req, regs);
 }
 
 #ifdef CONFIG_ARCH_OMAP3
@@ -252,10 +251,10 @@ void omap_intc_save_context(void)
                        intc_bank_read_reg(bank, INTC_IDLE);
                intc_context[ind].threshold =
                        intc_bank_read_reg(bank, INTC_THRESHOLD);
-               for (i = 0; i < INTCPS_NR_IRQS; i++)
+               for (i = 0; i < bank->nr_irqs; i++)
                        intc_context[ind].ilr[i] =
                                intc_bank_read_reg(bank, (0x100 + 0x4*i));
-               for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
+               for (i = 0; i < bank->nr_regs_req; i++)
                        intc_context[ind].mir[i] =
                                intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
                                (0x20 * i));
@@ -278,10 +277,10 @@ void omap_intc_restore_context(void)
                                        bank, INTC_IDLE);
                intc_bank_write_reg(intc_context[ind].threshold,
                                        bank, INTC_THRESHOLD);
-               for (i = 0; i < INTCPS_NR_IRQS; i++)
+               for (i = 0; i < bank->nr_irqs; i++)
                        intc_bank_write_reg(intc_context[ind].ilr[i],
                                bank, (0x100 + 0x4*i));
-               for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
+               for (i = 0; i < bank->nr_regs_req; i++)
                        intc_bank_write_reg(intc_context[ind].mir[i],
                                 &irq_banks[0], INTC_MIR0 + (0x20 * i));
        }
@@ -312,6 +311,6 @@ void omap3_intc_resume_idle(void)
 asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
 {
        void __iomem *base_addr = OMAP3_IRQ_BASE;
-       omap_intc_handle_irq(base_addr, regs);
+       omap_intc_handle_irq(base_addr, irq_banks[0].nr_regs_req, regs);
 }
 #endif /* CONFIG_ARCH_OMAP3 */
index e1cc75d1a57ac024ba18382c26daa127ccce3abe..6ad939d7904eff44764b6962e902e1de65df5100 100644 (file)
@@ -566,6 +566,48 @@ static inline void omap_mux_decode(struct seq_file *s, u16 val)
        } while (i-- > 0);
 }
 
+static inline void am33xx_mux_decode(struct seq_file *s, u16 val)
+{
+       char *flags[OMAP_MUX_MAX_NR_FLAGS];
+       char mode[sizeof("OMAP_MUX_MODE") + 1];
+       int i , j;
+
+       i = j = 0;
+       sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
+       flags[i] = mode;
+
+       if (val & AM33XX_INPUT_EN) {
+               j = 1;
+               if (val & AM33XX_PULL_DISA) {
+                       OMAP_MUX_TEST_FLAG(val, AM33XX_PIN_INPUT);
+               } else if (!(val & AM33XX_PULL_UP)) {
+                       OMAP_MUX_TEST_FLAG(val, AM33XX_PIN_INPUT_PULLDOWN);
+               } else {
+                       OMAP_MUX_TEST_FLAG(val, AM33XX_PIN_INPUT_PULLUP);
+               }
+       }
+       if (val & AM33XX_SLEWCTRL_SLOW) {
+               j = 1;
+               OMAP_MUX_TEST_FLAG(val, AM33XX_SLEWCTRL_SLOW);
+       } else if (!(val & AM33XX_INPUT_EN)) {
+               if (val & AM33XX_PIN_OUTPUT_PULLUP) {
+                       j = 1;
+                       OMAP_MUX_TEST_FLAG(val, AM33XX_PIN_OUTPUT_PULLUP);
+               } else if (val & AM33XX_PULL_DISA) {
+                       j = 1;
+                       OMAP_MUX_TEST_FLAG(val, AM33XX_PULL_DISA);
+               }
+       }
+       if (j == 0)
+               OMAP_MUX_TEST_FLAG(val, AM33XX_PIN_OUTPUT);
+
+       for (j = 0; j <= i; j++) {
+               seq_printf(s, "%s", flags[j]);
+               if (j != i)
+                       seq_printf(s, " | ");
+       }
+}
+
 #define OMAP_MUX_DEFNAME_LEN   32
 
 static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
@@ -602,7 +644,10 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
                 * same OMAP generation.
                 */
                seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def);
-               omap_mux_decode(s, val);
+               if (cpu_is_am335x())
+                       am33xx_mux_decode(s, val);
+               else
+                       omap_mux_decode(s, val);
                seq_printf(s, "),\n");
        }
 
@@ -661,7 +706,10 @@ static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
                        m->balls[0] ? m->balls[0] : none,
                        m->balls[1] ? m->balls[1] : none);
        seq_printf(s, "mode: ");
-       omap_mux_decode(s, val);
+       if (cpu_is_am335x())
+               am33xx_mux_decode(s, val);
+       else
+               omap_mux_decode(s, val);
        seq_printf(s, "\n");
        seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n",
                        m->muxnames[0] ? m->muxnames[0] : none,
index 59e51e01ac93202fdfdb18a09ff00cf628886651..150e478ab315ac03bc8b5ff752d5358b1ea15d52 100644 (file)
@@ -139,7 +139,7 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
                NULL, NULL, "mcasp0_fsr", "gpio2_1"),
        _AM33XX_MUXENTRY(GPMC_ADVN_ALE, 0,
                "gpmc_advn_ale", NULL, NULL, NULL,
-               NULL, NULL, NULL, "mmc1_sdcd"),
+               NULL, NULL, NULL, "gpio2_2"),
        _AM33XX_MUXENTRY(GPMC_OEN_REN, 0,
                "gpmc_oen_ren", NULL, NULL, NULL,
                NULL, NULL, NULL, "gpio2_3"),
@@ -340,7 +340,7 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
                "mmc2_sdcd", NULL, NULL, "gpio3_16"),
        _AM33XX_MUXENTRY(MCASP0_AHCLKR, 0,
                "mcasp0_ahclkr", NULL, "mcasp0_axr2", "spi1_cs0",
-               NULL, NULL, NULL, "gpio3_17"),
+               "ecap2_in_pwm2_out", NULL, NULL, "gpio3_17"),
        _AM33XX_MUXENTRY(MCASP0_ACLKR, 0,
                "mcasp0_aclkr", NULL, "mcasp0_axr2", "mcasp1_aclkx",
                "mmc0_sdwp", NULL, NULL, "gpio3_18"),
@@ -354,7 +354,7 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
                "mcasp0_ahclkx", NULL, "mcasp0_axr3", "mcasp1_axr1",
                NULL, NULL, NULL, "gpio3_21"),
        _AM33XX_MUXENTRY(XDMA_EVENT_INTR0, 0,
-               "xdma_event_intr0", NULL, NULL, NULL,
+               "xdma_event_intr0", NULL, NULL, "clkout1",
                "spi1_cs1", NULL, NULL, "gpio0_19"),
        _AM33XX_MUXENTRY(XDMA_EVENT_INTR1, 0,
                "xdma_event_intr1", NULL, NULL, "clkout2",
index bc14f9f69529217245d3cb0cbc0b9d059c228a7b..c638c8cb4ef1f8f96a22d8438776613f11e5a339 100644 (file)
@@ -1343,13 +1343,12 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
         * Note: cpu_is_omap34xx is true for am33xx device as well.
         */
        if (cpu_is_omap44xx() || cpu_is_am33xx()) {
-               if (ohri.st_shift)
-                       pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
-                              oh->name, name);
                ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
+                                 ohri.st_shift,
                                  oh->clkdm->pwrdm.ptr->prcm_partition,
                                  oh->clkdm->pwrdm.ptr->prcm_offs,
-                                 oh->prcm.omap4.rstctrl_offs);
+                                 oh->prcm.omap4.rstctrl_offs,
+                                 oh->prcm.omap4.rstst_offs);
        } else if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
                ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
                                                   ohri.rst_shift,
@@ -1548,16 +1547,6 @@ static int _enable(struct omap_hwmod *oh)
                return -EINVAL;
        }
 
-
-       /*
-        * If an IP contains only one HW reset line, then de-assert it in order
-        * to allow the module state transition. Otherwise the PRCM will return
-        * Intransition status, and the init will failed.
-        */
-       if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
-            oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
-               _deassert_hardreset(oh, oh->rst_lines[0].name);
-
        /* Mux pins for device runtime if populated */
        if (oh->mux && (!oh->mux->enabled ||
                        ((oh->_state == _HWMOD_STATE_IDLE) &&
@@ -1584,6 +1573,18 @@ static int _enable(struct omap_hwmod *oh)
        _enable_clocks(oh);
        _enable_module(oh);
 
+       /*
+        * If an IP contains only one HW reset line, then de-assert it in order
+        * to allow the module state transition. Otherwise the PRCM will return
+        * Intransition status, and the init will failed.
+        *
+        * TODO: Based on observation, on module enable sate, we can safely
+        *      assert the reset signal here (irrespective of idlemode state).
+        */
+       if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
+            oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
+               _deassert_hardreset(oh, oh->rst_lines[0].name);
+
        r = _wait_target_ready(oh);
        if (!r) {
                /*
@@ -1631,6 +1632,13 @@ static int _idle(struct omap_hwmod *oh)
                return -EINVAL;
        }
 
+       /*
+        * FIXME: Due to AM33XX CPSW IP integration bug, it is required
+        * to assert ocp reset signal to the module before disabling it.
+        */
+       if (oh->flags & HWMOD_SWSUP_RESET_BEFORE_IDLE)
+               _reset(oh);
+
        if (oh->class->sysc)
                _idle_sysc(oh);
        _del_initiator_dep(oh, mpu_oh);
index 9d3c9a53d07ee394bd1ee712216b80c81d92ef62..2f9982cc32ca3aab51308cc5bca492e617198741 100644 (file)
  * GNU General Public License for more details.
  */
 
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+
 #include <plat/omap_hwmod.h>
 #include <plat/cpu.h>
 #include <plat/gpio.h>
 #include <plat/mmc.h>
 #include <plat/mcspi.h>
 #include <plat/i2c.h>
+#include <plat/clock.h>
+#include <plat/prcm.h>
 
 #include "omap_hwmod_common_data.h"
 #include "control.h"
 #include "cm33xx.h"
 #include "prm33xx.h"
+#include "common.h"
 
 /* Backward references (IPs with Bus Master capability) */
 static struct omap_hwmod am33xx_mpu_hwmod;
@@ -81,6 +89,63 @@ static struct omap_hwmod am33xx_gpmc_hwmod;
 static struct omap_hwmod am33xx_lcdc_hwmod;
 static struct omap_hwmod am33xx_mailbox_hwmod;
 static struct omap_hwmod am33xx_cpgmac0_hwmod;
+static struct omap_hwmod am33xx_mdio_hwmod;
+
+/*
+ * ERRATA: (Yet to conform from IP team)
+ * As per the observation, in order to disable the cpsw clock/module
+ * from already enabled state, module level reset assertion is
+ * required; without reset the clock/module won't enter into
+ * idle state at all.
+ * Also, as per observation (have not conformed yet), we have to
+ * assert reset signal for all cpsw (4) submodules.
+ */
+
+/* OCP SYSSTATUS bit shifts/masks */
+#define SOFT_RESETDONE_SHIFT           0
+#define SOFT_RESETDONE_MASK            (1 << SOFT_RESETDONE_SHIFT)
+
+#define MAX_MODULE_SOFTRESET_WAIT      10000
+
+static int am33xx_cpgmac_reset(struct omap_hwmod *oh)
+{
+       int i;
+       int ret = 0;
+
+       pr_debug("%s: resetting via Module SOFTRESET bit\n", oh->name);
+
+       for (i = 0; i < oh->slaves_cnt; i++) {
+               int c = 0;
+               void __iomem *va_start;
+               struct omap_hwmod_ocp_if *os;
+               struct omap_hwmod_addr_space *mem;
+
+               os = oh->slaves[i];
+               /* FIXME: Only first instance's OCP_RST is asserted */
+               mem = &os->addr[0];
+
+               va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
+               if (!va_start) {
+                       pr_err("%s: Could not ioremap (%x)\n",
+                                       oh->name, mem->pa_start);
+                       ret = -ENOMEM;
+                       break;
+               }
+               /* Assert reset signal */
+               writel(1, va_start + oh->class->sysc->rst_offs);
+               omap_test_timeout(((readl(va_start + oh->class->sysc->rst_offs)
+                                       & SOFT_RESETDONE_MASK) == 0),
+                               MAX_MODULE_SOFTRESET_WAIT, c);
+
+               if (c == MAX_MODULE_SOFTRESET_WAIT) {
+                       pr_warning("%s: softreset failed (waited %d usec)\n",
+                                       oh->name, MAX_MODULE_SOFTRESET_WAIT);
+                       ret = -ETIMEDOUT;
+               }
+       }
+
+       return ret;
+}
 
 /*
  * Interconnects hwmod structures
@@ -369,11 +434,18 @@ static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
        { .irq = -1 }
 };
 
+static struct omap_hwmod_dma_info am33xx_aes0_dma[] = {
+       { .dma_req = AM33XX_DMA_AESEIP36T0_DOUT },
+       { .dma_req = AM33XX_DMA_AESEIP36T0_DIN },
+       { .dma_req = -1 }
+};
+
 static struct omap_hwmod am33xx_aes0_hwmod = {
        .name           = "aes0",
        .class          = &am33xx_aes_hwmod_class,
        .clkdm_name     = "l3_clkdm",
        .mpu_irqs       = am33xx_aes0_irqs,
+       .sdma_reqs      = am33xx_aes0_dma,
        .main_clk       = "aes0_fck",
        .prcm           = {
                .omap4  = {
@@ -450,23 +522,32 @@ static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
        .rev_offs       = 0x0,
        .sysc_offs      = 0x8,
        .syss_offs      = 0x4,
-       .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
-                       SYSS_HAS_RESET_STATUS),
+       .rst_offs       = 0x8,
+       .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
                        MSTANDBY_NO),
        .sysc_fields    = &omap_hwmod_sysc_type3,
 };
 
 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
-       .name           = "cpgmac0",
+       .name           = "cpsw",
        .sysc           = &am33xx_cpgmac_sysc,
+       .reset          = am33xx_cpgmac_reset,
 };
 
+/* Used by driver */
 struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
+       /* cpsw ss */
+       {
+               .pa_start       = 0x4A100000,
+               .pa_end         = 0x4A100000 + SZ_2K - 1,
+               .flags          = ADDR_MAP_ON_INIT,
+       },
+       /* cpsw wr */
        {
                .pa_start       = 0x4A101200,
-               .pa_end         = 0x4A101200 + SZ_8K - 1,
-               .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+               .pa_end         = 0x4A101200 + SZ_256 - 1,
+               .flags          = ADDR_TYPE_RT,
        },
        { }
 };
@@ -478,14 +559,68 @@ struct omap_hwmod_ocp_if am33xx_l3_main__cpgmac0 = {
        .user           = OCP_USER_MPU,
 };
 
+struct omap_hwmod_addr_space am33xx_cpsw_sl1_addr_space[] = {
+       /* cpsw sl1 */
+       {
+               .pa_start       = 0x4A100D84,
+               .pa_end         = 0x4A100D84 + SZ_32 - 1,
+               .flags          = ADDR_TYPE_RT,
+       },
+       { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__cpsw_sl1 = {
+       .master         = &am33xx_l3_main_hwmod,
+       .slave          = &am33xx_cpgmac0_hwmod,
+       .addr           = am33xx_cpsw_sl1_addr_space,
+       .user           = OCP_USER_MPU,
+};
+
+struct omap_hwmod_addr_space am33xx_cpsw_sl2_addr_space[] = {
+       /* cpsw sl2 */
+       {
+               .pa_start       = 0x4A100DC4,
+               .pa_end         = 0x4A100DC4 + SZ_32 - 1,
+               .flags          = ADDR_TYPE_RT,
+       },
+       { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__cpsw_sl2 = {
+       .master         = &am33xx_l3_main_hwmod,
+       .slave          = &am33xx_cpgmac0_hwmod,
+       .addr           = am33xx_cpsw_sl2_addr_space,
+       .user           = OCP_USER_MPU,
+};
+
+struct omap_hwmod_addr_space am33xx_cpsw_cpdma_addr_space[] = {
+       /* cpsw cpdma */
+       {
+               .pa_start       = 0x4A100814,
+               .pa_end         = 0x4A100814 + SZ_32 - 1,
+               .flags          = ADDR_TYPE_RT,
+       },
+       { }
+};
+
+struct omap_hwmod_ocp_if am33xx_l3_main__cpsw_cpdma = {
+       .master         = &am33xx_l3_main_hwmod,
+       .slave          = &am33xx_cpgmac0_hwmod,
+       .addr           = am33xx_cpsw_cpdma_addr_space,
+       .user           = OCP_USER_MPU,
+};
+
 static struct omap_hwmod_ocp_if *am33xx_cpgmac0_slaves[] = {
        &am33xx_l3_main__cpgmac0,
+       &am33xx_l3_main__cpsw_sl1,
+       &am33xx_l3_main__cpsw_sl2,
+       &am33xx_l3_main__cpsw_cpdma,
 };
 
 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
        { .name = "c0_rx_thresh_pend", .irq = 40 },
-       { .name = "c0_rx_pend", .irq = 41 },
-       { .name = "c0_tx_pend", .irq = 42 },
+       { .name = "c0_rx_pend", .irq = 93 },
+       { .name = "c0_tx_pend", .irq = 94 },
        { .name = "c0_misc_pend", .irq = 43 },
        { .irq = -1 }
 };
@@ -505,7 +640,41 @@ static struct omap_hwmod am33xx_cpgmac0_hwmod = {
        .slaves         = am33xx_cpgmac0_slaves,
        .slaves_cnt     = ARRAY_SIZE(am33xx_cpgmac0_slaves),
        .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
-                               HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+                               HWMOD_SWSUP_RESET_BEFORE_IDLE),
+};
+
+/* mdio class */
+static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
+       .name           = "davinci_mdio",
+};
+
+struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
+       {
+               .pa_start       = 0x4A101000,
+               .pa_end         = 0x4A101000 + SZ_256 - 1,
+               .flags          = ADDR_MAP_ON_INIT,
+       },
+       { }
+};
+
+struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
+       .master         = &am33xx_cpgmac0_hwmod,
+       .slave          = &am33xx_mdio_hwmod,
+       .addr           = am33xx_mdio_addr_space,
+       .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_ocp_if *am33xx_mdio_slaves[] = {
+       &am33xx_cpgmac0__mdio,
+};
+
+static struct omap_hwmod am33xx_mdio_hwmod = {
+       .name           = "mdio",
+       .class          = &am33xx_mdio_hwmod_class,
+       .clkdm_name     = "cpsw_125mhz_clkdm",
+       .main_clk       = "cpgmac0_ick",
+       .slaves         = am33xx_mdio_slaves,
+       .slaves_cnt     = ARRAY_SIZE(am33xx_mdio_slaves),
 };
 
 /* 'dcan' class */
@@ -1054,7 +1223,7 @@ static struct omap_hwmod am33xx_gpio0_hwmod = {
        .clkdm_name     = "l4_wkup_clkdm",
        .mpu_irqs       = am33xx_gpio0_irqs,
        .main_clk       = "gpio0_ick",
-       .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+       .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET | HWMOD_INIT_NO_RESET,
        .prcm           = {
                .omap4  = {
                        .clkctrl_offs   = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
@@ -2003,15 +2172,21 @@ static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 };
 
 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
-       { .irq = 108 },
+       { .irq = AM33XX_IRQ_SHAEIP57t0_P },
        { .irq = -1 }
 };
 
+static struct omap_hwmod_dma_info am33xx_sha0_dma[] = {
+       { .dma_req = AM33XX_DMA_SHAEIP57T0_DIN },
+       { .dma_req = -1 }
+};
+
 static struct omap_hwmod am33xx_sha0_hwmod = {
        .name           = "sha0",
        .class          = &am33xx_sha0_hwmod_class,
        .clkdm_name     = "l3_clkdm",
        .mpu_irqs       = am33xx_sha0_irqs,
+       .sdma_reqs      = am33xx_sha0_dma,
        .main_clk       = "sha0_fck",
        .prcm           = {
                .omap4  = {
@@ -3149,6 +3324,7 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
                .omap4  = {
                        .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
                        .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
+                       .rstst_offs     = AM33XX_RM_WKUP_RSTST_OFFSET,
                        .modulemode     = MODULEMODE_SWCTRL,
                },
        },
@@ -3240,7 +3416,7 @@ static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 };
 
 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
-       { .name = "gfx", .rst_shift = 0 },
+       { .name = "gfx", .rst_shift = 0, .st_shift = 0 },
 };
 
 static struct omap_hwmod am33xx_gfx_hwmod = {
@@ -3252,6 +3428,7 @@ static struct omap_hwmod am33xx_gfx_hwmod = {
                .omap4  = {
                        .clkctrl_offs   = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
                        .rstctrl_offs   = AM33XX_RM_GFX_RSTCTRL_OFFSET,
+                       .rstst_offs     = AM33XX_RM_GFX_RSTST_OFFSET,
                        .modulemode     = MODULEMODE_SWCTRL,
                },
        },
@@ -3278,6 +3455,7 @@ static struct omap_hwmod am33xx_pruss_hwmod = {
                .omap4  = {
                        .clkctrl_offs   = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
                        .rstctrl_offs   = AM33XX_RM_PER_RSTCTRL_OFFSET,
+                       .rstst_offs     = AM33XX_RM_PER_RSTST_OFFSET,
                        .modulemode     = MODULEMODE_SWCTRL,
                },
        },
@@ -3391,6 +3569,8 @@ static __initdata struct omap_hwmod *am33xx_hwmods[] = {
        &am33xx_usbss_hwmod,
        /* cpgmac0 class */
        &am33xx_cpgmac0_hwmod,
+       /* mdio class */
+       &am33xx_mdio_hwmod,
        /* tptc class */
        &am33xx_tptc0_hwmod,
        &am33xx_tptc1_hwmod,
index 0e540c8c2a357bcd31e73d368364e6a373ac43d4..9fbcfc336fdbb94fb4c203ef5421eab3c86d4d9e 100644 (file)
@@ -154,7 +154,15 @@ static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
 
 /* VDD1 */
 
-#define AM33XX_VDD_MPU_OPP50_UV                950000
+/*
+ * Errata 1.0.15: OPP50 Operation on MPU Domain is Not Supported.
+ *
+ * To minimize power consumption, the ARM Cortex-A8 may be operated at
+ * the lower frequency defined by OPP50, but the respective voltage
+ * domain VDD_MPU must be operated as defined by OPP100. So MPU OPP50
+ * definition is modified to 275MHz, 1.1V.
+ */
+#define AM33XX_VDD_MPU_OPP50_UV                1100000
 #define AM33XX_VDD_MPU_OPP100_UV       1100000
 #define AM33XX_VDD_MPU_OPP120_UV       1200000
 #define AM33XX_VDD_MPU_OPPTURBO_UV     1260000
index 68aeafced4449f16753f6ee049ae80f9e2fe5863..2bbb7a14c0dcd3b818f6f943d25363369eef1a67 100644 (file)
@@ -100,8 +100,9 @@ extern void omap3_save_scratchpad_contents(void);
 /* am33xx_do_wfi function pointer and size, for copy to SRAM */
 extern void am33xx_do_wfi(void);
 extern unsigned int am33xx_do_wfi_sz;
+extern unsigned int am33xx_resume_offset;
 /* ... and its pointer from SRAM after copy */
-extern void (*am33xx_do_wfi_sram)(void);
+extern void (*am33xx_do_wfi_sram)(u32 *);
 /* The resume location */
 extern void am33xx_resume_vector(void);
 
index 70bcb42ae4ce30d99890c39401f7c0657e3533fe..c607a7587f1ed1136abde4209eb5fede7e57f6f2 100644 (file)
 #include <linux/completion.h>
 #include <linux/pm_runtime.h>
 
+#include <mach/board-am335xevm.h>
 #include <plat/prcm.h>
 #include <plat/mailbox.h>
 #include <plat/sram.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
+#include <plat/emif.h>
 
 #include <asm/suspend.h>
 #include <asm/proc-fns.h>
 #include "clockdomain.h"
 #include "powerdomain.h"
 
-void (*am33xx_do_wfi_sram)(void);
+void (*am33xx_do_wfi_sram)(u32 *);
 
 #define DS_MODE                DS0_ID  /* DS0/1_ID */
 #define MODULE_DISABLE 0x0
 #define MODULE_ENABLE  0x2
 
 #ifdef CONFIG_SUSPEND
-
 void __iomem *ipc_regs;
 void __iomem *m3_eoi;
 void __iomem *m3_code;
+u32 suspend_cfg_param_list[SUSPEND_CFG_PARAMS_END];
 
 bool enable_deep_sleep = true;
 static suspend_state_t suspend_state = PM_SUSPEND_ON;
 
 static struct device *mpu_dev;
 static struct omap_mbox *m3_mbox;
-static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm;
+static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm;
 static struct clockdomain *gfx_l3_clkdm, *gfx_l4ls_clkdm;
 
-static struct am33xx_padconf lp_padconf;
-static int gmii_sel;
-
-static int core_suspend_stat = -1;
 static int m3_state = M3_STATE_UNKNOWN;
 
 static int am33xx_ipc_cmd(struct a8_wkup_m3_ipc_data *);
-static int am33xx_verify_lp_state(void);
+static int am33xx_verify_lp_state(int);
 static void am33xx_m3_state_machine_reset(void);
 
 static DECLARE_COMPLETION(a8_m3_sync);
 
 static void save_padconf(void)
 {
-       lp_padconf.mii1_col     = readl(AM33XX_CTRL_REGADDR(0x0908));
-       lp_padconf.mii1_crs     = readl(AM33XX_CTRL_REGADDR(0x090c));
-       lp_padconf.mii1_rxerr   = readl(AM33XX_CTRL_REGADDR(0x0910));
-       lp_padconf.mii1_txen    = readl(AM33XX_CTRL_REGADDR(0x0914));
-       lp_padconf.mii1_rxdv    = readl(AM33XX_CTRL_REGADDR(0x0918));
-       lp_padconf.mii1_txd3    = readl(AM33XX_CTRL_REGADDR(0x091c));
-       lp_padconf.mii1_txd2    = readl(AM33XX_CTRL_REGADDR(0x0920));
-       lp_padconf.mii1_txd1    = readl(AM33XX_CTRL_REGADDR(0x0924));
-       lp_padconf.mii1_txd0    = readl(AM33XX_CTRL_REGADDR(0x0928));
-       lp_padconf.mii1_txclk   = readl(AM33XX_CTRL_REGADDR(0x092c));
-       lp_padconf.mii1_rxclk   = readl(AM33XX_CTRL_REGADDR(0x0930));
-       lp_padconf.mii1_rxd3    = readl(AM33XX_CTRL_REGADDR(0x0934));
-       lp_padconf.mii1_rxd2    = readl(AM33XX_CTRL_REGADDR(0x0938));
-       lp_padconf.mii1_rxd1    = readl(AM33XX_CTRL_REGADDR(0x093c));
-       lp_padconf.mii1_rxd0    = readl(AM33XX_CTRL_REGADDR(0x0940));
-       lp_padconf.rmii1_refclk = readl(AM33XX_CTRL_REGADDR(0x0944));
-       lp_padconf.mdio_data    = readl(AM33XX_CTRL_REGADDR(0x0948));
-       lp_padconf.mdio_clk     = readl(AM33XX_CTRL_REGADDR(0x094c));
-       gmii_sel                = readl(AM33XX_CTRL_REGADDR(0x0650));
+       struct am33xx_padconf_regs *temp = am33xx_lp_padconf;
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(am33xx_lp_padconf); i++, temp++)
+               temp->val = readl(AM33XX_CTRL_REGADDR(temp->offset));
 }
 
 static void restore_padconf(void)
 {
-       writel(lp_padconf.mii1_col, AM33XX_CTRL_REGADDR(0x0908));
-       writel(lp_padconf.mii1_crs, AM33XX_CTRL_REGADDR(0x090c));
-       writel(lp_padconf.mii1_rxerr, AM33XX_CTRL_REGADDR(0x0910));
-       writel(lp_padconf.mii1_txen, AM33XX_CTRL_REGADDR(0x0914));
-       writel(lp_padconf.mii1_rxdv, AM33XX_CTRL_REGADDR(0x0918));
-       writel(lp_padconf.mii1_txd3, AM33XX_CTRL_REGADDR(0x091c));
-       writel(lp_padconf.mii1_txd2, AM33XX_CTRL_REGADDR(0x0920));
-       writel(lp_padconf.mii1_txd1, AM33XX_CTRL_REGADDR(0x0924));
-       writel(lp_padconf.mii1_txd0, AM33XX_CTRL_REGADDR(0x0928));
-       writel(lp_padconf.mii1_txclk, AM33XX_CTRL_REGADDR(0x092c));
-       writel(lp_padconf.mii1_rxclk, AM33XX_CTRL_REGADDR(0x0930));
-       writel(lp_padconf.mii1_rxd3, AM33XX_CTRL_REGADDR(0x0934));
-       writel(lp_padconf.mii1_rxd2, AM33XX_CTRL_REGADDR(0x0938));
-       writel(lp_padconf.mii1_rxd1, AM33XX_CTRL_REGADDR(0x093c));
-       writel(lp_padconf.mii1_rxd0, AM33XX_CTRL_REGADDR(0x0940));
-       writel(lp_padconf.rmii1_refclk, AM33XX_CTRL_REGADDR(0x0944));
-       writel(lp_padconf.mdio_data, AM33XX_CTRL_REGADDR(0x0948));
-       writel(lp_padconf.mdio_clk, AM33XX_CTRL_REGADDR(0x094c));
-       writel(gmii_sel, AM33XX_CTRL_REGADDR(0x0650));
+       struct am33xx_padconf_regs *temp = am33xx_lp_padconf;
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(am33xx_lp_padconf); i++, temp++)
+               writel(temp->val, AM33XX_CTRL_REGADDR(temp->offset));
 }
 
 static int am33xx_pm_prepare_late(void)
@@ -137,7 +107,8 @@ static void am33xx_pm_finish(void)
 
 static int am33xx_do_sram_idle(long unsigned int state)
 {
-       am33xx_do_wfi_sram();
+       am33xx_do_wfi_sram(&suspend_cfg_param_list[0]);
+
        return 0;
 }
 
@@ -145,17 +116,14 @@ static int am33xx_pm_suspend(void)
 {
        int state, ret = 0;
 
-       struct omap_hwmod *cpgmac_oh, *gpmc_oh, *usb_oh;
+       struct omap_hwmod *gpmc_oh, *usb_oh;
 
-       cpgmac_oh       = omap_hwmod_lookup("cpgmac0");
        usb_oh          = omap_hwmod_lookup("usb_otg_hs");
        gpmc_oh         = omap_hwmod_lookup("gpmc");
 
-       omap_hwmod_enable(cpgmac_oh);
        omap_hwmod_enable(usb_oh);
        omap_hwmod_enable(gpmc_oh);
 
-       omap_hwmod_idle(cpgmac_oh);
        omap_hwmod_idle(usb_oh);
        omap_hwmod_idle(gpmc_oh);
 
@@ -190,7 +158,7 @@ static int am33xx_pm_suspend(void)
                clkdm_wakeup(gfx_l4ls_clkdm);
        }
 
-       core_suspend_stat = ret;
+       ret = am33xx_verify_lp_state(ret);
 
        return ret;
 }
@@ -217,7 +185,13 @@ static int am33xx_pm_begin(suspend_state_t state)
 
        disable_hlt();
 
-       am33xx_lp_ipc.resume_addr = DS_RESUME_ADDR;
+       /*
+        * Populate the resume address as part of IPC data
+        * The offset to be added comes from sleep33xx.S
+        * Add 4 bytes to ensure that resume happens from
+        * the word *after* the word which holds the resume offset
+        */
+       am33xx_lp_ipc.resume_addr = (DS_RESUME_BASE + am33xx_resume_offset + 4);
        am33xx_lp_ipc.sleep_mode  = DS_MODE;
        am33xx_lp_ipc.ipc_data1   = DS_IPC_DEFAULT;
        am33xx_lp_ipc.ipc_data2   = DS_IPC_DEFAULT;
@@ -275,12 +249,8 @@ static void am33xx_m3_state_machine_reset(void)
 
 static void am33xx_pm_end(void)
 {
-       int ret;
-
        suspend_state = PM_SUSPEND_ON;
 
-       ret = am33xx_verify_lp_state();
-
        omap_mbox_enable_irq(m3_mbox, IRQ_RX);
 
        am33xx_m3_state_machine_reset();
@@ -310,7 +280,7 @@ int am33xx_ipc_cmd(struct a8_wkup_m3_ipc_data *data)
 }
 
 /* return 0 if no reset M3 needed, 1 otherwise */
-static int am33xx_verify_lp_state(void)
+static int am33xx_verify_lp_state(int core_suspend_stat)
 {
        int status, ret = 0;
 
@@ -325,6 +295,8 @@ static int am33xx_verify_lp_state(void)
 
        if (status == 0x0) {
                pr_info("Successfully transitioned all domains to low power state\n");
+               if (am33xx_lp_ipc.sleep_mode == DS0_ID)
+                       per_pwrdm->ret_logic_off_counter++;
                goto clear_old_status;
        } else if (status == 0x10000) {
                pr_err("Could not enter low power state\n"
@@ -511,39 +483,77 @@ static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
  */
 void am33xx_push_sram_idle(void)
 {
-       am33xx_do_wfi_sram = omap_sram_push(am33xx_do_wfi, am33xx_do_wfi_sz);
+       am33xx_do_wfi_sram = (void *)omap_sram_push
+                                       (am33xx_do_wfi, am33xx_do_wfi_sz);
 }
 
 static int __init am33xx_pm_init(void)
 {
        int ret;
+#ifdef CONFIG_SUSPEND
+       void __iomem *base;
+       u32 reg;
+       u32 evm_id;
 
+#endif
        if (!cpu_is_am33xx())
                return -ENODEV;
 
        pr_info("Power Management for AM33XX family\n");
 
 #ifdef CONFIG_SUSPEND
+
+#ifdef CONFIG_TI_PM_DISABLE_VT_SWITCH
+       pm_set_vt_switch(0);
+#endif
+
+/* Read SDRAM_CONFIG register to determine Memory Type */
+       base = am33xx_get_ram_base();
+       reg = readl(base + EMIF4_0_SDRAM_CONFIG);
+       reg = (reg & SDRAM_TYPE_MASK) >> SDRAM_TYPE_SHIFT;
+       suspend_cfg_param_list[MEMORY_TYPE] = reg;
+
+/*
+ * vtp_ctrl register value for DDR2 and DDR3 as suggested
+ * by h/w team
+ */
+       if (reg == MEM_TYPE_DDR2)
+               suspend_cfg_param_list[SUSP_VTP_CTRL_VAL] = SUSP_VTP_CTRL_DDR2;
+       else
+               suspend_cfg_param_list[SUSP_VTP_CTRL_VAL] = SUSP_VTP_CTRL_DDR3;
+
+
+       /* Get Board Id */
+       evm_id = am335x_evm_get_id();
+       if (evm_id != -EINVAL)
+               suspend_cfg_param_list[EVM_ID] = evm_id;
+       else
+               suspend_cfg_param_list[EVM_ID] = 0xff;
+
        (void) clkdm_for_each(clkdms_setup, NULL);
 
        /* CEFUSE domain should be turned off post bootup */
        cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm");
        if (cefuse_pwrdm == NULL)
-               printk(KERN_ERR "Failed to get cefuse_pwrdm\n");
+               pr_err("Failed to get cefuse_pwrdm\n");
        else
                pwrdm_set_next_pwrst(cefuse_pwrdm, PWRDM_POWER_OFF);
 
        gfx_pwrdm = pwrdm_lookup("gfx_pwrdm");
        if (gfx_pwrdm == NULL)
-               printk(KERN_ERR "Failed to get gfx_pwrdm\n");
+               pr_err("Failed to get gfx_pwrdm\n");
+
+       per_pwrdm = pwrdm_lookup("per_pwrdm");
+       if (per_pwrdm == NULL)
+               pr_err("Failed to get per_pwrdm\n");
 
        gfx_l3_clkdm = clkdm_lookup("gfx_l3_clkdm");
        if (gfx_l3_clkdm == NULL)
-               printk(KERN_ERR "Failed to get gfx_l3_clkdm\n");
+               pr_err("Failed to get gfx_l3_clkdm\n");
 
        gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
        if (gfx_l4ls_clkdm == NULL)
-               printk(KERN_ERR "Failed to get gfx_l4ls_gfx_clkdm\n");
+               pr_err("Failed to get gfx_l4ls_gfx_clkdm\n");
 
        mpu_dev = omap_device_get_by_hwmod_name("mpu");
 
index 3a00eaa96dd489261013259c51536d27bfb36c09..adf56bf8637b616f55bf17b96a96e7c1909ee450 100644 (file)
 #define __ARCH_ARM_MACH_OMAP2_PM33XX_H
 
 #include <mach/hardware.h>     /* XXX Is this the right one to include? */
+#include "control.h"
+#include "mux33xx.h"
 
 #ifndef __ASSEMBLER__
 extern void __iomem *am33xx_get_ram_base(void);
 
+/*
+ * This enum is used to index the array passed to suspend routine with
+ * parameters that vary across DDR2 and DDR3 sleep sequence.
+ *
+ * Since these are used to load into registers by suspend code,
+ * entries here must always be in sync with the suspend code
+ * in arm/mach-omap2/sleep33xx.S
+ */
+enum suspend_cfg_params {
+       MEMORY_TYPE = 0,
+       SUSP_VTP_CTRL_VAL,
+       EVM_ID,
+       SUSPEND_CFG_PARAMS_END /* Must be the last entry */
+};
+
 struct a8_wkup_m3_ipc_data {
        int resume_addr;
        int sleep_mode;
@@ -23,31 +40,54 @@ struct a8_wkup_m3_ipc_data {
        int ipc_data2;
 } am33xx_lp_ipc;
 
-struct am33xx_padconf {
-       int     mii1_col;
-       int     mii1_crs;
-       int     mii1_rxerr;
-       int     mii1_txen;
-       int     mii1_rxdv;
-       int     mii1_txd3;
-       int     mii1_txd2;
-       int     mii1_txd1;
-       int     mii1_txd0;
-       int     mii1_txclk;
-       int     mii1_rxclk;
-       int     mii1_rxd3;
-       int     mii1_rxd2;
-       int     mii1_rxd1;
-       int     mii1_rxd0;
-       int     rmii1_refclk;
-       int     mdio_data;
-       int     mdio_clk;
+struct am33xx_padconf_regs {
+       u16 offset;
+       u32 val;
+};
+
+#ifdef CONFIG_SUSPEND
+static struct am33xx_padconf_regs am33xx_lp_padconf[] = {
+       {.offset = AM33XX_CONTROL_GMII_SEL_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_GPMC_A0_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_GPMC_A1_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_GPMC_A2_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_GPMC_A3_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_GPMC_A4_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_GPMC_A5_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_GPMC_A6_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_GPMC_A7_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_GPMC_A8_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_GPMC_A9_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_GPMC_A10_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_GPMC_A11_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_GPMC_WAIT0_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_GPMC_WPN_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_GPMC_BEN1_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_COL_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_CRS_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_RXERR_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_TXEN_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_RXDV_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_TXD3_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_TXD2_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_TXD1_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_TXD0_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_TXCLK_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_RXCLK_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_RXD3_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_RXD2_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_RXD1_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_RXD0_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MII1_REFCLK_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MDIO_DATA_OFFSET},
+       {.offset = AM33XX_CONTROL_PADCONF_MDIO_CLK_OFFSET},
 };
+#endif /* CONFIG_SUSPEND */
 #endif /* ASSEMBLER */
 
 #define M3_TXEV_EOI                    (AM33XX_CTRL_BASE + 0x1324)
 #define A8_M3_IPC_REGS                 (AM33XX_CTRL_BASE + 0x1328)
-#define DS_RESUME_ADDR                 0x40300340
+#define DS_RESUME_BASE                 0x40300000
 #define DS_IPC_DEFAULT                 0xffffffff
 #define M3_UMEM                                0x44D00000
 
@@ -60,92 +100,22 @@ struct am33xx_padconf {
 #define M3_STATE_MSG_FOR_LP            2
 #define M3_STATE_MSG_FOR_RESET         3
 
-/* DDR offsets */
-#define DDR_CMD0_IOCTRL                        (AM33XX_CTRL_BASE + 0x1404)
-#define DDR_CMD1_IOCTRL                        (AM33XX_CTRL_BASE + 0x1408)
-#define DDR_CMD2_IOCTRL                        (AM33XX_CTRL_BASE + 0x140C)
-#define DDR_DATA0_IOCTRL               (AM33XX_CTRL_BASE + 0x1440)
-#define DDR_DATA1_IOCTRL               (AM33XX_CTRL_BASE + 0x1444)
-
-#define DDR_IO_CTRL                    (AM33XX_CTRL_BASE + 0x0E04)
-#define VTP0_CTRL_REG                  (AM33XX_CTRL_BASE + 0x0E0C)
-#define DDR_CKE_CTRL                   (AM33XX_CTRL_BASE + 0x131C)
-#define DDR_PHY_BASE_ADDR              (AM33XX_CTRL_BASE + 0x2000)
-
-#define CMD0_CTRL_SLAVE_RATIO_0                (DDR_PHY_BASE_ADDR + 0x01C)
-#define CMD0_CTRL_SLAVE_FORCE_0                (DDR_PHY_BASE_ADDR + 0x020)
-#define CMD0_CTRL_SLAVE_DELAY_0                (DDR_PHY_BASE_ADDR + 0x024)
-#define CMD0_DLL_LOCK_DIFF_0           (DDR_PHY_BASE_ADDR + 0x028)
-#define CMD0_INVERT_CLKOUT_0           (DDR_PHY_BASE_ADDR + 0x02C)
-
-#define CMD1_CTRL_SLAVE_RATIO_0                (DDR_PHY_BASE_ADDR + 0x050)
-#define CMD1_CTRL_SLAVE_FORCE_0                (DDR_PHY_BASE_ADDR + 0x054)
-#define CMD1_CTRL_SLAVE_DELAY_0                (DDR_PHY_BASE_ADDR + 0x058)
-#define CMD1_DLL_LOCK_DIFF_0           (DDR_PHY_BASE_ADDR + 0x05C)
-#define CMD1_INVERT_CLKOUT_0           (DDR_PHY_BASE_ADDR + 0x060)
-
-#define CMD2_CTRL_SLAVE_RATIO_0                (DDR_PHY_BASE_ADDR + 0x084)
-#define CMD2_CTRL_SLAVE_FORCE_0                (DDR_PHY_BASE_ADDR + 0x088)
-#define CMD2_CTRL_SLAVE_DELAY_0                (DDR_PHY_BASE_ADDR + 0x08C)
-#define CMD2_DLL_LOCK_DIFF_0           (DDR_PHY_BASE_ADDR + 0x090)
-#define CMD2_INVERT_CLKOUT_0           (DDR_PHY_BASE_ADDR + 0x094)
-
-#define DATA0_RD_DQS_SLAVE_RATIO_0     (DDR_PHY_BASE_ADDR + 0x0C8)
-#define DATA0_RD_DQS_SLAVE_RATIO_1     (DDR_PHY_BASE_ADDR + 0x0CC)
-
-#define DATA0_WR_DQS_SLAVE_RATIO_0     (DDR_PHY_BASE_ADDR + 0x0DC)
-#define DATA0_WR_DQS_SLAVE_RATIO_1     (DDR_PHY_BASE_ADDR + 0x0E0)
-
-#define DATA0_WRLVL_INIT_RATIO_0       (DDR_PHY_BASE_ADDR + 0x0F0)
-#define DATA0_WRLVL_INIT_RATIO_1       (DDR_PHY_BASE_ADDR + 0x0F4)
-
-#define DATA0_GATELVL_INIT_RATIO_0     (DDR_PHY_BASE_ADDR + 0x0FC)
-#define DATA0_GATELVL_INIT_RATIO_1     (DDR_PHY_BASE_ADDR + 0x100)
-
-#define DATA0_FIFO_WE_SLAVE_RATIO_0    (DDR_PHY_BASE_ADDR + 0x108)
-#define DATA0_FIFO_WE_SLAVE_RATIO_1    (DDR_PHY_BASE_ADDR + 0x10C)
-
-#define DATA0_WR_DATA_SLAVE_RATIO_0    (DDR_PHY_BASE_ADDR + 0x120)
-#define DATA0_WR_DATA_SLAVE_RATIO_1    (DDR_PHY_BASE_ADDR + 0x124)
-
-#define DATA0_DLL_LOCK_DIFF_0          (DDR_PHY_BASE_ADDR + 0x138)
-
-#define DATA0_RANK0_DELAYS_0           (DDR_PHY_BASE_ADDR + 0x134)
-#define DATA1_RANK0_DELAYS_0           (DDR_PHY_BASE_ADDR + 0x1D8)
-
-/* Temp placeholder for the values we want in the registers */
-#define EMIF_READ_LATENCY      0x04
-#define EMIF_TIM1              0x0666B3D6
-#define EMIF_TIM2              0x143731DA
-#define EMIF_TIM3              0x00000347
-#define EMIF_SDCFG             0x43805332
-#define EMIF_SDREF             0x0000081a
-#define EMIF_SDMGT             0x80000000
-#define EMIF_SDRAM             0x00004650
-#define EMIF_PHYCFG            0x2
-
-#define DDR2_DLL_LOCK_DIFF     0x0
-#define DDR2_RD_DQS            0x12
-#define DDR2_PHY_FIFO_WE       0x80
-
-#define DDR_PHY_RESET          (0x1 << 10)
-#define DDR_PHY_READY          (0x1 << 2)
-#define DDR2_RATIO             0x80
-#define CMD_FORCE              0x00
-#define CMD_DELAY              0x00
-
-#define DDR2_INVERT_CLKOUT     0x00
-#define DDR2_WR_DQS            0x00
-#define DDR2_PHY_WRLVL         0x00
-#define DDR2_PHY_GATELVL       0x00
-#define DDR2_PHY_WR_DATA       0x40
-#define PHY_RANK0_DELAY                0x01
-#define PHY_DLL_LOCK_DIFF      0x0
-#define DDR_IOCTRL_VALUE       0x18B
-
 #define VTP_CTRL_READY         (0x1 << 5)
 #define VTP_CTRL_ENABLE                (0x1 << 6)
 #define VTP_CTRL_LOCK_EN       (0x1 << 4)
 #define VTP_CTRL_START_EN      (0x1)
 
+#define DDR_IO_CTRL            (AM33XX_CTRL_BASE + 0x0E04)
+#define VTP0_CTRL_REG          (AM33XX_CTRL_BASE + 0x0E0C)
+#define DDR_CMD0_IOCTRL                (AM33XX_CTRL_BASE + 0x1404)
+#define DDR_CMD1_IOCTRL                (AM33XX_CTRL_BASE + 0x1408)
+#define DDR_CMD2_IOCTRL                (AM33XX_CTRL_BASE + 0x140C)
+#define DDR_DATA0_IOCTRL       (AM33XX_CTRL_BASE + 0x1440)
+#define DDR_DATA1_IOCTRL       (AM33XX_CTRL_BASE + 0x1444)
+
+#define MEM_TYPE_DDR2          2
+
+#define SUSP_VTP_CTRL_DDR2     0x10117
+#define SUSP_VTP_CTRL_DDR3     0x0
+
 #endif
index 5fd13b442c230b5a897abfa295812f041a91e393..b28fbd3fd5405b75ab91ba084118d458d7c9010e 100644 (file)
@@ -129,6 +129,7 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
  * wait
  * @rstctrl_reg: RM_RSTCTRL register address for this module
  * @shift: register bit shift corresponding to the reset line to deassert
+ * @st_shift: register bit shift corresponding to the reset line to deassert
  *
  * Some IPs like dsp, ipu or iva contain processors that require an HW
  * reset line to be asserted / deasserted in order to fully enable the
@@ -139,12 +140,14 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
  * -EINVAL upon an argument error, -EEXIST if the submodule was already out
  * of reset, or -EBUSY if the submodule did not exit reset promptly.
  */
-int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
-                                    u16 rstctrl_offs)
+int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part,
+                               s16 inst, u16 rstctrl_offs, u16 rstst_offs)
 {
        int c;
-       u32 mask = 1 << shift;
-       u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
+
+       rstst_offs = rstst_offs ? rstst_offs :
+                       (rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET);
+       st_shift = st_shift ? st_shift : shift;
 
        /* Check the current status to avoid de-asserting the line twice */
        if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
@@ -152,13 +155,13 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
                return -EEXIST;
 
        /* Clear the reset status by writing 1 to the status bit */
-       omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
+       omap4_prminst_rmw_inst_reg_bits(0xffffffff, (1 << st_shift), part, inst,
                                        rstst_offs);
        /* de-assert the reset control line */
-       omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
+       omap4_prminst_rmw_inst_reg_bits((1 << shift), 0, part, inst, rstctrl_offs);
        /* wait the status to be set */
-       omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
-                                                             rstst_offs),
+       omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift,
+                                       part, inst, rstst_offs),
                          MAX_MODULE_HARDRESET_WAIT, c);
 
        return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
index 9a44c68f5d398617d461fa9f2b833120fae59ef9..53a4b45a74fe34ad81308657ad6b7ac8c60d7a33 100644 (file)
@@ -27,7 +27,7 @@ extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
                                               u16 rstctrl_offs);
 extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
                                          u16 rstctrl_offs);
-extern int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
-                                           u16 rstctrl_offs);
+extern int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part,
+                               s16 inst, u16 rstctrl_offs, u16 rstst_offs);
 extern void __init omap44xx_prminst_init(void);
 #endif
index 69b49ea2497abf800de5c1abbecf9f2ee7ed4520..4af2e3a04284038d6f83728839a8b4bd5f428c3e 100644 (file)
 #include <asm/memory.h>
 #include <asm/assembler.h>
 #include <mach/io.h>
-#include <plat/emif.h>
-#include "cm33xx.h"
+#include <mach/board-am335xevm.h>
 
 #include <plat/emif.h>
 #include <plat/sram.h>
+#include <plat/gpio.h>
 
 #include "cm33xx.h"
 #include "pm33xx.h"
 #include "prm33xx.h"
 #include "control.h"
 
-/* We should probably pass in the virtual address of PRCM, Control and EMIF
- * along with the physical addresses
- * load it into the registers and then continue
+/*
+ * We should probably pass in the virtual address of PRCM, Control and EMIF
+ * along with the physical addresses, load it into the registers
+ * and then continue.
+ *
+ * This routine is executed from internal RAM and expects the memory type and
+ * other DDR configuration values which are different across different memory
+ * types to be passed in r0 _strictly_ in following order:
+ * 1) memory_type [r0]
+ * 2) susp_vtp_ctrl_val [r1]
+ * 3) evm_id [r2]
+ *
+ * The code loads these values taking r0 value as reference to the array in
+ * registers starting from r0, i,e memory_type goes to r0 and susp_vtp_ctrl_val
+ * goes to r1 and so on. These are then saved into memory locations before
+ * proceeding with the sleep sequence and hence registers r0,r1 can still be
+ * used in the rest of the sleep code.
+ *
+ * mem_type is used to decide different suspend-resume sequences for DDR2
+ * and DDR3.
  */
        .align 3
 ENTRY(am33xx_do_wfi)
        stmfd   sp!, {r4 - r11, lr}     @ save registers on stack
 
-       .macro  pll_bypass, name, clk_mode_addr, idlest_addr
+       .macro  pll_bypass, name, clk_mode_addr, idlest_addr, pll_mode
 pll_bypass_\name:
        ldr     r0, \clk_mode_addr
        ldr     r1, [r0]
+       str     r1, clk_mode_\pll_mode
        bic     r1, r1, #(7 << 0)
        orr     r1, r1, #0x5
        str     r1, [r0]
@@ -51,47 +69,198 @@ wait_pll_bypass_\name:
        bne     wait_pll_bypass_\name
        .endm
 
-       .macro  pll_lock, name, clk_mode_addr, idlest_addr
+       .macro  pll_lock, name, clk_mode_addr, idlest_addr, pll_mode
 pll_lock_\name:
        ldr     r0, \clk_mode_addr
-       ldr     r1, [r0]
-       bic     r1, r1, #(7 << 0)
-       orr     r1, r1, #0x7
+       ldr     r1, clk_mode_\pll_mode
        str     r1, [r0]
+       and     r1, r1, #0x7
+       cmp     r1, #0x7
+       bne     pll_mode_restored_\name
        ldr     r0, \idlest_addr
 wait_pll_lock_\name:
        ldr     r1, [r0]
-       tst     r1, #0x1
-       bne     wait_pll_lock_\name
+       ands    r1, #0x1
+       beq     wait_pll_lock_\name
+pll_mode_restored_\name:
+       nop
+       .endm
+
+       .macro  ddr_self_refresh, num
+ddr_self_refresh_\num:
+       add     r1, r0, #EMIF4_0_SDRAM_MGMT_CTRL
+       ldr     r2, [r1]
+       orr     r2, r2, #0xa0           @ a reasonable delay for entering SR
+       str     r2, [r1, #0]
+       str     r2, [r1, #4]            @ write to shadow register also
+
+       ldr     r2, ddr_start           @ do a dummy access to DDR
+       ldr     r3, [r2, #0]
+       ldr     r3, [r1, #0]
+       orr     r3, r3, #0x200          @ now set the LP MODE to Self-Refresh
+       str     r3, [r1, #0]
+
+       mov     r1, #0x1000             @ Give some time for system to enter SR
+wait_sr_\num:
+       subs    r1, r1, #1
+       bne     wait_sr_\num
+       .endm
+
+       .macro  wait_sdram_config ,num
+wait_sdram_config_\num:
+       mov     r0, #0x100
+wait_sc_\num:
+       subs    r0, r0 ,#1
+       bne     wait_sc_\num
        .endm
 
+       mov     r8, r0                  @ same arg list passed to us
+
        /* EMIF config for low power mode */
        ldr     r0, emif_addr_func
        blx     r0
 
        str     r0, emif_addr_virt
 
+       ldr     r0, gpio0_addr_func
+       blx     r0
+
+       str     r0, gpio0_addr_virt
+
+       /* This ensures isb */
+       ldr     r0, dcache_flush
+       blx     r0
+
+       /* Same as v7_flush_icache_all - saving a branch */
+       mov     r0, #0
+       mcr     p15, 0, r0, c7, c5, 0   @ I+BTB cache invalidate
+
+       ldm     r8, {r0-r2}             @ gather values passed
+
+       /* Save the values passed */
+       str     r0, mem_type
+       str     r1, susp_vtp_ctrl_val
+       str     r2, evm_id
+
+       ldr     r0, emif_addr_virt
+
+       /* Save EMIF configuration */
+       ldr     r1, [r0, #EMIF4_0_SDRAM_CONFIG]
+       str     r1, emif_sdcfg_val
+       ldr     r1, [r0, #EMIF4_0_SDRAM_REF_CTRL]
+       str     r1, emif_ref_ctrl_val
+       ldr     r1, [r0, #EMIF4_0_SDRAM_TIM_1]
+       str     r1, emif_timing1_val
+       ldr     r1, [r0, #EMIF4_0_SDRAM_TIM_2]
+       str     r1, emif_timing2_val
+       ldr     r1, [r0, #EMIF4_0_SDRAM_TIM_3]
+       str     r1, emif_timing3_val
+       ldr     r1, [r0, #EMIF4_0_SDRAM_MGMT_CTRL]
+       str     r1, emif_pmcr_val
+       ldr     r1, [r0, #EMIF4_0_SDRAM_MGMT_CTRL_SHADOW]
+       str     r1, emif_pmcr_shdw_val
+       ldr     r1, [r0, #EMIF4_0_ZQ_CONFIG]
+       str     r1, emif_zqcfg_val
+       ldr     r1, [r0, #EMIF4_0_DDR_PHY_CTRL_1]
+       str     r1, emif_rd_lat_val
+
        /* Ensure that all the writes to DDR leave the A8 */
        dsb
        dmb
        isb
 
-       add     r1, r0, #EMIF4_0_SDRAM_MGMT_CTRL
+       /* Different sleep sequences for DDR2 and DDR3 */
+       ldr     r6, mem_type
+       cmp     r6, #MEM_TYPE_DDR2
+       beq     ddr2_susp_seq
+
+       /* DDR3 suspend sequence */
+
+       /* For DDR3, hold DDR_RESET high via control module */
+       ldr     r2, virt_ddr_io_ctrl
+       ldr     r1, [r2]
+       mov     r3,#1
+       mov     r3,r3,lsl #31
+       orr     r1,r1,r3                @ set ddr3_rst_def_val
+       str     r1, [r2]
+
+       ddr_self_refresh        1
+
+       /* Disable VTT_Regulator on EVM-SK*/
+       ldr     r6, evm_id
+       cmp     r6, #EVM_SK
+       bne     no_gpio_toggle
+
+       /* Drive GPIO0_7 LOW */
+       ldr     r0, gpio0_addr_virt
+       ldr     r1, [r0, #OMAP4_GPIO_CLEARDATAOUT]
+       mov     r2, #(1 << 7)
+       str     r2, [r0, #OMAP4_GPIO_CLEARDATAOUT]
+
+no_gpio_toggle:
+       /* Weak pull down for macro DATA0 */
+       ldr     r1, virt_ddr_data0_ioctrl
+       ldr     r2, susp_io_pull_data
+       str     r2, [r1]
+
+       /* Weak pull down for macro DATA1 */
+       ldr     r1, virt_ddr_data1_ioctrl
+       ldr     r2, susp_io_pull_data
+       str     r2, [r1]
+
+       /* Weak pull down for macro CMD0 */
+       ldr     r1, virt_ddr_cmd0_ioctrl
+       ldr     r2, susp_io_pull_cmd1
+       str     r2, [r1]
+
+       /* Weak pull down for macro CMD1 */
+       ldr     r1, virt_ddr_cmd1_ioctrl
+       ldr     r2, susp_io_pull_cmd1
+       str     r2, [r1]
+
+       /*
+        * Weak pull down for macro CMD2
+        * exception: keep DDR_RESET pullup
+        */
+       ldr     r1, virt_ddr_cmd2_ioctrl
+       ldr     r2, susp_io_pull_cmd2
+       str     r2, [r1]
+
+       /* Disable VTP */
+       ldr     r1, virt_ddr_vtp_ctrl
+       ldr     r2, susp_vtp_ctrl_val
+       str     r2, [r1]
+
+       /* Put IO in mDDR (cmos) mode */
+       ldr     r0, virt_ddr_io_ctrl
+       ldr     r1, [r0]
+       mov     r2, #(0x1 << 28)
+       orr     r3,r2,r1
+       str     r3, [r0]
+
+       /* Disable EMIF at this point */
+       ldr     r1, virt_emif_clkctrl
        ldr     r2, [r1]
-       orr     r2, r2, #0xa0           @ a reasonable delay for entering SR
-       str     r2, [r1, #0]
+       bic     r2, r2, #(3 << 0)
+       str     r2, [r1]
 
-       ldr     r2, ddr_start           @ do a dummy access to DDR
-       ldr     r3, [r2, #0]
-       ldr     r3, [r1, #0]
-       orr     r3, r3, #0x200          @ now set the LP MODE to Self-Refresh
-       str     r3, [r1, #0]
-       str     r2, [r1, #4]            @ write to shadow register also
+       ldr     r1, virt_emif_clkctrl
+wait_emif_disable3:
+       ldr     r2, [r1]
+       ldr     r3, module_disabled_val
+       cmp     r2, r3
+       bne     wait_emif_disable3
 
-       mov     r1, #0x1000             @ Give some time for the system to enter SR
-wait_sr:
-       subs    r1, r1, #1
-       bne     wait_sr
+       /* Enable SRAM LDO ret mode */
+       ldr     r0, virt_sram_ldo_addr
+       ldr     r1, [r0]
+       orr     r1, #1
+       str     r1, [r0]
+
+       b       put_pll_bypass
+
+ddr2_susp_seq:
+       ddr_self_refresh        2
 
        /* Disable EMIF at this point */
        ldr     r1, virt_emif_clkctrl
@@ -106,39 +275,38 @@ wait_emif_disable:
        cmp     r2, r3
        bne     wait_emif_disable
 
+       /* DDR3 reset override and mDDR mode selection */
+       ldr     r0, virt_ddr_io_ctrl
+       mov     r1, #(0x9 << 28)
+       str     r1, [r0]
+
        /* Weak pull down for DQ, DM */
        ldr     r1, virt_ddr_io_pull1
-       ldr     r2, susp_io_pull
+       ldr     r2, susp_io_pull_data
        str     r2, [r1]
 
        ldr     r1, virt_ddr_io_pull2
-       ldr     r2, susp_io_pull
+       ldr     r2, susp_io_pull_data
        str     r2, [r1]
 
-       /* Disable VTP with N & P = 0x1 */
+       /* Disable VTP */
        ldr     r1, virt_ddr_vtp_ctrl
        ldr     r2, susp_vtp_ctrl_val
        str     r2, [r1]
 
-       /* IO to work in mDDR mode */
-       ldr     r0, virt_ddr_io_ctrl
-       ldr     r1, [r0]
-       mov     r2, #1
-       mov     r3, r2, lsl #28
-       str     r3, [r0]
-
        /* Enable SRAM LDO ret mode */
        ldr     r0, virt_sram_ldo_addr
        ldr     r1, [r0]
        orr     r1, #1
        str     r1, [r0]
 
+put_pll_bypass:
        /* Put the PLLs in bypass mode */
-       pll_bypass      core, virt_core_clk_mode, virt_core_idlest
-       pll_bypass      ddr, virt_ddr_clk_mode, virt_ddr_idlest
-       pll_bypass      disp, virt_disp_clk_mode, virt_disp_idlest
-       pll_bypass      per, virt_per_clk_mode, virt_per_idlest
-       pll_bypass      mpu, virt_mpu_clk_mode, virt_mpu_idlest
+       pll_bypass      core, virt_core_clk_mode, virt_core_idlest, core_val
+       pll_bypass      ddr, virt_ddr_clk_mode, virt_ddr_idlest, ddr_val
+       pll_bypass      disp, virt_disp_clk_mode, virt_disp_idlest, disp_val
+       pll_bypass      per, virt_per_clk_mode, virt_per_idlest, per_val
+       pll_bypass      mpu, virt_mpu_clk_mode, virt_mpu_idlest, mpu_val
 
        dsb
        dmb
@@ -156,15 +324,23 @@ wait_emif_disable:
        nop
        nop
        nop
+       nop
+       nop
 
        /* We come here in case of an abort */
 
        /* Relock the PLLs */
-       pll_lock        mpu_abt, virt_mpu_clk_mode, virt_mpu_idlest
-       pll_lock        per_abt, virt_per_clk_mode, virt_per_idlest
-       pll_lock        disp_abt, virt_disp_clk_mode, virt_disp_idlest
-       pll_lock        ddr_abt, virt_ddr_clk_mode, virt_ddr_idlest
-       pll_lock        core_abt, virt_core_clk_mode, virt_core_idlest
+       pll_lock        mpu_abt, virt_mpu_clk_mode, virt_mpu_idlest, mpu_val
+       pll_lock        per_abt, virt_per_clk_mode, virt_per_idlest, per_val
+       pll_lock        disp_abt, virt_disp_clk_mode, virt_disp_idlest, disp_val
+       pll_lock        ddr_abt, virt_ddr_clk_mode, virt_ddr_idlest, ddr_val
+       pll_lock        core_abt, virt_core_clk_mode, virt_core_idlest, core_val
+
+       ldr     r6, mem_type
+       cmp     r6, #MEM_TYPE_DDR2
+       beq     ddr2_resume_seq_abt
+
+       /* DDR3 resume path */
 
        /* Disable SRAM LDO ret mode */
        ldr     r0, virt_sram_ldo_addr
@@ -172,22 +348,111 @@ wait_emif_disable:
        bic     r1, #1
        str     r1, [r0]
 
-       /* IO to work in DDR mode */
+       /* Enable EMIF */
+       ldr     r1, virt_emif_clkctrl
+       mov     r2, #0x2
+       str     r2, [r1]
+wait_emif_enable3:
+       ldr     r3, [r1]
+       cmp     r2, r3
+       bne     wait_emif_enable3
+
+       /* Take out IO of mDDR mode */
        ldr     r0, virt_ddr_io_ctrl
        ldr     r1, [r0]
-       mov     r2, #0x0
-       mov     r3, r2, lsl #28
-       str     r3, [r0]
+       bic     r1, r1, #(1 << 28)
+       str     r1, [r0]
+
+       /* Enable VTP */
+config_vtp_abt3:
+       ldr     r0, virt_ddr_vtp_ctrl
+       ldr     r1, [r0]
+       mov     r2, #0x0        @ clear the register
+       str     r2, [r0]
+       mov     r2, #0x6        @ write the filter value
+       str     r2, [r0]
+
+       ldr     r1, [r0]
+       ldr     r2, vtp_enable  @ set the enable bit
+       orr     r2, r2, r1
+       str     r2, [r0]
+
+       ldr     r1, [r0]        @ toggle the CLRZ bit
+       bic     r1, #1
+       str     r1, [r0]
+
+       ldr     r1, [r0]
+       orr     r1, #1
+       str     r1, [r0]
+
+poll_vtp_ready_abt3:
+       ldr     r1, [r0]        @ poll for VTP ready
+       tst     r1, #(1 << 5)
+       beq     poll_vtp_ready_abt3
+
+       /*      Disable the pull for CMD2 */
+       ldr     r1, virt_ddr_cmd2_ioctrl
+       ldr     r2, resume_io_pull_cmd
+       str     r2, [r1]
+       /*      Disable the pull for CMD1 */
+       ldr     r1, virt_ddr_cmd1_ioctrl
+       ldr     r2, resume_io_pull_cmd
+       str     r2, [r1]
+       /*      Disable the pull for CMD0 */
+       ldr     r1, virt_ddr_cmd0_ioctrl
+       ldr     r2, resume_io_pull_cmd
+       str     r2, [r1]
+       /*      Disable the pull for DATA1 */
+       ldr     r1, virt_ddr_data1_ioctrl
+       ldr     r2, resume_io_pull_data
+       str     r2, [r1]
+       /*      Disable the pull for DATA0 */
+       ldr     r1, virt_ddr_data0_ioctrl
+       ldr     r2, resume_io_pull_data
+       str     r2, [r1]
+
+       wait_sdram_config       1
+
+       /* Enable VTT_Regulator on EVM-SK */
+       ldr     r6, evm_id
+       cmp     r6, #EVM_SK
+       bne     no_gpio_toggle2
+
+       /* Drive GPIO0_7 HIGH */
+       ldr     r0, gpio0_addr_virt
+       ldr     r1, [r0, #OMAP4_GPIO_SETDATAOUT]
+       mov     r2, #(1 << 7)
+       str     r2, [r0, #OMAP4_GPIO_SETDATAOUT]
+
+no_gpio_toggle2:
+       b       emif_self_refresh_dis
+
+       /* DDR2 resume path */
+ddr2_resume_seq_abt:
+       /* Disable SRAM LDO ret mode */
+       ldr     r0, virt_sram_ldo_addr
+       ldr     r1, [r0]
+       bic     r1, #1
+       str     r1, [r0]
 
        /* Restore the pull for DQ, DM */
        ldr     r1, virt_ddr_io_pull1
-       ldr     r2, resume_io_pull1
+       ldr     r2, resume_io_pull_data
        str     r2, [r1]
 
        ldr     r1, virt_ddr_io_pull2
-       ldr     r2, resume_io_pull2
+       ldr     r2, resume_io_pull_data
        str     r2, [r1]
 
+       /* Enable EMIF */
+       ldr     r1, virt_emif_clkctrl
+       mov     r2, #0x2
+       str     r2, [r1]
+wait_emif_enable:
+       ldr     r3, [r1]
+       cmp     r2, r3
+       bne     wait_emif_enable
+
        /* Enable VTP */
 config_vtp_abt:
        ldr     r0, virt_ddr_vtp_ctrl
@@ -215,45 +480,54 @@ poll_vtp_ready_abt:
        tst     r1, #(1 << 5)
        beq     poll_vtp_ready_abt
 
-       /* Enable EMIF */
-       ldr     r1, virt_emif_clkctrl
-       mov     r2, #0x2
-       str     r2, [r1]
-wait_emif_enable:
-       ldr     r3, [r1]
-       cmp     r2, r3
-       bne     wait_emif_enable
+       /* DDR3 reset override and mDDR mode clear */
+       ldr     r0, virt_ddr_io_ctrl
+       mov     r1, #0
+       str     r1, [r0]
 
+emif_self_refresh_dis:
        /* Disable EMIF self-refresh */
        ldr     r0, emif_addr_virt
        add     r0, r0, #EMIF4_0_SDRAM_MGMT_CTRL
        ldr     r1, [r0]
-       bic     r1, r1, #(0x7 << 7)
+       bic     r1, r1, #(0x7 << 8)
        str     r1, [r0]
+       str     r1, [r0, #4]
+
+/*
+ * A write to SDRAM CONFIG register triggers
+ * an init sequence and hence it must be done
+ * at the end
+ */
+       ldr r0, emif_addr_virt
+       add r0, r0, #EMIF4_0_SDRAM_CONFIG
+       ldr r4, emif_sdcfg_val
+       str r4, [r0]
+
+       mov r0, #0x2000
+wait_loop4:
+       subs   r0, r0, #1
+       bne wait_loop4
 
        mov     r0, #7
        ldmfd   sp!, {r4 - r11, pc}     @ restore regs and return
 
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
-       nop
+ENTRY(am33xx_resume_offset)
+       .word . - am33xx_do_wfi
 
+ENTRY(am33xx_resume_from_deep_sleep)
        /* Take the PLLs out of LP_BYPASS */
-       pll_lock        mpu, phys_mpu_clk_mode, phys_mpu_idlest
-       pll_lock        per, phys_per_clk_mode, phys_per_idlest
-       pll_lock        disp, phys_disp_clk_mode, phys_disp_idlest
-       pll_lock        ddr, phys_ddr_clk_mode, phys_ddr_idlest
-       pll_lock        core, phys_core_clk_mode, phys_core_idlest
+       pll_lock        mpu, phys_mpu_clk_mode, phys_mpu_idlest, mpu_val
+       pll_lock        per, phys_per_clk_mode, phys_per_idlest, per_val
+       pll_lock        disp, phys_disp_clk_mode, phys_disp_idlest, disp_val
+       pll_lock        ddr, phys_ddr_clk_mode, phys_ddr_idlest, ddr_val
+       pll_lock        core, phys_core_clk_mode, phys_core_idlest, core_val
+
+       ldr     r6, mem_type
+       cmp     r6, #MEM_TYPE_DDR2
+       beq     ddr2_resume_seq
+
+       /* DDR3 resume path */
 
        /* Disable SRAM LDO ret mode */
        ldr     r0, phys_sram_ldo_addr
@@ -261,43 +535,95 @@ wait_emif_enable:
        bic     r1, #1
        str     r1, [r0]
 
-       /* Restore the pull for DQ, DM */
-       ldr     r1, phys_ddr_io_pull1
-       ldr     r2, resume_io_pull1
-       str     r2, [r1]
+       /* TODO: Put EMIF enable here */
 
-       ldr     r1, phys_ddr_io_pull2
-       ldr     r2, resume_io_pull2
-       str     r2, [r1]
+       /* Take out IO of mDDR mode */
+       ldr     r0, phys_ddr_io_ctrl
+       ldr     r1, [r0]
+       bic     r1, r1, #(1 << 28)
+       str     r1, [r0]
+
+config_vtp3:
+       ldr     r0, phys_ddr_vtp_ctrl
+       ldr     r1, [r0]
+       mov     r2, #0x0        @ clear the register
+       str     r2, [r0]
+       mov     r2, #0x6        @ write the filter value
+       str     r2, [r0]
 
-       /* Disable EMIF self-refresh */
-       ldr     r0, emif_phys_addr
-       add     r0, r0, #EMIF4_0_SDRAM_MGMT_CTRL
        ldr     r1, [r0]
-       bic     r1, r1, #(0x7 << 7)
+       ldr     r2, vtp_enable  @ set the enable bit
+       orr     r2, r2, r1
+       str     r2, [r0]
+
+       ldr     r1, [r0]        @ toggle the CLRZ bit
+       bic     r1, #1
        str     r1, [r0]
 
-       /* Take out IO of mDDR mode */
-       ldr     r0, phys_ddr_io_ctrl
        ldr     r1, [r0]
-       bic     r1, r1, #28
+       orr     r1, #1
        str     r1, [r0]
+poll_vtp_ready3:
+       ldr     r1, [r0]        @ poll for VTP ready
+       tst     r1, #(1 << 5)
+       beq     poll_vtp_ready3
 
-/*
- * Instead of harcoding the EMIF and DDR PHY related settings
- * in this file, the sane thing to do would have been to backup
- * the register contents during suspend and restore it back in
- * the resume path. However, due to the Si errata related to
- * DDR PHY registers, these registers are read-only. So, we'll
- * need to hardcode atleast the DDR PHY configuration over here.
- * We _could_ back up the EMIF registers but in order to be
- * consistent with the DDR setup procedure we skip this for now.
- * The person updating the DDR PHY config values is expected
- * to update the EMIF config values also.
- */
+       /*      Disable the pull for CMD2 */
+       ldr     r1, phys_ddr_cmd2_ioctrl
+       ldr     r2, resume_io_pull_cmd
+       str     r2, [r1]
+       /*      Disable the pull for CMD1 */
+       ldr     r1, phys_ddr_cmd1_ioctrl
+       ldr     r2, resume_io_pull_cmd
+       str     r2, [r1]
+       /*      Disable the pull for CMD0 */
+       ldr     r1, phys_ddr_cmd0_ioctrl
+       ldr     r2, resume_io_pull_cmd
+       str     r2, [r1]
+       /*      Disable the pull for DATA1 */
+       ldr     r1, phys_ddr_data1_ioctrl
+       ldr     r2, resume_io_pull_data
+       str     r2, [r1]
+       /*      Disable the pull for DATA0 */
+       ldr     r1, phys_ddr_data0_ioctrl
+       ldr     r2, resume_io_pull_data
+       str     r2, [r1]
+
+       wait_sdram_config       2
+
+       /* Enable VTT_Regulator on EVM-SK */
+       ldr     r6, evm_id
+       cmp     r6, #EVM_SK
+       bne     no_gpio_toggle3
+
+       /* Drive GPIO0_7 HIGH */
+       ldr     r0, gpio0_phys_addr
+       ldr     r1, [r0, #OMAP4_GPIO_SETDATAOUT]
+       mov     r2, #(1 << 7)
+       str     r2, [r0, #OMAP4_GPIO_SETDATAOUT]
+
+no_gpio_toggle3:
+       b       config_emif_timings
+
+       /* DDR2 resume path */
+ddr2_resume_seq:
+       /* Disable SRAM LDO ret mode */
+       ldr     r0, phys_sram_ldo_addr
+       ldr     r1, [r0]
+       bic     r1, #1
+       str     r1, [r0]
+
+       /* Restore the pull for DQ, DM */
+       ldr     r1, phys_ddr_io_pull1
+       ldr     r2, resume_io_pull_data
+       str     r2, [r1]
+
+       ldr     r1, phys_ddr_io_pull2
+       ldr     r2, resume_io_pull_data
+       str     r2, [r1]
 
 config_vtp:
-       ldr     r0, vtp0_addr
+       ldr     r0, phys_ddr_vtp_ctrl
        ldr     r1, [r0]
        mov     r2, #0x0        @ clear the register
        str     r2, [r0]
@@ -322,233 +648,58 @@ poll_vtp_ready:
        tst     r1, #(1 << 5)
        beq     poll_vtp_ready
 
-cmd_macro_config:
-       ldr     r0, ddr_phy_base
-       ldr     r1, [r0]
-       ldr     r2, ddr2_ratio_val
-       mov     r3, r2
-       @ TODO: Need to use proper variable here
-       mov     r4, #0
-       str     r3, [r0, #28]   @cmd0
-       str     r4, [r0, #32]
-       str     r4, [r0, #36]
-       str     r4, [r0, #40]
-       str     r4, [r0, #44]
-       str     r3, [r0, #80]   @cmd1
-       str     r4, [r0, #84]
-       str     r4, [r0, #88]
-       str     r4, [r0, #92]
-       str     r4, [r0, #96]
-       str     r3, [r0, #132]  @cmd2
-       str     r4, [r0, #136]
-       str     r4, [r0, #140]
-       str     r4, [r0, #144]
-       str     r4, [r0, #148]
-
-       mov     r3, #0x0
-       bl      data_macro_config
-       mov     r3, #0xa4
-       bl      data_macro_config
-       b       setup_rank_delays
-
-data_macro_config:
-       ldr     r0, ddr_phy_base
-       add     r0, r0, r3
-rd_dqs:
-       ldr     r1, data0_rd_dqs_slave_ratio0_val
-       mov     r2, r1
-       /* shift by 30, 20, 10 and orr */
-       mov     r5, r2, lsl #10
-       mov     r6, r2, lsl #20
-       mov     r7, r2, lsl #30
-       orr     r2, r2, r5
-       orr     r2, r2, r6
-       orr     r2, r2, r7
-       /* Done with crazy bit ops. store it now */
-       str     r2, [r0, #200]
-       ldr     r1, data0_rd_dqs_slave_ratio1_val
-       mov     r2, r1
-       mov     r5, r2, lsr #2
-       mov     r2, r5
-       str     r2, [r0, #204]
-wr_dqs:
-       ldr     r1, data0_wr_dqs_slave_ratio0_val
-       mov     r2, r1
-       /* shift by 30, 20, 10 and orr */
-       mov     r5, r2, lsl #10
-       mov     r6, r2, lsl #20
-       mov     r7, r2, lsl #30
-       orr     r2, r2, r5
-       orr     r2, r2, r6
-       orr     r2, r2, r7
-       /* Done with crazy bit ops. store it now */
-       str     r2, [r0, #220]
-       ldr     r1, data0_wr_dqs_slave_ratio1_val
-       mov     r2, r1
-       mov     r5, r2, lsr #2
-       mov     r2, r5
-       str     r2, [r0, #224]
-wr_lvl:
-       ldr     r1, data0_wr_lvl_init_ratio0_val
-       mov     r2, r1
-       /* shift by 30, 20, 10 and orr */
-       mov     r5, r2, lsl #10
-       mov     r6, r2, lsl #20
-       mov     r7, r2, lsl #30
-       orr     r2, r2, r5
-       orr     r2, r2, r6
-       orr     r2, r2, r7
-       /* Done with crazy bit ops. store it now */
-       str     r2, [r0, #240]
-       ldr     r1, data0_wr_lvl_init_ratio1_val
-       mov     r2, r1
-       mov     r5, r2, lsr #2
-       mov     r2, r5
-       str     r2, [r0, #244]
-gate_lvl:
-       ldr     r1, data0_gate_lvl_init_ratio0_val
-       mov     r2, r1
-       /* shift by 30, 20, 10 and orr */
-       mov     r5, r2, lsl #10
-       mov     r6, r2, lsl #20
-       mov     r7, r2, lsl #30
-       orr     r2, r2, r5
-       orr     r2, r2, r6
-       orr     r2, r2, r7
-       /* Done with crazy bit ops. store it now */
-       str     r2, [r0, #248]
-       ldr     r1, data0_gate_lvl_init_ratio1_val
-       mov     r2, r1
-       mov     r5, r2, lsr #2
-       mov     r2, r5
-       str     r2, [r0, #256]
-we_slv:
-       ldr     r1, data0_wr_lvl_slave_ratio0_val
-       mov     r2, r1
-       /* shift by 30, 20, 10 and orr */
-       mov     r5, r2, lsl #10
-       mov     r6, r2, lsl #20
-       mov     r7, r2, lsl #30
-       orr     r2, r2, r5
-       orr     r2, r2, r6
-       orr     r2, r2, r7
-       /* Done with crazy bit ops. store it now */
-       str     r2, [r0, #264]
-       ldr     r1, data0_wr_lvl_slave_ratio1_val
-       mov     r2, r1
-       mov     r5, r2, lsr #2
-       mov     r2, r5
-       str     r2, [r0, #268]
-wr_data:
-       ldr     r1, data0_wr_data_slave_ratio0_val
-       mov     r2, r1
-       /* shift by 30, 20, 10 and orr */
-       mov     r5, r2, lsl #10
-       mov     r6, r2, lsl #20
-       mov     r7, r2, lsl #30
-       orr     r2, r2, r5
-       orr     r2, r2, r6
-       orr     r2, r2, r7
-       /* Done with crazy bit ops. store it now */
-       str     r2, [r0, #288]
-       ldr     r1, data0_wr_data_slave_ratio1_val
-       mov     r2, r1
-       mov     r5, r2, lsr #2
-       mov     r2, r5
-       str     r2, [r0, #292]
-dll_lock:
-       ldr     r1, data0_dll_lock_diff_val
-       mov     r2, r1
-       str     r2, [r0, #312]
-
-setup_rank_delays:
-       ldr     r1, data0_rank0_delay0_val
-       mov     r2, r1
-       str     r2, [r0, #308]
-       ldr     r1, data1_rank0_delay1_val
-       mov     r2, r1
-       str     r2, [r0, #472]
-
-setup_io_ctrl:
-       ldr     r0, control_base
-       ldr     r1, ddr_ioctrl_val
-       mov     r2, r1
-       ldr     r4, ddr_cmd_offset
-       mov     r3, r4
-       str     r2, [r0, r3]    @cmd0 0x1404
-       add     r3, r3, #4
-       str     r2, [r0, r3]    @cmd1 0x1408
-       add     r3, r3, #4
-       str     r2, [r0, r3]    @cmd2 0x140c
-       ldr     r4, ddr_data_offset
-       mov     r3, r4
-       str     r2, [r0, r3]    @data0 0x1440
-       add     r3, r3, #4
-       str     r2, [r0, r3]    @data1 0x1444
-
-misc_config:
-       ldr     r1, ddr_io_ctrl_addr
-       ldr     r2, [r1]
-       and     r2, #0xefffffff
-       str     r2, [r1]
-       ldr     r1, ddr_cke_addr
-       ldr     r2, [r1]
-       orr     r2, #0x00000001
-       str     r2, [r1]
+       /* DDR3 reset override and mDDR mode clear */
+       ldr     r0, phys_ddr_io_ctrl
+       mov     r1, #0
+       str     r1, [r0]
 
 config_emif_timings:
-       mov     r3, #1275068416 @ 0x4c000000
-disable_sr:
-       mov     r4, #0
-       str     r4, [r3, #56]   @ 0x38
+       ldr     r3, emif_phys_addr
        ldr     r4, emif_rd_lat_val
-       mov     r2, r4
 rd_lat:
-       str     r2, [r3, #228]  @ 0xe4
-       str     r2, [r3, #232]  @ 0xe8
-       str     r2, [r3, #236]  @ 0xec
+       str     r4, [r3, #EMIF4_0_DDR_PHY_CTRL_1]
+       str     r4, [r3, #EMIF4_0_DDR_PHY_CTRL_1_SHADOW]
 timing1:
        ldr     r4, emif_timing1_val
-       mov     r2, r4
-       str     r2, [r3, #24]
-       str     r2, [r3, #28]
+       str     r4, [r3, #EMIF4_0_SDRAM_TIM_1]
+       str     r4, [r3, #EMIF4_0_SDRAM_TIM_1_SHADOW]
 timing2:
        ldr     r4, emif_timing2_val
-       mov     r2, r4
-       str     r2, [r3, #32]
-       str     r2, [r3, #36]   @ 0x24
+       str     r4, [r3, #EMIF4_0_SDRAM_TIM_2]
+       str     r4, [r3, #EMIF4_0_SDRAM_TIM_2_SHADOW]
 timing3:
        ldr     r4, emif_timing3_val
-       mov     r2, r4
-       str     r2, [r3, #40]   @ 0x28
-       str     r2, [r3, #44]   @ 0x2c
-sdcfg1:
-       ldr     r4, emif_sdcfg_val
-       mov     r2, r4
-       str     r2, [r3, #8]
-       str     r2, [r3, #12]
-ref_ctrl_const:
-       ldr     r4, emif_ref_ctrl_const_val
-       mov     r2, r4
-       str     r2, [r3, #16]
-       str     r2, [r3, #20]
-
-       /* GEL had a loop with init value of 5000 */
-       mov     r0, #0x1000
-wait_loop1:
-       subs    r0, r0, #1
-       bne     wait_loop1
-
-ref_ctrl_actual:
+       str     r4, [r3, #EMIF4_0_SDRAM_TIM_3]
+       str     r4, [r3, #EMIF4_0_SDRAM_TIM_3_SHADOW]
+sdram_ref_ctrl:
        ldr     r4, emif_ref_ctrl_val
-       mov     r2, r4
-       str     r2, [r3, #16]
-       str     r2, [r3, #20]
-sdcfg2:
+       str     r4, [r3, #EMIF4_0_SDRAM_REF_CTRL]
+       str     r4, [r3, #EMIF4_0_SDRAM_REF_CTRL_SHADOW]
+pmcr:
+       ldr     r4, emif_pmcr_val
+       str     r4, [r3, #EMIF4_0_SDRAM_MGMT_CTRL]
+pmcr_shdw:
+       ldr     r4, emif_pmcr_shdw_val
+       str     r4, [r3, #EMIF4_0_SDRAM_MGMT_CTRL_SHADOW]
+
+       /*
+        * Output impedence calib needed only for DDR3
+        * but since the initial state of this will be
+        * disabled for DDR2 no harm in restoring the
+        * old configuration
+        */
+zqcfg:
+       ldr     r4, emif_zqcfg_val
+       str     r4, [r3, #EMIF4_0_ZQ_CONFIG]
+
+       /*
+        * A write to SDRAM CONFIG register triggers
+        * an init sequence and hence it must be done
+        * at the end
+        */
+sdcfg:
        ldr     r4, emif_sdcfg_val
-       mov     r2, r4
-       str     r2, [r3, #8]
-       str     r2, [r3, #12]
+       str     r4, [r3, #EMIF4_0_SDRAM_CONFIG]
 
        /* Back from la-la-land. Kill some time for sanity to settle in */
        mov     r0, #0x1000
@@ -564,6 +715,8 @@ ENTRY(am33xx_resume_vector)
  * Local variables
  */
 
+dcache_flush:
+       .word   v7_flush_dcache_all
 resume_addr:
        .word   cpu_resume - PAGE_OFFSET + 0x80000000
 
@@ -572,10 +725,13 @@ emif_addr_func:
 emif_phys_addr:
        .word   AM33XX_EMIF0_BASE
 
-emif_pm_ctrl:
-       .word EMIF4_0_SDRAM_MGMT_CTRL
+gpio0_addr_func:
+       .word   am33xx_get_gpio0_base
+gpio0_phys_addr:
+       .word   AM33XX_GPIO0_BASE
+
 ddr_start:
-       .word PAGE_OFFSET
+       .word   PAGE_OFFSET
 
 virt_mpu_idlest:
        .word   AM33XX_CM_IDLEST_DPLL_MPU
@@ -638,61 +794,6 @@ module_disabled_val:
        .word   0x30000
 
 /* DDR related stuff */
-vtp0_addr:
-       .word   VTP0_CTRL_REG
-vtp_enable:
-       .word   VTP_CTRL_ENABLE
-vtp_start_en:
-       .word   VTP_CTRL_START_EN
-vtp_ready:
-       .word   VTP_CTRL_READY
-
-ddr_phy_base:
-       .word   DDR_PHY_BASE_ADDR
-ddr2_ratio_val:
-       .word   DDR2_RATIO
-data0_rd_dqs_slave_ratio0_val:
-       .word   DDR2_RD_DQS
-data0_rd_dqs_slave_ratio1_val:
-       .word   DDR2_RD_DQS
-data0_wr_dqs_slave_ratio0_val:
-       .word   DDR2_WR_DQS
-data0_wr_dqs_slave_ratio1_val:
-       .word   DDR2_WR_DQS
-data0_wr_lvl_init_ratio0_val:
-       .word   DDR2_PHY_WRLVL
-data0_wr_lvl_init_ratio1_val:
-       .word   DDR2_PHY_WRLVL
-data0_gate_lvl_init_ratio0_val:
-       .word   DDR2_PHY_GATELVL
-data0_gate_lvl_init_ratio1_val:
-       .word   DDR2_PHY_GATELVL
-data0_wr_lvl_slave_ratio0_val:
-       .word   DDR2_PHY_FIFO_WE
-data0_wr_lvl_slave_ratio1_val:
-       .word   DDR2_PHY_FIFO_WE
-data0_wr_data_slave_ratio0_val:
-       .word   DDR2_PHY_WR_DATA
-data0_wr_data_slave_ratio1_val:
-       .word   DDR2_PHY_WR_DATA
-data0_dll_lock_diff_val:
-       .word   PHY_DLL_LOCK_DIFF
-
-data0_rank0_delay0_val:
-       .word   PHY_RANK0_DELAY
-data1_rank0_delay1_val:
-       .word   PHY_RANK0_DELAY
-
-control_base:
-       .word   AM33XX_CTRL_BASE
-ddr_io_ctrl_addr:
-       .word   DDR_IO_CTRL
-ddr_ioctrl_val:
-       .word   0x18B
-ddr_cmd_offset:
-       .word   0x1404
-ddr_data_offset:
-       .word   0x1440
 virt_ddr_io_ctrl:
        .word   AM33XX_CTRL_REGADDR(0x0E04)
 phys_ddr_io_ctrl:
@@ -701,6 +802,29 @@ virt_ddr_vtp_ctrl:
        .word   AM33XX_CTRL_REGADDR(0x0E0C)
 phys_ddr_vtp_ctrl:
        .word   VTP0_CTRL_REG
+virt_ddr_cmd0_ioctrl:
+       .word   AM33XX_CTRL_REGADDR(0x1404)
+phys_ddr_cmd0_ioctrl:
+       .word   DDR_CMD0_IOCTRL
+virt_ddr_cmd1_ioctrl:
+       .word   AM33XX_CTRL_REGADDR(0x1408)
+phys_ddr_cmd1_ioctrl:
+       .word   DDR_CMD1_IOCTRL
+virt_ddr_cmd2_ioctrl:
+       .word   AM33XX_CTRL_REGADDR(0x140C)
+phys_ddr_cmd2_ioctrl:
+       .word   DDR_CMD2_IOCTRL
+virt_ddr_data0_ioctrl:
+       .word   AM33XX_CTRL_REGADDR(0x1440)
+phys_ddr_data0_ioctrl:
+       .word   DDR_DATA0_IOCTRL
+virt_ddr_data1_ioctrl:
+       .word   AM33XX_CTRL_REGADDR(0x1444)
+phys_ddr_data1_ioctrl:
+       .word   DDR_DATA1_IOCTRL
+vtp_enable:
+       .word   VTP_CTRL_ENABLE
+
 virt_ddr_io_pull1:
        .word   AM33XX_CTRL_REGADDR(0x1440)
 phys_ddr_io_pull1:
@@ -714,38 +838,58 @@ virt_ddr_io_pull3:
 phys_ddr_io_pull3:
        .word   AM33XX_CTRL_BASE + (0x1448)
 
-ddr_cke_addr:
-       .word   DDR_CKE_CTRL
+susp_io_pull_data:
+       .word   0x3FF00003
+susp_io_pull_cmd1:
+       .word   0xFFE0018B
+susp_io_pull_cmd2:
+       .word   0xFFA0098B
+
+resume_io_pull_data:
+       .word   0x18B
+resume_io_pull_cmd:
+       .word   0x18B
+
+susp_vtp_ctrl_val:
+       .word   0xDEADBEEF
+mem_type:
+       .word   0xDEADBEEF
+evm_id:
+       .word   0xDEADBEEF
+emif_addr_virt:
+       .word   0xDEADBEEF
+gpio0_addr_virt:
+       .word   0xDEADBEEF
 emif_rd_lat_val:
-       .word   EMIF_READ_LATENCY
+       .word   0xDEADBEEF
 emif_timing1_val:
-       .word   EMIF_TIM1
+       .word   0xDEADBEEF
 emif_timing2_val:
-       .word   EMIF_TIM2
+       .word   0xDEADBEEF
 emif_timing3_val:
-       .word   EMIF_TIM3
+       .word   0xDEADBEEF
 emif_sdcfg_val:
-       .word   EMIF_SDCFG
-emif_ref_ctrl_const_val:
-       .word   0x4650
+       .word   0xDEADBEEF
 emif_ref_ctrl_val:
-       .word   EMIF_SDREF
-
-susp_io_pull:
-       .word   0x3FF00003
-resume_io_pull1:
-       .word   0x18B
-resume_io_pull2:
-       .word   0x18B
-dyn_pd_val:
-       .word   0x100000
-susp_sdram_config:
-       .word   0x40805332
-susp_vtp_ctrl_val:
-       .word   0x10117
-emif_addr_virt:
+       .word   0xDEADBEEF
+emif_zqcfg_val:
+       .word   0xDEADBEEF
+emif_pmcr_val:
+       .word   0xDEADBEEF
+emif_pmcr_shdw_val:
        .word   0xDEADBEEF
 
+/* PLL CLKMODE before suspend */
+clk_mode_mpu_val:
+       .word   0xDEADBEEF
+clk_mode_per_val:
+       .word   0xDEADBEEF
+clk_mode_disp_val:
+       .word   0xDEADBEEF
+clk_mode_ddr_val:
+       .word   0xDEADBEEF
+clk_mode_core_val:
+       .word   0xDEADBEEF
 
 ENTRY(am33xx_do_wfi_sz)
        .word   . - am33xx_do_wfi
index 734009a93857bd70f7dcdca8831c26b25fe62d62..33f17f2d8f8d2821324a7b511e4d915176c2d1b3 100644 (file)
@@ -43,6 +43,27 @@ config OMAP_DEBUG_LEDS
        depends on OMAP_DEBUG_DEVICES
        default y if LEDS_CLASS
 
+config AM33XX_SMARTREFLEX
+       bool "AM33XX SmartReflex support"
+       depends on (SOC_OMAPAM33XX) && PM
+       help
+         Say Y if you want to enable SmartReflex.
+
+         SmartReflex can perform continuous dynamic voltage
+         scaling around the nominal operating point voltage
+         according to silicon characteristics and operating
+         conditions. Enabling SmartReflex reduces active power
+         consumption.
+
+         Please note, that by default SmartReflex is enabled.
+          To disable the automatic voltage compensation for 
+          vdd mpu and vdd core from user space, user must 
+          write 1 to /debug/smartreflex/autocomp.
+
+         Optionally autocompensation can be disabled in the kernel
+         by default during system init via the enable_on_init flag
+         which an be passed as platform data to the smartreflex driver.
+
 config OMAP_SMARTREFLEX
        bool "SmartReflex support"
        depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
index 19719329a47b0fb96a4b75e42f8103f505c00c84..52720b4df44cc43f0547fdeae93fb3200915d581 100644 (file)
@@ -26,6 +26,7 @@
 #include <plat/mmc.h>
 #include <plat/menelaus.h>
 #include <plat/omap44xx.h>
+#include <plat/am33xx.h>
 
 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
        defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
@@ -104,6 +105,28 @@ static void omap_init_rng(void)
 {
        (void) platform_device_register(&omap_rng_device);
 }
+#elif defined(CONFIG_HW_RANDOM_OMAP4) || defined(CONFIG_HW_RANDOM_OMAP4_MODULE)
+
+static struct resource rng_resources[] = {
+       {
+               .start          = AM33XX_RNG_BASE,
+               .end            = AM33XX_RNG_BASE + 0x1FFC,
+               .flags          = IORESOURCE_MEM,
+       },
+};
+
+static struct platform_device omap4_rng_device = {
+       .name           = "omap4_rng",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(rng_resources),
+       .resource       = rng_resources,
+};
+
+static void omap_init_rng(void)
+{
+       (void) platform_device_register(&omap4_rng_device);
+}
+
 #else
 static inline void omap_init_rng(void) {}
 #endif
index a16e72c02fa8dbdbdcfc2000694a1341b3e480b0..a628b1f305d90f79296bb1b7bc43b3f5df4a032e 100644 (file)
@@ -43,6 +43,9 @@
 #define AM33XX_TSC_BASE                0x44E0D000
 #define AM33XX_RTC_BASE                0x44E3E000
 
+#define AM33XX_SR0_BASE         0x44E37000
+#define AM33XX_SR1_BASE         0x44E39000
+
 #define AM33XX_ASP0_BASE       0x48038000
 #define AM33XX_ASP1_BASE       0x4803C000
 
 
 #define AM33XX_ELM_BASE                0x48080000
 
+/* Base address for crypto modules */
+#define AM33XX_SHA1MD5_S_BASE  0x53000000
+#define AM33XX_SHA1MD5_P_BASE  0x53100000
+
+#define        AM33XX_AES0_S_BASE      0x53400000
+#define        AM33XX_AES0_P_BASE      0x53500000
+#define        AM33XX_AES1_S_BASE      0x53600000
+#define        AM33XX_AES1_P_BASE      0x53700000
+
+#define        AM33XX_RNG_BASE         0x48310000
+
 #define AM33XX_ASP0_BASE       0x48038000
 #define AM33XX_ASP1_BASE       0x4803C000
 
 #define AM33XX_EPWMSS1_BASE    0x48302000
 #define AM33XX_EPWMSS2_BASE    0x48304000
 
+/*
+ * ----------------------------------------------------------------------------
+ * CPSW
+ * ----------------------------------------------------------------------------
+ */
+#ifndef __ASSEMBLER__
+enum am33xx_cpsw_mac_mode {
+       AM33XX_CPSW_MODE_MII,
+       AM33XX_CPSW_MODE_RMII,
+       AM33XX_CPSW_MODE_RGMII,
+};
+int am33xx_cpsw_init(enum am33xx_cpsw_mac_mode mode, unsigned char *phy_id0,
+                    unsigned char *phy_id1);
+#endif
+
 #endif /* __ASM_ARCH_AM33XX_H */
index 314c1264a493db5c7fa6ba7e6f99a21d742d1216..22a1e66ddf06c97f097a0043038c851c2a45c0bd 100644 (file)
 #define __EMIF_H
 
 #define EMIF_MOD_ID_REV                        (0x0)
-#define EMIF4_0_SDRAM_STATUS            (0x04)
-#define EMIF4_0_SDRAM_CONFIG            (0x08)
-#define EMIF4_0_SDRAM_CONFIG2           (0x0C)
-#define EMIF4_0_SDRAM_REF_CTRL          (0x10)
-#define EMIF4_0_SDRAM_REF_CTRL_SHADOW   (0x14)
-#define EMIF4_0_SDRAM_TIM_1             (0x18)
-#define EMIF4_0_SDRAM_TIM_1_SHADOW      (0x1C)
-#define EMIF4_0_SDRAM_TIM_2             (0x20)
-#define EMIF4_0_SDRAM_TIM_2_SHADOW      (0x24)
-#define EMIF4_0_SDRAM_TIM_3             (0x28)
-#define EMIF4_0_SDRAM_TIM_3_SHADOW      (0x2C)
-#define EMIF4_0_SDRAM_MGMT_CTRL         (0x38)
-#define EMIF4_0_SDRAM_MGMT_CTRL_SHD     (0x3C)
-#define EMIF4_0_DDR_PHY_CTRL_1          (0xE4)
-#define EMIF4_0_DDR_PHY_CTRL_1_SHADOW   (0xE8)
-#define EMIF4_0_DDR_PHY_CTRL_2          (0xEC)
-#define EMIF4_0_IODFT_TLGC              (0x60)
+#define EMIF4_0_SDRAM_STATUS           (0x04)
+#define EMIF4_0_SDRAM_CONFIG           (0x08)
+#define EMIF4_0_SDRAM_CONFIG2          (0x0C)
+#define EMIF4_0_SDRAM_REF_CTRL         (0x10)
+#define EMIF4_0_SDRAM_REF_CTRL_SHADOW  (0x14)
+#define EMIF4_0_SDRAM_TIM_1            (0x18)
+#define EMIF4_0_SDRAM_TIM_1_SHADOW     (0x1C)
+#define EMIF4_0_SDRAM_TIM_2            (0x20)
+#define EMIF4_0_SDRAM_TIM_2_SHADOW     (0x24)
+#define EMIF4_0_SDRAM_TIM_3            (0x28)
+#define E