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raw | patch | inline | side by side (parent: f3bae4c)
raw | patch | inline | side by side (parent: f3bae4c)
author | Ajay Kumar Gupta <ajay.gupta@ti.com> | |
Fri, 18 Nov 2011 06:56:02 +0000 (12:26 +0530) | ||
committer | Vaibhav Hiremath <hvaibhav@ti.com> | |
Mon, 23 Jan 2012 19:14:35 +0000 (00:44 +0530) |
Unable to flush musb Tx endpoint fifo during disconnect while i/o
in progress. The workaround is to set only fifoflush bit and clear
other bits in tx-csr register.
Signed-off-by: Ravi B <ravibabu@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
in progress. The workaround is to set only fifoflush bit and clear
other bits in tx-csr register.
Signed-off-by: Ravi B <ravibabu@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
drivers/usb/musb/musb_host.c | patch | blob | history |
index 5b1f74214623ac3f467090418c54f1235eb21338..509f7385c919a89e6d0c02f08b7f84cd8fa0fe0a 100644 (file)
if (csr != lastcsr)
dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
lastcsr = csr;
- csr |= MUSB_TXCSR_FLUSHFIFO;
+ csr = MUSB_TXCSR_FLUSHFIFO;
musb_writew(epio, MUSB_TXCSR, csr);
csr = musb_readw(epio, MUSB_TXCSR);
+ if (!(csr & MUSB_TXCSR_FIFONOTEMPTY))
+ break;
if (retries-- < 1) {
dev_dbg(musb->controller, "Could not flush host TX%d fifo: csr: %04x\n",
ep->epnum, csr);