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raw | patch | inline | side by side (parent: ef7e409)
raw | patch | inline | side by side (parent: ef7e409)
author | Vaibhav Bedia <vaibhav.bedia@ti.com> | |
Tue, 20 Dec 2011 11:32:38 +0000 (17:02 +0530) | ||
committer | Vaibhav Hiremath <hvaibhav@ti.com> | |
Mon, 23 Jan 2012 19:14:42 +0000 (00:44 +0530) |
Add the base address for mailbox and register
the hwmod for the same
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
the hwmod for the same
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | patch | blob | history | |
arch/arm/plat-omap/include/plat/am33xx.h | patch | blob | history |
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index cd9cadd70d379f2d16366b07b382cfc7b336c9e9..32fb5d90d83f3bed4c25401622e93043b0f64071 100644 (file)
},
};
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors using a
+ * queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
+ .name = "mailbox",
+ .sysc = &am33xx_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod am33xx_mailbox_hwmod;
+static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
+ { .irq = AM33XX_IRQ_MAILBOX },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
+ {
+ .pa_start = AM33XX_MAILBOX0_BASE,
+ .pa_end = AM33XX_MAILBOX0_BASE + (SZ_4K - 1),
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> mailbox */
+static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
+ .master = &am33xx_l4per_hwmod,
+ .slave = &am33xx_mailbox_hwmod,
+ .addr = am33xx_mailbox_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *am33xx_mailbox_slaves[] = {
+ &am33xx_l4_per__mailbox,
+};
+
+static struct omap_hwmod am33xx_mailbox_hwmod = {
+ .name = "mailbox",
+ .class = &am33xx_mailbox_hwmod_class,
+ .clkdm_name = "l4ls_clkdm",
+ .mpu_irqs = am33xx_mailbox_irqs,
+ .main_clk = "mailbox0_fck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .slaves = am33xx_mailbox_slaves,
+ .slaves_cnt = ARRAY_SIZE(am33xx_mailbox_slaves),
+};
+
/* 'mcasp' class */
static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
.name = "mcasp",
&am33xx_icss_hwmod,
/* ieee5000 class */
&am33xx_ieee5000_hwmod,
+ /* mailbox class */
+ &am33xx_mailbox_hwmod,
/* mcasp class */
&am33xx_mcasp0_hwmod,
/* mmc class */
index 475d020560234ae58f30f86b6d4c6f6f02615d52..18b1629da99ba5d8c07a7c890e848574d6345bcb 100644 (file)
#define AM33XX_ASP0_BASE 0x48038000
#define AM33XX_ASP1_BASE 0x4803C000
+#define AM33XX_MAILBOX0_BASE 0x480C8000
+
#define AM33XX_MMC0_BASE 0x48060100
#define AM33XX_MMC1_BASE 0x481D8100
#define AM33XX_MMC2_BASE 0x47810100