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raw | patch | inline | side by side (parent: bd01f0d)
raw | patch | inline | side by side (parent: bd01f0d)
author | Vaibhav Bedia <vaibhav.bedia@ti.com> | |
Tue, 6 Mar 2012 04:53:54 +0000 (10:23 +0530) | ||
committer | Sekhar Nori <nsekhar@ti.com> | |
Fri, 9 Mar 2012 10:14:27 +0000 (15:44 +0530) |
...since it's not available in hardware.
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
arch/arm/mach-omap2/clockdomains33xx_data.c | patch | blob | history |
diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c
index 7d653ce2dd089283ba11d6690c303091a4f9b071..a4734e905e20e65a2467b717e4703b011ac4a050 100644 (file)
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain l3s_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain l4fw_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain l3_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain l4hs_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain ocpwp_l3_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain pruss_ocp_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain cpsw_125mhz_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain lcdc_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain clk_24mhz_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain l4_wkup_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain l3_aon_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain l4_wkup_aon_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain mpu_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain l4_rtc_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain gfx_l3_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain l4_cefuse_am33xx_clkdm = {
.prcm_partition = AM33XX_PRM_PARTITION,
.clkdm_offs = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET,
.clktrctrl_mask = AM33XX_CLKTRCTRL_MASK,
- .flags = CLKDM_CAN_SWSUP,
+ .flags = (CLKDM_CAN_SWSUP | CLKDM_NO_AUTODEPS),
};
static struct clockdomain *clockdomains_am33xx[] __initdata = {