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raw | patch | inline | side by side (parent: 241a659)
raw | patch | inline | side by side (parent: 241a659)
author | Ravi B <ravibabu@ti.com> | |
Tue, 21 Jun 2011 07:00:13 +0000 (12:30 +0530) | ||
committer | Vaibhav Hiremath <hvaibhav@ti.com> | |
Mon, 23 Jan 2012 19:14:17 +0000 (00:44 +0530) |
Signed-off-by: Ravi B <ravibabu@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
index 6a412d2e99d548327a17ed7f4f894a066d9cc325..8da1492d4fdf4ada44e1d45fc760cec4cf5453a9 100644 (file)
struct omap_usb_config *config = pdev->dev.platform_data;
struct clk *dc_clk;
struct clk *hhc_clk;
+ u8 pdev_id;
/* NOTE: "knows" the order of the resources! */
if (!request_mem_region(pdev->resource[0].start,
* use it. Except for OTG, we don't _need_ to talk to one;
* but not having one probably means no VBUS detection.
*/
- xceiv = otg_get_transceiver(0);
+ pdev_id = (pdev->id >= 0) ? pdev->id : 0;
+ xceiv = otg_get_transceiver(pdev_id);
if (xceiv)
type = xceiv->label;
else if (config->otg) {
index f68333e345ed81484dafcb396f15442d55e5ef75..331a03de60049149d3e1241d2318bd3d97b1b64f 100644 (file)
--- a/drivers/usb/musb/am35x.c
+++ b/drivers/usb/musb/am35x.c
#define USB_MENTOR_CORE_OFFSET 0x400
#ifdef CONFIG_USB_TI_CPPI41_DMA
+#define CPPI41_QMGR_REG0SIZE 0x3fff
+
/*
* CPPI 4.1 resources used for USB OTG controller module:
*
cppi41_dma_block[0].sched_table_base = musb->ctrl_base + 0x2800;
/* Initialize for Linking RAM region 0 alone */
- cppi41_queue_mgr_init(cppi_info->q_mgr, 0, 0x3fff);
+ cppi41_queue_mgr_init(cppi_info->q_mgr, 0, CPPI41_QMGR_REG0SIZE);
numch = USB_CPPI41_NUM_CH * 2;
order = get_count_order(numch);
index bc42ac2b73058d31b281fe745a6e887fe68714db..9d42109b7645f528d515b9a50c12ae183b287846 100644 (file)
#define CPPI41_TXDMA_MAXLEN (4 * 1024 * 1024 - 1)
#define CPPI41_RXDMA_MAXLEN (64 * 1024)
+
+/*
+ * Queue Status register
+ */
+#define CPPI41_QSTATUS_REG0 0x90
+#define CPPI41_QSTATUS_REG1 0x94
+#define CPPI41_QSTATUS_REG2 0x98
+#define CPPI41_QSTATUS_REG3 0x9c
+#define CPPI41_QSTATUS_REG4 0xa0
+
/*
* DMA Scheduler - Table Region
*/
index c0c8230ee3e588c7e76492cda5d4fdfa0cc5a2eb..cb4497219d54b3878035dd28fce696c910a99c25 100644 (file)
int offset;
struct musb_hw_ep *hw_ep = musb->endpoints;
- if (musb->config->fifo_mode) {
+ if (musb->config->fifo_mode)
fifo_mode = musb->config->fifo_mode;
- } else if (musb->config->fifo_cfg) {
+ else if (musb->config->fifo_cfg) {
cfg = musb->config->fifo_cfg;
n = musb->config->fifo_cfg_size;
goto done;
index 3724950adcc178fb45d9a8e1f58d10bc3e65d5dd..6fb5a56d3abb68215b4953ca70e4bea1e5e9015d 100644 (file)
/*
- * Texas Instruments TI81XX "glue layer"
+ * Texas Instruments TI81XX "usb platform glue layer"
*
* Copyright (c) 2008, MontaVista Software, Inc. <source@mvista.com>
*
usbss_write(USBSS_IRQ_STATUS, intr_status);
else
printk(KERN_DEBUG "spurious usbss intr\n");
- q_cmpl_status_0 = musb_readl(q_mgr_base, 0x98);
- q_cmpl_status_1 = musb_readl(q_mgr_base, 0x9c);
- q_cmpl_status_2 = musb_readl(q_mgr_base, 0xa0);
+
+ q_cmpl_status_0 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG2);
+ q_cmpl_status_1 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG3);
+ q_cmpl_status_2 = musb_readl(q_mgr_base, CPPI41_QSTATUS_REG4);
/* USB0 tx/rx completion */
/* usb0 tx completion interrupt for ep1..15 */