arm:omap:am33xx: HWMOD updates
authorVaibhav Bedia <vaibhav.bedia@ti.com>
Tue, 20 Dec 2011 11:47:04 +0000 (17:17 +0530)
committerVaibhav Hiremath <hvaibhav@ti.com>
Mon, 23 Jan 2012 19:14:43 +0000 (00:44 +0530)
1. Set the no idle flags for the OCMC to avoid issues in
sram init code which does not explicitly enable the clocks
2. Add reset line info for wkup_m3 and keep the reset asserted

Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
arch/arm/mach-omap2/omap_hwmod_33xx_data.c

index 32fb5d90d83f3bed4c25401622e93043b0f64071..a0b6721bcdbf2e4530bfe0035ac11257c8310185 100644 (file)
@@ -26,6 +26,7 @@
 #include "omap_hwmod_common_data.h"
 #include "control.h"
 #include "cm33xx.h"
+#include "prm33xx.h"
 
 /* Backward references (IPs with Bus Master capability) */
 static struct omap_hwmod am33xx_mpu_hwmod;
@@ -1332,6 +1333,7 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = {
                        .modulemode     = MODULEMODE_SWCTRL,
                },
        },
+       .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 };
 
 /* 'ocpwp' class */
@@ -2431,18 +2433,26 @@ static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
        .name           = "wkup_m3",
 };
 
+static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
+       { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
+};
+
 /* wkup_m3 */
 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
        .name           = "wkup_m3",
        .class          = &am33xx_wkup_m3_hwmod_class,
        .clkdm_name     = "l4_wkup_aon_clkdm",
        .main_clk       = "wkup_m3_fck",
+       .rst_lines      = am33xx_wkup_m3_resets,
+       .rst_lines_cnt  = ARRAY_SIZE(am33xx_wkup_m3_resets),
        .prcm           = {
                .omap4  = {
                        .clkctrl_offs   = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
+                       .rstctrl_offs   = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
                        .modulemode     = MODULEMODE_SWCTRL,
                },
        },
+       .flags          = HWMOD_INIT_NO_RESET,  /* Keep hardreset asserted */
 };
 
 /* L3 SLOW -> USBSS interface */