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raw | patch | inline | side by side (parent: 0f7cb6d)
author | Vaibhav Bedia <vaibhav.bedia@ti.com> | |
Mon, 17 Oct 2011 09:12:11 +0000 (14:42 +0530) | ||
committer | Vaibhav Hiremath <hvaibhav@ti.com> | |
Mon, 23 Jan 2012 19:14:24 +0000 (00:44 +0530) |
FIFO should be flushed before it is enabled for the first time
This fixes the I/O errors reported by the ASoC core on a fresh boot
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
This fixes the I/O errors reported by the ASoC core on a fresh boot
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
sound/soc/davinci/davinci-mcasp.c | patch | blob | history |
index ea1754e2eff4c9915f35fa010c0204e540c775ba..9dfcb1e977bcf788939d5ecb15adcdf1de948409 100644 (file)
static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
{
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
- if (dev->txnumevt) { /* enable FIFO */
- if (dev->version == MCASP_VERSION_3)
- mcasp_set_bits(dev->base +
- MCASP_VER3_WFIFOCTL,
- FIFO_ENABLE);
- else
- mcasp_set_bits(dev->base +
- DAVINCI_MCASP_WFIFOCTL,
- FIFO_ENABLE);
+ if (dev->txnumevt) { /* flush and enable FIFO */
+ if (dev->version == MCASP_VERSION_3) {
+ mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
+ FIFO_ENABLE);
+ mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
+ FIFO_ENABLE);
+ } else {
+ mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
+ FIFO_ENABLE);
+ mcasp_set_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
+ FIFO_ENABLE);
+ }
}
mcasp_start_tx(dev);
} else {
- if (dev->rxnumevt) { /* enable FIFO */
- if (dev->version == MCASP_VERSION_3)
- mcasp_set_bits(dev->base +
- MCASP_VER3_WFIFOCTL,
- FIFO_ENABLE);
- else
- mcasp_set_bits(dev->base +
- DAVINCI_MCASP_RFIFOCTL,
- FIFO_ENABLE);
+ if (dev->rxnumevt) { /* flush and enable FIFO */
+ if (dev->version == MCASP_VERSION_3) {
+ mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
+ FIFO_ENABLE);
+ mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
+ FIFO_ENABLE);
+ } else {
+ mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
+ FIFO_ENABLE);
+ mcasp_set_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
+ FIFO_ENABLE);
+ }
}
mcasp_start_rx(dev);
}
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
if (dev->txnumevt) { /* disable FIFO */
if (dev->version == MCASP_VERSION_3)
- mcasp_clr_bits(dev->base +
- MCASP_VER3_WFIFOCTL,
+ mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
FIFO_ENABLE);
else
- mcasp_clr_bits(dev->base +
- DAVINCI_MCASP_WFIFOCTL,
+ mcasp_clr_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
FIFO_ENABLE);
}
mcasp_stop_tx(dev);
} else {
if (dev->rxnumevt) { /* disable FIFO */
if (dev->version == MCASP_VERSION_3)
- mcasp_clr_bits(dev->base +
- MCASP_VER3_RFIFOCTL,
+ mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
FIFO_ENABLE);
else
- mcasp_clr_bits(dev->base +
- DAVINCI_MCASP_RFIFOCTL,
+ mcasp_clr_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
FIFO_ENABLE);
}
mcasp_stop_rx(dev);