From: Patil, Rachna Date: Mon, 23 Jan 2012 11:26:59 +0000 (+0530) Subject: arm: omap: am33xx: update TSC hwmod data X-Git-Url: https://git.ti.com/gitweb?p=sitara-epos%2Fsitara-epos-kernel.git;a=commitdiff_plain;h=0e82a6b311ae038dc03f5291c93b42747762dbd7 arm: omap: am33xx: update TSC hwmod data Sysconfig register bits are updated for TSC hwmod. TSC supports idle mode at bit position 2&3, hence following omap4 IP's. Signed-off-by: Patil, Rachna --- diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index f9b91fa98851..77030e41a358 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -277,8 +277,18 @@ static struct omap_hwmod am33xx_l4wkup_hwmod = { }; /* 'adc_tsc' class */ +static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x10, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | + SIDLE_SMART | SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = { .name = "adc_tsc", + .sysc = &am33xx_adc_tsc_sysc, }; /* adc_tsc */